SE520115C2 - Diken med plan ovansida - Google Patents

Diken med plan ovansida

Info

Publication number
SE520115C2
SE520115C2 SE9701154A SE9701154A SE520115C2 SE 520115 C2 SE520115 C2 SE 520115C2 SE 9701154 A SE9701154 A SE 9701154A SE 9701154 A SE9701154 A SE 9701154A SE 520115 C2 SE520115 C2 SE 520115C2
Authority
SE
Sweden
Prior art keywords
trench
insulating layer
polysilicon
insulating
layer
Prior art date
Application number
SE9701154A
Other languages
English (en)
Swedish (sv)
Other versions
SE9701154L (sv
SE9701154D0 (sv
Inventor
Anders Karl Sivert Soederbaerg
Nils Ola Oegren
Ernst Haakan Sjoedin
Olof Mikael Zackrisson
Original Assignee
Ericsson Telefon Ab L M
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ericsson Telefon Ab L M filed Critical Ericsson Telefon Ab L M
Priority to SE9701154A priority Critical patent/SE520115C2/sv
Publication of SE9701154D0 publication Critical patent/SE9701154D0/xx
Priority to TW086105057A priority patent/TW356579B/zh
Priority to KR10-1999-7008655A priority patent/KR100374455B1/ko
Priority to EP98912851A priority patent/EP1018156A1/fr
Priority to JP54556198A priority patent/JP2001519097A/ja
Priority to PCT/SE1998/000528 priority patent/WO1998043293A1/fr
Priority to CA002285627A priority patent/CA2285627A1/fr
Priority to AU67539/98A priority patent/AU6753998A/en
Priority to CN98805442A priority patent/CN1110848C/zh
Publication of SE9701154L publication Critical patent/SE9701154L/
Publication of SE520115C2 publication Critical patent/SE520115C2/sv

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/041—Manufacture or treatment of isolation regions comprising polycrystalline semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/40—Isolation regions comprising polycrystalline semiconductor materials

Landscapes

  • Element Separation (AREA)
  • Drying Of Semiconductors (AREA)
SE9701154A 1997-03-26 1997-03-26 Diken med plan ovansida SE520115C2 (sv)

Priority Applications (9)

Application Number Priority Date Filing Date Title
SE9701154A SE520115C2 (sv) 1997-03-26 1997-03-26 Diken med plan ovansida
TW086105057A TW356579B (en) 1997-03-26 1997-04-18 Planar trenches
CN98805442A CN1110848C (zh) 1997-03-26 1998-03-23 在半导体衬底中制造平面绝缘沟槽的方法
JP54556198A JP2001519097A (ja) 1997-03-26 1998-03-23 プレーナトレンチの製造方法
EP98912851A EP1018156A1 (fr) 1997-03-26 1998-03-23 Procede de production des sillons plats
KR10-1999-7008655A KR100374455B1 (ko) 1997-03-26 1998-03-23 평면 트렌치의 제조 방법
PCT/SE1998/000528 WO1998043293A1 (fr) 1997-03-26 1998-03-23 Procede de production des sillons plats
CA002285627A CA2285627A1 (fr) 1997-03-26 1998-03-23 Procede de production des sillons plats
AU67539/98A AU6753998A (en) 1997-03-26 1998-03-23 Method for producing planar trenches

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SE9701154A SE520115C2 (sv) 1997-03-26 1997-03-26 Diken med plan ovansida

Publications (3)

Publication Number Publication Date
SE9701154D0 SE9701154D0 (sv) 1997-03-26
SE9701154L SE9701154L (sv) 1998-09-27
SE520115C2 true SE520115C2 (sv) 2003-05-27

Family

ID=20406360

Family Applications (1)

Application Number Title Priority Date Filing Date
SE9701154A SE520115C2 (sv) 1997-03-26 1997-03-26 Diken med plan ovansida

Country Status (9)

Country Link
EP (1) EP1018156A1 (fr)
JP (1) JP2001519097A (fr)
KR (1) KR100374455B1 (fr)
CN (1) CN1110848C (fr)
AU (1) AU6753998A (fr)
CA (1) CA2285627A1 (fr)
SE (1) SE520115C2 (fr)
TW (1) TW356579B (fr)
WO (1) WO1998043293A1 (fr)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6498383B2 (en) * 2001-05-23 2002-12-24 International Business Machines Corporation Oxynitride shallow trench isolation and method of formation
US6461936B1 (en) * 2002-01-04 2002-10-08 Infineon Technologies Ag Double pullback method of filling an isolation trench
JP2008028357A (ja) 2006-07-24 2008-02-07 Hynix Semiconductor Inc 半導体素子及びその製造方法
JP4717122B2 (ja) * 2009-01-13 2011-07-06 三菱電機株式会社 薄膜太陽電池の製造方法
CN102468176B (zh) * 2010-11-19 2013-12-18 上海华虹Nec电子有限公司 超级结器件制造纵向区的方法
CN103822735A (zh) * 2012-11-16 2014-05-28 无锡华润上华半导体有限公司 一种压力传感器用晶片结构及该晶片结构的加工方法
CN107507773B (zh) * 2016-06-14 2021-09-17 格科微电子（上海）有限公司 优化cmos图像传感器晶体管结构的方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2207281B (en) * 1987-07-24 1992-02-05 Plessey Co Plc A method of providing refilled trenches
US5175122A (en) * 1991-06-28 1992-12-29 Digital Equipment Corporation Planarization process for trench isolation in integrated circuit manufacture
US5561073A (en) * 1992-03-13 1996-10-01 Jerome; Rick C. Method of fabricating an isolation trench for analog bipolar devices in harsh environments
US5627092A (en) * 1994-09-26 1997-05-06 Siemens Aktiengesellschaft Deep trench dram process on SOI for low leakage DRAM cell
US5683945A (en) * 1996-05-16 1997-11-04 Siemens Aktiengesellschaft Uniform trench fill recess by means of isotropic etching

Also Published As

Publication number Publication date
CN1110848C (zh) 2003-06-04
KR100374455B1 (ko) 2003-03-04
AU6753998A (en) 1998-10-20
CA2285627A1 (fr) 1998-10-01
WO1998043293A1 (fr) 1998-10-01
TW356579B (en) 1999-04-21
EP1018156A1 (fr) 2000-07-12
SE9701154L (sv) 1998-09-27
SE9701154D0 (sv) 1997-03-26
CN1257609A (zh) 2000-06-21
JP2001519097A (ja) 2001-10-16
KR20010005591A (ko) 2001-01-15

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