SG100732A1 - Programmable delay control in a memory - Google Patents

Programmable delay control in a memory

Info

Publication number
SG100732A1
SG100732A1 SG200103540A SG200103540A SG100732A1 SG 100732 A1 SG100732 A1 SG 100732A1 SG 200103540 A SG200103540 A SG 200103540A SG 200103540 A SG200103540 A SG 200103540A SG 100732 A1 SG100732 A1 SG 100732A1
Authority
SG
Singapore
Prior art keywords
memory
delay control
programmable delay
programmable
control
Prior art date
Application number
SG200103540A
Other languages
English (en)
Inventor
Ray Chang
William R Weier
Richard Y Wong
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of SG100732A1 publication Critical patent/SG100732A1/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/023—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in clock generator or timing circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/026—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in sense amplifiers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/131—Digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Dram (AREA)
SG200103540A 1999-03-01 1999-09-15 Programmable delay control in a memory SG100732A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/259,454 US6111796A (en) 1999-03-01 1999-03-01 Programmable delay control for sense amplifiers in a memory

Publications (1)

Publication Number Publication Date
SG100732A1 true SG100732A1 (en) 2003-12-26

Family

ID=22985023

Family Applications (2)

Application Number Title Priority Date Filing Date
SG200103540A SG100732A1 (en) 1999-03-01 1999-09-15 Programmable delay control in a memory
SG9904489A SG103248A1 (en) 1999-03-01 1999-09-15 Programmable delay control in a memory

Family Applications After (1)

Application Number Title Priority Date Filing Date
SG9904489A SG103248A1 (en) 1999-03-01 1999-09-15 Programmable delay control in a memory

Country Status (8)

Country Link
US (2) US6111796A (de)
EP (3) EP1770710B1 (de)
JP (2) JP4445074B2 (de)
KR (1) KR100665484B1 (de)
CN (1) CN1265509B (de)
DE (1) DE69942354D1 (de)
SG (2) SG100732A1 (de)
TW (1) TW440869B (de)

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US7157952B2 (en) * 2004-08-20 2007-01-02 L-3 Integrated Systems Company Systems and methods for implementing delay line circuitry
EP1630815B1 (de) * 2004-08-24 2011-10-05 Infineon Technologies AG Speicherschaltung mit spannungsversorgungsnachgebiegkeit und einer an spannunasversorgung angepassten leistung
KR100613073B1 (ko) 2004-09-21 2006-08-16 주식회사 하이닉스반도체 센스 앰프 오버드라이브 회로
KR100609621B1 (ko) 2005-07-19 2006-08-08 삼성전자주식회사 메모리 블락별로 레이턴시 제어가 가능한 동기식 반도체메모리 장치
US7215585B2 (en) * 2005-09-01 2007-05-08 Micron Technology, Inc. Method and apparatus for synchronizing data from memory arrays
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KR100824779B1 (ko) * 2007-01-11 2008-04-24 삼성전자주식회사 반도체 메모리 장치의 데이터 출력 경로 및 데이터 출력방법
KR100889311B1 (ko) * 2007-02-23 2009-03-18 주식회사 하이닉스반도체 비트라인 감지증폭기를 포함하는 반도체메모리소자
JP5102800B2 (ja) 2009-04-15 2012-12-19 インターナショナル・ビジネス・マシーンズ・コーポレーション 半導体記憶装置
KR20110025487A (ko) * 2009-09-04 2011-03-10 삼성전자주식회사 반도체 메모리 장치
JP5471761B2 (ja) * 2010-04-15 2014-04-16 富士通株式会社 受信回路
US9201096B2 (en) 2010-09-08 2015-12-01 Dcg Systems, Inc. Laser-assisted device alteration using synchronized laser pulses
JP5579580B2 (ja) * 2010-11-12 2014-08-27 ピーエスフォー ルクスコ エスエイアールエル 半導体装置
US8400852B2 (en) * 2011-03-04 2013-03-19 Taiwan Semiconductor Manufacturing Company, Ltd. Circuit with remote amplifier
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US8879303B2 (en) * 2013-01-03 2014-11-04 Lsi Corporation Pre-charge tracking of global read lines in high speed SRAM
US11209985B2 (en) * 2019-04-23 2021-12-28 Macronix International Co., Ltd. Input/output delay optimization method, electronic system and memory device using the same
CN112069768B (zh) * 2020-09-08 2024-07-16 飞腾信息技术有限公司 一种针对双端口sram输入输出延时优化的方法
KR102692866B1 (ko) * 2021-04-26 2024-08-08 한국전자통신연구원 컴퓨팅 자원 분할 운용 방법 및 장치
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Also Published As

Publication number Publication date
CN1265509B (zh) 2010-10-27
KR100665484B1 (ko) 2007-01-10
US6111796A (en) 2000-08-29
EP1033721A2 (de) 2000-09-06
JP4903847B2 (ja) 2012-03-28
EP1033721B1 (de) 2017-03-15
TW440869B (en) 2001-06-16
EP1770710A2 (de) 2007-04-04
US6385101B1 (en) 2002-05-07
KR20000062133A (ko) 2000-10-25
EP1770710A3 (de) 2007-07-04
EP1770710B1 (de) 2010-05-05
JP2000251472A (ja) 2000-09-14
SG103248A1 (en) 2004-04-29
EP1770708A2 (de) 2007-04-04
EP1770708A3 (de) 2007-07-04
EP1770708B1 (de) 2012-11-14
DE69942354D1 (de) 2010-06-17
CN1265509A (zh) 2000-09-06
JP2010003406A (ja) 2010-01-07
EP1033721A3 (de) 2000-10-25
JP4445074B2 (ja) 2010-04-07

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