SG105533A1 - Memory transfer controller and method of transfer control of video line data and macroblock data - Google Patents

Memory transfer controller and method of transfer control of video line data and macroblock data

Info

Publication number
SG105533A1
SG105533A1 SG200200600A SG200200600A SG105533A1 SG 105533 A1 SG105533 A1 SG 105533A1 SG 200200600 A SG200200600 A SG 200200600A SG 200200600 A SG200200600 A SG 200200600A SG 105533 A1 SG105533 A1 SG 105533A1
Authority
SG
Singapore
Prior art keywords
data
video line
transfer control
line data
macroblock
Prior art date
Application number
SG200200600A
Other languages
English (en)
Inventor
Yin Patricia Chiang Wei
Y W Hui Lucas
Original Assignee
St Microelectronics Asia
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by St Microelectronics Asia filed Critical St Microelectronics Asia
Priority to SG200200600A priority Critical patent/SG105533A1/en
Priority to US10/356,719 priority patent/US7126992B2/en
Priority to DE60312417T priority patent/DE60312417D1/de
Priority to EP03001949A priority patent/EP1333683B1/de
Publication of SG105533A1 publication Critical patent/SG105533A1/en
Priority to US11/461,611 priority patent/US9100653B2/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H04N19/423—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/60—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
    • H04N19/61—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Compression Or Coding Systems Of Tv Signals (AREA)
SG200200600A 2002-01-30 2002-01-31 Memory transfer controller and method of transfer control of video line data and macroblock data SG105533A1 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
SG200200600A SG105533A1 (en) 2002-01-31 2002-01-31 Memory transfer controller and method of transfer control of video line data and macroblock data
US10/356,719 US7126992B2 (en) 2002-01-31 2003-01-30 Memory transfer controller and method of transfer control of video line data and macroblock data
DE60312417T DE60312417D1 (de) 2002-01-31 2003-01-30 Verfahren und Vorrichtung zur Speicherübertragungssteuerung von Videoliniendaten und Makroblockdaten
EP03001949A EP1333683B1 (de) 2002-01-31 2003-01-30 Verfahren und Vorrichtung zur Speicherübertragungssteuerung von Videoliniendaten und Makroblockdaten
US11/461,611 US9100653B2 (en) 2002-01-30 2006-08-01 Memory transfer controller and method of transfer control of video line data and macroblock data

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SG200200600A SG105533A1 (en) 2002-01-31 2002-01-31 Memory transfer controller and method of transfer control of video line data and macroblock data

Publications (1)

Publication Number Publication Date
SG105533A1 true SG105533A1 (en) 2004-08-27

Family

ID=20430897

Family Applications (1)

Application Number Title Priority Date Filing Date
SG200200600A SG105533A1 (en) 2002-01-30 2002-01-31 Memory transfer controller and method of transfer control of video line data and macroblock data

Country Status (4)

Country Link
US (2) US7126992B2 (de)
EP (1) EP1333683B1 (de)
DE (1) DE60312417D1 (de)
SG (1) SG105533A1 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8428349B2 (en) 2003-05-21 2013-04-23 Broadcom Corporation Method and apparatus for DRAM 2D video word formatting
JP4909779B2 (ja) * 2006-04-17 2012-04-04 パナソニック株式会社 画像データ転送方法、画像処理装置、及び撮像システム
KR100817057B1 (ko) * 2006-08-30 2008-03-26 삼성전자주식회사 동일한 픽셀 데이터 그룹에 포함되는 픽셀 데이터들을메모리의 동일한 뱅크 어드레스로 매핑하는 매핑 방법 및비디오 시스템
US8583692B2 (en) 2009-04-30 2013-11-12 Oracle International Corporation DDL and DML support for hybrid columnar compressed tables
US8296517B2 (en) 2009-08-19 2012-10-23 Oracle International Corporation Database operation-aware striping technique
US9179156B2 (en) * 2011-11-10 2015-11-03 Intel Corporation Memory controller for video analytics and encoding
CN104025028B (zh) * 2011-12-28 2018-12-04 英特尔公司 在视频分析中的视频编码
US10628894B1 (en) 2015-01-28 2020-04-21 Intuit Inc. Method and system for providing personalized responses to questions received from a user of an electronic tax return preparation system
US10937109B1 (en) 2016-01-08 2021-03-02 Intuit Inc. Method and technique to calculate and provide confidence score for predicted tax due/refund

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6330644B1 (en) * 1994-10-27 2001-12-11 Canon Kabushiki Kaisha Signal processor with a plurality of kinds of processors and a shared memory accessed through a versatile control means
US5581310A (en) 1995-01-26 1996-12-03 Hitachi America, Ltd. Architecture for a high definition video frame memory and an accompanying data organization for use therewith and efficient access therefrom
FR2745650B1 (fr) 1996-02-29 1998-05-22 Sgs Thomson Microelectronics Adressage d'une zone memoire d'un decodeur mpeg
US5883670A (en) * 1996-08-02 1999-03-16 Avid Technology, Inc. Motion video processing circuit for capture playback and manipulation of digital motion video information on a computer
US6028612A (en) 1997-11-18 2000-02-22 Stmicroelectronics, Inc. Picture memory mapping to minimize memory bandwidth in compression and decompression of data sequences
US6104416A (en) * 1997-11-18 2000-08-15 Stmicroelectronics, Inc. Tiling in picture memory mapping to minimize memory bandwidth in compression and decompression of data sequences
US6205181B1 (en) * 1998-03-10 2001-03-20 Chips & Technologies, Llc Interleaved strip data storage system for video processing
IL129345A (en) * 1999-04-06 2004-05-12 Broadcom Corp Video encoding and video/audio/data multiplexing device

Also Published As

Publication number Publication date
DE60312417D1 (de) 2007-04-26
EP1333683A3 (de) 2004-06-16
US7126992B2 (en) 2006-10-24
US20030169371A1 (en) 2003-09-11
US9100653B2 (en) 2015-08-04
EP1333683B1 (de) 2007-03-14
US20070121730A1 (en) 2007-05-31
EP1333683A2 (de) 2003-08-06

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