SG11201803662SA - Method for synchronising data converters by means of a signal transmitted from one to the next - Google Patents

Method for synchronising data converters by means of a signal transmitted from one to the next

Info

Publication number
SG11201803662SA
SG11201803662SA SG11201803662SA SG11201803662SA SG11201803662SA SG 11201803662S A SG11201803662S A SG 11201803662SA SG 11201803662S A SG11201803662S A SG 11201803662SA SG 11201803662S A SG11201803662S A SG 11201803662SA SG 11201803662S A SG11201803662S A SG 11201803662SA
Authority
SG
Singapore
Prior art keywords
converters
synchronizing
converter
clock
signal transmitted
Prior art date
Application number
SG11201803662SA
Other languages
English (en)
Inventor
Etienne Bouin
Rémi Laube
Jérôme Ligozat
Marc Stackler
Original Assignee
Teledyne E2V Semiconductors Sas
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Teledyne E2V Semiconductors Sas filed Critical Teledyne E2V Semiconductors Sas
Publication of SG11201803662SA publication Critical patent/SG11201803662SA/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/153—Arrangements in which a pulse is delivered at the instant when a predetermined characteristic of an input signal is present or at a fixed time interval after this instant
    • H03K5/1534—Transition or edge detectors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
    • H03M1/0624—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by synchronisation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/1205—Multiplexed conversion systems
    • H03M1/123—Simultaneous, i.e. using one converter per channel but with common control or reference circuits for multiple converters
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00234—Layout of the delay element using circuits having two logic levels
    • H03K2005/00267—Layout of the delay element using circuits having two logic levels using D/A or A/D converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/1205—Multiplexed conversion systems
    • H03M1/121—Interleaved, i.e. using multiple converters or converter parts for one channel
    • H03M1/1215—Interleaved, i.e. using multiple converters or converter parts for one channel using time-division multiplexing

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Analogue/Digital Conversion (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
SG11201803662SA 2015-11-10 2016-11-04 Method for synchronising data converters by means of a signal transmitted from one to the next SG11201803662SA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1560739A FR3043477B1 (fr) 2015-11-10 2015-11-10 Procede de synchronisation de convertisseurs de donnees par un signal transmis de proche en proche
PCT/EP2016/076689 WO2017080925A1 (fr) 2015-11-10 2016-11-04 Procede de synchronisation de convertisseurs de donnees par un signal transmis de proche en proche

Publications (1)

Publication Number Publication Date
SG11201803662SA true SG11201803662SA (en) 2018-06-28

Family

ID=55361644

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201803662SA SG11201803662SA (en) 2015-11-10 2016-11-04 Method for synchronising data converters by means of a signal transmitted from one to the next

Country Status (11)

Country Link
US (1) US10320406B2 (fr)
EP (1) EP3375092B1 (fr)
JP (1) JP6898319B2 (fr)
KR (1) KR102559701B1 (fr)
CN (1) CN108352829B (fr)
AU (1) AU2016354402B2 (fr)
CA (1) CA3004791C (fr)
FR (1) FR3043477B1 (fr)
SG (1) SG11201803662SA (fr)
TW (1) TWI690161B (fr)
WO (1) WO2017080925A1 (fr)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7193110B2 (ja) * 2018-07-27 2022-12-20 ザインエレクトロニクス株式会社 複数レーン・シリアライザ装置
FR3094593B1 (fr) * 2019-03-29 2021-02-19 Teledyne E2V Semiconductors Sas Procédé de synchronisation de données numériques envoyées en série
FR3100068B1 (fr) * 2019-08-20 2021-07-16 Teledyne E2V Semiconductors Sas Procédé de synchronisation de données analogiques en sortie d’une pluralité de convertisseurs numérique/analogique
CN110445492B (zh) * 2019-09-09 2023-04-07 Oppo广东移动通信有限公司 跨时钟域分频时钟保护电路、分频电路、方法及终端设备
FR3111249B1 (fr) 2020-06-09 2023-12-22 Teledyne E2V Semiconductors Sas Procédé de synchronisation de convertisseurs de type analogique-numérique ou numérique-analogique, et système correspondant.
JP7158632B2 (ja) * 2020-07-22 2022-10-21 三菱電機株式会社 スレーブ装置、中継装置、マスタスレーブシステム、スレーブ制御方法、スレーブ制御プログラム、中継方法、及び、中継プログラム
CN113381831A (zh) * 2021-05-12 2021-09-10 聚融医疗科技(杭州)有限公司 多片fpga的收发同步方法、系统和超声控制设备
PL248220B1 (pl) * 2022-07-22 2025-11-12 Siec Badawcza Lukasiewicz Inst Tele I Radiotechniczny Urządzenie do zbierania i przetwarzania próbek cyfrowych sygnału analogowego z synchronizacją momentu próbkowania do sygnału zewnętrznego
FR3140231B1 (fr) 2022-09-22 2024-10-04 Teledyne E2V Semiconductors Sas Procédé de détermination du déphasage entre un premier signal d’horloge reçu par un premier composant électronique et un deuxième signal d’horloge reçu par un deuxième composant électronique

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US5436628A (en) * 1993-09-13 1995-07-25 Intel Corporation Programmable frequency timing generator with phase adjust
FR2746987A1 (fr) * 1996-03-29 1997-10-03 Philips Electronics Nv Convertisseur analogique/numerique a frequence d'echantillonnage elevee
JP2985957B1 (ja) * 1998-09-11 1999-12-06 松下電器産業株式会社 位相比較器及びデジタル式位相同期回路
JP3657188B2 (ja) * 2000-10-31 2005-06-08 Ｎｅｃエレクトロニクス株式会社 装置及びその動作方法
JP2002232402A (ja) * 2001-02-07 2002-08-16 Toyo Commun Equip Co Ltd クロック信号の自動位相反転回路
US6836852B2 (en) * 2001-10-29 2004-12-28 Agilent Technologies, Inc. Method for synchronizing multiple serial data streams using a plurality of clock signals
DE102004050648A1 (de) * 2004-10-18 2006-04-20 Rohde & Schwarz Gmbh & Co. Kg Anordnung zur synchronen Ausgabe von in zwei oder mehr Digitale/Analog-Wandlern erzeugten Analogsignalen
US7328299B2 (en) * 2004-11-23 2008-02-05 Atmel Corporation Interface for compressed data transfer between host system and parallel data processing system
CN101098220B (zh) * 2006-06-29 2010-08-18 中兴通讯股份有限公司 一种基于数字锁相环的时钟同步方法及其系统
CN101546207B (zh) * 2008-03-28 2011-08-10 盛群半导体股份有限公司 时钟信号切换电路
EP2198519A4 (fr) * 2008-06-06 2012-10-31 Lsi Corp Systèmes et procédés de conversion analogique-numérique recalée synchrone
US7728753B2 (en) * 2008-10-13 2010-06-01 National Semiconductor Corporation Continuous synchronization for multiple ADCs
CN102495912B (zh) * 2011-10-26 2013-11-20 电子科技大学 一种具有同步校正功能的多通道高速数据采集系统
JP2014017590A (ja) * 2012-07-06 2014-01-30 Fujitsu Ltd 電子回路及び通信方法
US9037893B2 (en) * 2013-03-15 2015-05-19 Analog Devices, Inc. Synchronizing data transfer from a core to a physical interface
WO2015162763A1 (fr) * 2014-04-24 2015-10-29 三菱電機株式会社 Système de réseau
JP6213538B2 (ja) * 2015-09-24 2017-10-18 横河電機株式会社 信号処理回路

Also Published As

Publication number Publication date
CN108352829B (zh) 2022-02-25
CA3004791A1 (fr) 2017-05-18
KR20180079339A (ko) 2018-07-10
EP3375092A1 (fr) 2018-09-19
AU2016354402A1 (en) 2018-06-21
CA3004791C (fr) 2023-12-12
FR3043477A1 (fr) 2017-05-12
US10320406B2 (en) 2019-06-11
US20180323794A1 (en) 2018-11-08
FR3043477B1 (fr) 2017-11-24
JP2018537031A (ja) 2018-12-13
JP6898319B2 (ja) 2021-07-07
EP3375092B1 (fr) 2019-09-04
TW201740683A (zh) 2017-11-16
AU2016354402B2 (en) 2020-11-19
TWI690161B (zh) 2020-04-01
KR102559701B1 (ko) 2023-07-25
CN108352829A (zh) 2018-07-31
WO2017080925A1 (fr) 2017-05-18

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