SG131025A1 - Integrated circuit including silicon wafer with annealed glass paste - Google Patents
Integrated circuit including silicon wafer with annealed glass pasteInfo
- Publication number
- SG131025A1 SG131025A1 SG200605916-6A SG2006059166A SG131025A1 SG 131025 A1 SG131025 A1 SG 131025A1 SG 2006059166 A SG2006059166 A SG 2006059166A SG 131025 A1 SG131025 A1 SG 131025A1
- Authority
- SG
- Singapore
- Prior art keywords
- integrated circuit
- glass paste
- silicon wafer
- circuit including
- layer
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
- H10W74/124—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed the encapsulations having cavities other than that occupied by chips
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
- H10W74/121—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/40—Encapsulations, e.g. protective coatings characterised by their materials
- H10W74/43—Encapsulations, e.g. protective coatings characterised by their materials comprising oxides, nitrides or carbides, e.g. ceramics or glasses
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/5445—Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/931—Shapes of bond pads
- H10W72/932—Plan-view shape, i.e. in top view
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Die Bonding (AREA)
- Oscillators With Electromechanical Resonators (AREA)
- Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (9)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US71445405P | 2005-09-06 | 2005-09-06 | |
| US73056805P | 2005-10-27 | 2005-10-27 | |
| US75682806P | 2006-01-06 | 2006-01-06 | |
| US11/328,979 US20060113639A1 (en) | 2002-10-15 | 2006-01-10 | Integrated circuit including silicon wafer with annealed glass paste |
| US11/487,077 US7253495B2 (en) | 2002-10-15 | 2006-07-14 | Integrated circuit package with air gap |
| US11/486,898 US7812683B2 (en) | 2002-10-15 | 2006-07-14 | Integrated circuit package with glass layer and oscillator |
| US11/486,557 US20060267194A1 (en) | 2002-10-15 | 2006-07-14 | Integrated circuit package with air gap |
| US11/486,945 US7301408B2 (en) | 2002-10-15 | 2006-07-14 | Integrated circuit with low dielectric loss packaging material |
| US11/486,944 US20060262623A1 (en) | 2002-10-15 | 2006-07-14 | Phase locked loop with temperature compensation |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| SG131025A1 true SG131025A1 (en) | 2007-04-26 |
Family
ID=37103167
Family Applications (3)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| SG200605916-6A SG131025A1 (en) | 2005-09-06 | 2006-08-31 | Integrated circuit including silicon wafer with annealed glass paste |
| SG200605918-2A SG131026A1 (en) | 2005-09-06 | 2006-08-31 | Integrated circuit including silicon wafer with annealed glass paste |
| SG200605915-8A SG131024A1 (en) | 2005-09-06 | 2006-08-31 | Integrated circuit including silcon wafer with annealed glass paste |
Family Applications After (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| SG200605918-2A SG131026A1 (en) | 2005-09-06 | 2006-08-31 | Integrated circuit including silicon wafer with annealed glass paste |
| SG200605915-8A SG131024A1 (en) | 2005-09-06 | 2006-08-31 | Integrated circuit including silcon wafer with annealed glass paste |
Country Status (2)
| Country | Link |
|---|---|
| EP (1) | EP1760780A3 (de) |
| SG (3) | SG131025A1 (de) |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4835778A (de) * | 1971-09-09 | 1973-05-26 | ||
| JPH06314756A (ja) * | 1993-04-27 | 1994-11-08 | Sony Corp | 半導体製造方法 |
| US6323550B1 (en) * | 1995-06-06 | 2001-11-27 | Analog Devices, Inc. | Package for sealing an integrated circuit die |
| JP2001227902A (ja) * | 2000-02-16 | 2001-08-24 | Mitsubishi Electric Corp | 半導体装置 |
| US20020180032A1 (en) * | 2001-05-29 | 2002-12-05 | Agere Systems Inc. | Package for reducing cross-talk between devices on a device substrate and a method of manufacture therefor |
| SG99386A1 (en) * | 2002-01-29 | 2003-10-27 | Sensfab Pte Ltd | Method of manufacturing an accelerometer |
| JP2005109221A (ja) * | 2003-09-30 | 2005-04-21 | Toshiba Corp | ウェーハレベルパッケージ及びその製造方法 |
-
2006
- 2006-08-30 EP EP06018104.7A patent/EP1760780A3/de not_active Withdrawn
- 2006-08-31 SG SG200605916-6A patent/SG131025A1/en unknown
- 2006-08-31 SG SG200605918-2A patent/SG131026A1/en unknown
- 2006-08-31 SG SG200605915-8A patent/SG131024A1/en unknown
Also Published As
| Publication number | Publication date |
|---|---|
| EP1760780A3 (de) | 2013-05-15 |
| SG131024A1 (en) | 2007-04-26 |
| SG131026A1 (en) | 2007-04-26 |
| EP1760780A2 (de) | 2007-03-07 |
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