SG46285A1 - Input buffer circuit having sleep mode and bus hold function - Google Patents

Input buffer circuit having sleep mode and bus hold function

Info

Publication number
SG46285A1
SG46285A1 SG1996002128A SG1996002128A SG46285A1 SG 46285 A1 SG46285 A1 SG 46285A1 SG 1996002128 A SG1996002128 A SG 1996002128A SG 1996002128 A SG1996002128 A SG 1996002128A SG 46285 A1 SG46285 A1 SG 46285A1
Authority
SG
Singapore
Prior art keywords
sleep mode
buffer circuit
input buffer
hold function
bus hold
Prior art date
Application number
SG1996002128A
Other languages
English (en)
Inventor
Carlos D Obregon
Michael A Wells
Eric D Neely
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of SG46285A1 publication Critical patent/SG46285A1/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
SG1996002128A 1993-04-30 1994-03-31 Input buffer circuit having sleep mode and bus hold function SG46285A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/054,495 US5432462A (en) 1993-04-30 1993-04-30 Input buffer circuit having sleep mode and bus hold function

Publications (1)

Publication Number Publication Date
SG46285A1 true SG46285A1 (en) 1998-02-20

Family

ID=21991487

Family Applications (1)

Application Number Title Priority Date Filing Date
SG1996002128A SG46285A1 (en) 1993-04-30 1994-03-31 Input buffer circuit having sleep mode and bus hold function

Country Status (4)

Country Link
US (1) US5432462A (fr)
EP (1) EP0622903A3 (fr)
JP (1) JPH06350431A (fr)
SG (1) SG46285A1 (fr)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE59510974D1 (de) * 1995-03-30 2004-12-30 Texas Instruments Deutschland Bus-Treiberschaltung
US5656951A (en) * 1996-02-05 1997-08-12 Motorola, Inc. Input circuit and method for holding data in mixed power supply mode
US5973530A (en) * 1998-05-29 1999-10-26 Lucent Technologies Inc. Low power, high voltage-tolerant bus holder circuit in low voltage technology
US6150845A (en) * 1999-06-01 2000-11-21 Fairchild Semiconductor Corp. Bus hold circuit with overvoltage tolerance
US7725748B1 (en) 2000-12-29 2010-05-25 Intel Corporation Low power subsystem for portable computers
US7058829B2 (en) * 2002-08-14 2006-06-06 Intel Corporation Method and apparatus for a computing system having an active sleep mode CPU that uses the cache of a normal active mode CPU
US7117379B2 (en) * 2002-08-14 2006-10-03 Intel Corporation Method and apparatus for a computing system having an active sleep mode
US7114090B2 (en) 2003-02-14 2006-09-26 Intel Corporation Computing system with operational low power states
US7080271B2 (en) * 2003-02-14 2006-07-18 Intel Corporation Non main CPU/OS based operational environment
US7254730B2 (en) * 2003-02-14 2007-08-07 Intel Corporation Method and apparatus for a user to interface with a mobile computing device
JP3948621B2 (ja) * 2003-06-30 2007-07-25 株式会社山武 インターフェース回路
US8473647B2 (en) 2007-09-17 2013-06-25 Apple Inc. Methods and apparatus for decreasing power consumption and bus activity
US10353457B1 (en) 2015-03-04 2019-07-16 Altera Corporation Systems and methods for sleep mode power savings in integrated circuit devices
CN109410811B (zh) * 2017-08-17 2020-11-06 京东方科技集团股份有限公司 一种移位寄存器、栅极驱动电路及显示装置
US12112789B2 (en) * 2022-05-24 2024-10-08 Micron Technology, Inc. Apparatuses and methods for input buffer enable clock synchronization

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4438352A (en) * 1980-06-02 1984-03-20 Xerox Corporation TTL Compatible CMOS input buffer
US4406957A (en) * 1981-10-22 1983-09-27 Rca Corporation Input buffer circuit
US4501978A (en) * 1982-11-24 1985-02-26 Rca Corporation Level shift interface circuit
US4717847A (en) * 1985-04-29 1988-01-05 Harris Corporation TTL compatible CMOS input buffer
EP0218940A1 (fr) * 1985-09-30 1987-04-22 Siemens Aktiengesellschaft Circuit de conversion de tension
US4707623A (en) * 1986-07-29 1987-11-17 Rca Corporation CMOS input level shifting buffer circuit
JPH07120727B2 (ja) * 1987-03-27 1995-12-20 株式会社東芝 ＢｉＭＯＳ論理回路
US4894558A (en) * 1988-10-11 1990-01-16 Nec Electronics Inc. Power saving input buffer for use with a gate array
JPH02214219A (ja) * 1989-02-14 1990-08-27 Nec Corp バイポーラｍｏｓ３値出力バッファ
JPH03231455A (ja) * 1990-02-07 1991-10-15 Toshiba Corp 半導体集積回路
US5087841A (en) * 1990-04-09 1992-02-11 National Semiconductor Corporation TTL to CMOS translating circuits without static current
IL95576A0 (en) * 1990-09-04 1991-06-30 Quick Tech Ltd Controlled slew rate buffer
US5146111A (en) * 1991-04-10 1992-09-08 International Business Machines Corporation Glitch-proof powered-down on chip receiver with non-overlapping outputs
US5138198A (en) * 1991-05-03 1992-08-11 Lattice Semiconductor Corporation Integrated programmable logic device with control circuit to power down unused sense amplifiers
US5276362A (en) * 1992-05-06 1994-01-04 Motorola, Inc. BiCMOS TTL to CMOS level translator
US5280203A (en) * 1992-05-15 1994-01-18 Altera Corporation Look-ahead asynchronous register set/reset in programmable logic device

Also Published As

Publication number Publication date
EP0622903A3 (fr) 1995-08-02
US5432462A (en) 1995-07-11
EP0622903A2 (fr) 1994-11-02
JPH06350431A (ja) 1994-12-22

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