SG71192A1 - Pseudo precise i-cache inclusivity for vertical caches - Google Patents

Pseudo precise i-cache inclusivity for vertical caches

Info

Publication number
SG71192A1
SG71192A1 SG1999000590A SG1999000590A SG71192A1 SG 71192 A1 SG71192 A1 SG 71192A1 SG 1999000590 A SG1999000590 A SG 1999000590A SG 1999000590 A SG1999000590 A SG 1999000590A SG 71192 A1 SG71192 A1 SG 71192A1
Authority
SG
Singapore
Prior art keywords
inclusivity
pseudo
cache
precise
caches
Prior art date
Application number
SG1999000590A
Other languages
English (en)
Inventor
Ravi Kumar Arimilli
John Steven Dodson
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of SG71192A1 publication Critical patent/SG71192A1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
SG1999000590A 1998-02-17 1999-02-13 Pseudo precise i-cache inclusivity for vertical caches SG71192A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/024,321 US6345339B1 (en) 1998-02-17 1998-02-17 Pseudo precise I-cache inclusivity for vertical caches

Publications (1)

Publication Number Publication Date
SG71192A1 true SG71192A1 (en) 2000-03-21

Family

ID=21819988

Family Applications (1)

Application Number Title Priority Date Filing Date
SG1999000590A SG71192A1 (en) 1998-02-17 1999-02-13 Pseudo precise i-cache inclusivity for vertical caches

Country Status (10)

Country Link
US (1) US6345339B1 (de)
EP (1) EP0936552B1 (de)
JP (1) JP3245125B2 (de)
KR (1) KR100320974B1 (de)
CN (1) CN1134735C (de)
CA (1) CA2260285A1 (de)
DE (1) DE69930983T2 (de)
MY (1) MY119935A (de)
SG (1) SG71192A1 (de)
TW (1) TW428133B (de)

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JP3540255B2 (ja) 1999-09-28 2004-07-07 シャープ株式会社 液晶表示装置の導通不良修正方法
US6748490B1 (en) * 2000-03-29 2004-06-08 Ati International Srl Method and apparatus for maintaining data coherency in a shared memory system
US7117316B2 (en) * 2002-08-05 2006-10-03 Micron Technology, Inc. Memory hub and access method having internal row caching
US6993628B2 (en) * 2003-04-28 2006-01-31 International Business Machines Corporation Cache allocation mechanism for saving elected unworthy member via substitute victimization and imputed worthiness of substitute victim member
US6996679B2 (en) * 2003-04-28 2006-02-07 International Business Machines Corporation Cache allocation mechanism for saving multiple elected unworthy members via substitute victimization and imputed worthiness of multiple substitute victim members
US7484044B2 (en) * 2003-09-12 2009-01-27 Intel Corporation Method and apparatus for joint cache coherency states in multi-interface caches
US7426612B2 (en) * 2004-06-30 2008-09-16 Intel Corporation Methods and apparatus for enforcing instruction-cache coherence
US7418557B2 (en) * 2004-11-30 2008-08-26 International Business Machines Corporation Managing multiprocessor operations
US20070094450A1 (en) * 2005-10-26 2007-04-26 International Business Machines Corporation Multi-level cache architecture having a selective victim cache
US7836257B2 (en) * 2007-12-19 2010-11-16 International Business Machines Corpation System and method for cache line replacement selection in a multiprocessor environment
US8055847B2 (en) * 2008-07-07 2011-11-08 International Business Machines Corporation Efficient processing of data requests with the aid of a region cache
CN106776364B (zh) * 2012-10-22 2020-07-17 英特尔公司 用于高性能互连物理层的装置、方法和系统
US9639471B2 (en) 2012-11-27 2017-05-02 Nvidia Corporation Prefetching according to attributes of access requests
US9563562B2 (en) 2012-11-27 2017-02-07 Nvidia Corporation Page crossing prefetches
US9824009B2 (en) * 2012-12-21 2017-11-21 Nvidia Corporation Information coherency maintenance systems and methods
CN104978283B (zh) * 2014-04-10 2018-06-05 华为技术有限公司 一种内存访问控制方法，及装置
US9852071B2 (en) 2014-10-20 2017-12-26 International Business Machines Corporation Granting exclusive cache access using locality cache coherency state
JP7095208B2 (ja) * 2016-12-12 2022-07-05 インテル・コーポレーション プロセッサアーキテクチャのための装置および方法
US10282296B2 (en) 2016-12-12 2019-05-07 Intel Corporation Zeroing a cache line
CN119375664B (zh) * 2024-09-30 2025-07-25 兆讯恒达科技股份有限公司 面向可测试性设计的SoC缓存测试方法

Family Cites Families (11)

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US5553262B1 (en) * 1988-01-21 1999-07-06 Mitsubishi Electric Corp Memory apparatus and method capable of setting attribute of information to be cached
US5023776A (en) * 1988-02-22 1991-06-11 International Business Machines Corp. Store queue for a tightly coupled multiple processor configuration with two-level cache buffer storage
US5317716A (en) * 1988-08-16 1994-05-31 International Business Machines Corporation Multiple caches using state information indicating if cache line was previously modified and type of access rights granted to assign access rights to cache line
US5319766A (en) * 1992-04-24 1994-06-07 Digital Equipment Corporation Duplicate tag store for a processor having primary and backup cache memories in a multiprocessor computer system
CA2148186A1 (en) 1994-05-04 1995-11-05 Michael T. Jackson Processor board having a second level writeback cache system and a third level writethrough cache system which stores exclusive state information for use in a multiprocessor computer system
US5551001A (en) * 1994-06-29 1996-08-27 Exponential Technology, Inc. Master-slave cache system for instruction and data cache memories
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US5996048A (en) * 1997-06-20 1999-11-30 Sun Microsystems, Inc. Inclusion vector architecture for a level two cache
US6199144B1 (en) * 1997-12-31 2001-03-06 Intel Corporation Method and apparatus for transferring data in a computer system

Also Published As

Publication number Publication date
DE69930983D1 (de) 2006-06-01
CN1231443A (zh) 1999-10-13
MY119935A (en) 2005-08-30
EP0936552A3 (de) 1999-09-22
CA2260285A1 (en) 1999-08-17
EP0936552B1 (de) 2006-04-26
JP3245125B2 (ja) 2002-01-07
DE69930983T2 (de) 2006-11-23
JPH11328024A (ja) 1999-11-30
KR100320974B1 (ko) 2002-01-18
US6345339B1 (en) 2002-02-05
TW428133B (en) 2001-04-01
EP0936552A2 (de) 1999-08-18
KR19990072592A (ko) 1999-09-27
CN1134735C (zh) 2004-01-14

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