SG74672A1 - Integrated circuit and method of using porous silicon to achieve component isolation in radio frequency applications - Google Patents

Integrated circuit and method of using porous silicon to achieve component isolation in radio frequency applications

Info

Publication number
SG74672A1
SG74672A1 SG1998004663A SG1998004663A SG74672A1 SG 74672 A1 SG74672 A1 SG 74672A1 SG 1998004663 A SG1998004663 A SG 1998004663A SG 1998004663 A SG1998004663 A SG 1998004663A SG 74672 A1 SG74672 A1 SG 74672A1
Authority
SG
Singapore
Prior art keywords
integrated circuit
radio frequency
porous silicon
frequency applications
component isolation
Prior art date
Application number
SG1998004663A
Other languages
English (en)
Inventor
Han-Tzong Yuan
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of SG74672A1 publication Critical patent/SG74672A1/en

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326Deposition processes
    • H10P14/6349Deposition of epitaxial materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/66Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials
    • H10P14/665Porous materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19Preparing inhomogeneous wafers
    • H10P90/1904Preparing vertically inhomogeneous wafers
    • H10P90/1906Preparing SOI wafers
    • H10P90/191Preparing SOI wafers using full isolation by porous oxide silicon [FIPOS]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10Isolation regions comprising dielectric materials
    • H10W10/181Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
SG1998004663A 1997-12-29 1998-11-13 Integrated circuit and method of using porous silicon to achieve component isolation in radio frequency applications SG74672A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US6892297P 1997-12-29 1997-12-29

Publications (1)

Publication Number Publication Date
SG74672A1 true SG74672A1 (en) 2000-08-22

Family

ID=22085571

Family Applications (1)

Application Number Title Priority Date Filing Date
SG1998004663A SG74672A1 (en) 1997-12-29 1998-11-13 Integrated circuit and method of using porous silicon to achieve component isolation in radio frequency applications

Country Status (5)

Country Link
EP (1) EP0932204A1 (fr)
JP (1) JP4322985B2 (fr)
KR (1) KR19990063549A (fr)
SG (1) SG74672A1 (fr)
TW (1) TW436921B (fr)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002164512A (ja) * 2000-11-28 2002-06-07 Fujitsu Ltd 半導体装置及びその製造方法
FR2826177B1 (fr) * 2001-06-15 2004-07-02 St Microelectronics Sa Substrat a base de silicium poreux et procede de fabrication d'un tel substrat
FR2830670A1 (fr) * 2001-10-10 2003-04-11 St Microelectronics Sa Inductance et son procede de fabrication
FR2830683A1 (fr) 2001-10-10 2003-04-11 St Microelectronics Sa Realisation d'inductance et de via dans un circuit monolithique
US7176129B2 (en) 2001-11-20 2007-02-13 The Regents Of The University Of California Methods of fabricating highly conductive regions in semiconductor substrates for radio frequency applications
DE10209115B4 (de) * 2002-03-01 2004-05-06 Robert Bosch Gmbh Halbleiterbauelement mit porösen Bereichen
JP4661588B2 (ja) * 2005-12-27 2011-03-30 沖電気工業株式会社 ミリ波実装用配線基板
JP5421742B2 (ja) * 2009-11-24 2014-02-19 パナソニック株式会社 トランス
CN103956362A (zh) * 2014-05-20 2014-07-30 中国工程物理研究院电子工程研究所 基于图形化高能离子注入的低衬底损耗硅基集成电路及其制作方法
WO2021015816A1 (fr) * 2019-07-19 2021-01-28 Iqe Plc Matériau semi-conducteur ayant une permittivité accordable et une conductibilité thermique accordable
GB2612040B (en) 2021-10-19 2025-02-12 Iqe Plc Porous distributed Bragg reflector apparatuses, systems, and methods
WO2023125895A1 (fr) * 2021-12-31 2023-07-06 苏州能讯高能半导体有限公司 Composant passif composite et son procédé de préparation

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5472913A (en) * 1994-08-05 1995-12-05 Texas Instruments Incorporated Method of fabricating porous dielectric material with a passivation layer for electronics applications
KR100314610B1 (ko) * 1996-08-09 2001-12-28 윤덕용 산화막다공성실리콘기판을이용한초고주파소자
US5736749A (en) * 1996-11-19 1998-04-07 Lucent Technologies Inc. Integrated circuit device with inductor incorporated therein
US5767561A (en) * 1997-05-09 1998-06-16 Lucent Technologies Inc. Integrated circuit device with isolated circuit elements
KR100281637B1 (ko) * 1997-12-22 2001-03-02 정선종 기판 변환 기술에 의한 고성능 인덕터 소자의 제조방법

Also Published As

Publication number Publication date
KR19990063549A (ko) 1999-07-26
EP0932204A1 (fr) 1999-07-28
TW436921B (en) 2001-05-28
JPH11251532A (ja) 1999-09-17
JP4322985B2 (ja) 2009-09-02

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