SG79221A1 - Control structure for a high-speed asynchronous pipeline - Google Patents

Control structure for a high-speed asynchronous pipeline

Info

Publication number
SG79221A1
SG79221A1 SG9703626A SG1997003626A SG79221A1 SG 79221 A1 SG79221 A1 SG 79221A1 SG 9703626 A SG9703626 A SG 9703626A SG 1997003626 A SG1997003626 A SG 1997003626A SG 79221 A1 SG79221 A1 SG 79221A1
Authority
SG
Singapore
Prior art keywords
control structure
speed asynchronous
asynchronous pipeline
pipeline
speed
Prior art date
Application number
SG9703626A
Other languages
English (en)
Inventor
E Molnar Charles
M Fairbanks Scott
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Publication of SG79221A1 publication Critical patent/SG79221A1/en

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/08Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations, the intermediate ones not being accessible for either enqueue or dequeue operations, e.g. using a shift register
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003Arrangements for executing specific machine instructions
    • G06F9/30076Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/30079Pipeline control instructions, e.g. multicycle NOP
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/10Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
    • G06F5/12Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations
    • G06F5/14Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations for overflow or underflow handling, e.g. full or empty flags
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149Source or drain regions of field-effect devices
    • H10D62/151Source or drain regions of field-effect devices of IGFETs 
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804Details
    • G06F2207/386Special constructional features
    • G06F2207/3884Pipelining

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Information Transfer Systems (AREA)
  • Dram (AREA)
  • Advance Control (AREA)
  • Shift Register Type Memory (AREA)
SG9703626A 1996-10-01 1997-10-01 Control structure for a high-speed asynchronous pipeline SG79221A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/720,755 US5937177A (en) 1996-10-01 1996-10-01 Control structure for a high-speed asynchronous pipeline

Publications (1)

Publication Number Publication Date
SG79221A1 true SG79221A1 (en) 2001-03-20

Family

ID=24895160

Family Applications (1)

Application Number Title Priority Date Filing Date
SG9703626A SG79221A1 (en) 1996-10-01 1997-10-01 Control structure for a high-speed asynchronous pipeline

Country Status (6)

Country Link
US (1) US5937177A (fr)
EP (2) EP0834802A3 (fr)
JP (1) JPH11167791A (fr)
KR (1) KR19980032458A (fr)
SG (1) SG79221A1 (fr)
TW (1) TW345638B (fr)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6502180B1 (en) * 1997-09-12 2002-12-31 California Institute Of Technology Asynchronous circuits with pipelined completion process
US9092595B2 (en) 1997-10-08 2015-07-28 Pact Xpp Technologies Ag Multiprocessor having associated RAM units
WO2001016702A1 (fr) 1999-09-01 2001-03-08 Intel Corporation Ensemble de registres utilise dans une architecture de processeurs multifiliere paralleles
HK1046049A1 (zh) 1999-09-01 2002-12-20 Intel Corporation 用於多线程处理器的分支指令
US6477637B1 (en) * 1999-09-30 2002-11-05 International Business Machines Corporation Method and apparatus for transporting store requests between functional units within a processor
US6574690B1 (en) 1999-12-29 2003-06-03 Sun Microsystems, Inc. Asynchronous pulse bifurcator circuit with a bifurcation path coupled to control fifo and first and second subordinate fifo
US7681018B2 (en) 2000-08-31 2010-03-16 Intel Corporation Method and apparatus for providing large register address space while maximizing cycletime performance for a multi-threaded register file set
US6420907B1 (en) * 2000-09-29 2002-07-16 Sun Microsystems, Inc. Method and apparatus for asynchronously controlling state information within a circuit
US20020078328A1 (en) * 2000-12-14 2002-06-20 International Business Machines Corporation Pulse-controlled micropipeline architecture
US6925549B2 (en) * 2000-12-21 2005-08-02 International Business Machines Corporation Asynchronous pipeline control interface using tag values to control passing data through successive pipeline stages
US6859873B2 (en) * 2001-06-08 2005-02-22 Infineon Technologies Ag Variable length instruction pipeline
US7437724B2 (en) * 2002-04-03 2008-10-14 Intel Corporation Registers for data transfers
AU2003233109A1 (en) * 2002-06-14 2003-12-31 Koninklijke Philips Electronics N.V. Fifo-register
US7423696B2 (en) * 2005-01-07 2008-09-09 Hewlett-Packard Development Company, L.P. Concurrent luminance-saturation adjustment of digital images
CN101258463A (zh) * 2005-09-05 2008-09-03 Nxp股份有限公司 异步脉动流水线
US7890826B2 (en) * 2006-12-11 2011-02-15 Oracle America, Inc. Method and apparatus for test of asynchronous pipelines
US7971043B2 (en) * 2007-11-22 2011-06-28 Andes Technology Corporation Electronic system and method for changing number of operation stages of a pipeline
US20150074353A1 (en) * 2013-09-06 2015-03-12 Futurewei Technologies, Inc. System and Method for an Asynchronous Processor with Multiple Threading
US9385717B1 (en) * 2014-05-30 2016-07-05 Altera Corporation Level-sensitive two-phase single-wire latch controllers without contention
CN112667292B (zh) * 2021-01-26 2024-04-05 北京中科芯蕊科技有限公司 一种异步微流水线控制器

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4151609A (en) * 1977-10-11 1979-04-24 Monolithic Memories, Inc. First in first out (FIFO) memory
EP0312914B1 (fr) * 1987-10-22 1995-02-22 Advanced Micro Devices, Inc. Dispositif de mémoire PEPS à propagation
US5513224A (en) * 1993-09-16 1996-04-30 Codex, Corp. Fill level indicator for self-timed fifo

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3510680A (en) * 1967-06-28 1970-05-05 Mohawk Data Sciences Corp Asynchronous shift register with data control gating therefor
US4225920A (en) * 1978-09-11 1980-09-30 Burroughs Corporation Operator independent template control architecture
FR2552916B1 (fr) * 1983-09-29 1988-06-10 Thomas Alain File d'attente asynchrone a empilement de registres
US5187800A (en) * 1985-01-04 1993-02-16 Sun Microsystems, Inc. Asynchronous pipelined data processing system
US4791551A (en) * 1985-02-11 1988-12-13 Analog Devices, Inc. Microprogrammable devices using transparent latch
GB9114513D0 (en) * 1991-07-04 1991-08-21 Univ Manchester Condition detection in asynchronous pipelines
US5572691A (en) * 1993-04-21 1996-11-05 Gi Corporation Apparatus and method for providing multiple data streams from stored data using dual memory buffers
EP0650117B1 (fr) * 1993-10-21 2002-04-10 Sun Microsystems, Inc. Pipeline à contre-courant
US5638009A (en) * 1993-10-21 1997-06-10 Sun Microsystems, Inc. Three conductor asynchronous signaling

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4151609A (en) * 1977-10-11 1979-04-24 Monolithic Memories, Inc. First in first out (FIFO) memory
EP0312914B1 (fr) * 1987-10-22 1995-02-22 Advanced Micro Devices, Inc. Dispositif de mémoire PEPS à propagation
US5513224A (en) * 1993-09-16 1996-04-30 Codex, Corp. Fill level indicator for self-timed fifo

Also Published As

Publication number Publication date
US5937177A (en) 1999-08-10
EP1296221A1 (fr) 2003-03-26
JPH11167791A (ja) 1999-06-22
EP0834802A2 (fr) 1998-04-08
EP0834802A3 (fr) 1999-05-19
TW345638B (en) 1998-11-21
KR19980032458A (ko) 1998-07-25

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