SU1084792A2 - Firmwave control unit - Google Patents

Abstract

MICROPROGRAMMING ENHANCEMENT OF THE ELECTRONIC DEVICE according to the author of the USSR USSR № 949657 ,. characterized in that in order to increase its reliability by monitoring the progress of the microprogram execution, it additionally contains a reversible counter, the control input of which is connected to the microcommand register control control output, the reversible counter's count input, the counter overflow output connected to the fault output of the device. Q

Description

The invention relates to automation and computing, in particular to microprogrammed control devices, and can be used in digital computing systems, as well as terminal equipment. According to the main author. St. No. 949657 a firmware control device is known that contains a microinstructor memory block, a microcommand register, an address register, a condition checker, a pulse generator, a group of And elements, a lock register and an And element, with the outputs of the condition testing block connected to the address register inputs The outputs of which are connected to the inputs of the microinstructions memory block, the outputs of which are connected to the information inputs of the register of microinstructions, whose address outputs are connected to the information inputs of the condition checker that controls Which one is the device input, the control outputs of the micro-command register are connected to the first inputs of the element group element, whose outputs are the first output of the device, and the information outputs of the micro-command register are the second output device, the output of each element And the element group And is connected to inverse the inputs of all subsequent AND elements of the AND group of elements, with the reverse input of the AND element and with the installation input of the lock register, the outputs of the lock register are connected to the second inputs of the AND elements Rupp element and output element and coupled with the control register microinstruction WMOs house and installation of the entrance to the initial state lock register timing input connected to the output of the pulse generator of S. n disadvantage of the known devices is the lack of control stroke vsholneni firmware. The aim of the invention is to increase the reliability of the device by monitoring the progress of the microprogram execution. This goal is achieved by the fact that a reversible counter is entered into the microprogram control device, the control input of which is connected to the microcommand register account control output, the counter input the output of the clock pulse-generator. and the overflow output of the counter is connected to the malfunction output of the device. With this solution, in each executed micro-command, a reversible counter is counted in accordance with the number of micro-orders in the micro-command and the specified count direction. If the firmware is executed correctly, the reversible counter does not overflow and does not zero. In the event of a violation of the correct course of the firmware, the counting mode of the reversible counter is violated, as a result of which it either overflows or zeroes. In this case, the transfer or loan signals at its controlled output indicate an error. FIG. 1 shows a diagram of the proposed device; in fig. 2 block diagram checkout; in fig. 3 - time diagram of the device. The microprogram control device contains a block of 1 microinstructor memory, a register of 2 microinstructions, a register of 3 addresses, a condition checking block 4, a generator of 5 clock pulses, a lock register 6, a group of elements 7, an element 8, a reversible counter 9, first outputs O, the first inputs 11, the input 12 of the initial installation, the second outputs 13, the output 14 of the fault. The condition verification unit 4 (FIG. 2) contains a group of EXCLUSIVE OR elements 15. The first and second inputs of the EXCLUSIVE OR elements 15 are, respectively, the information inputs of the condition verification unit 4 and the device inputs 11. The outputs of the EXCLUSIVE OR 15 VL elements are the outputs of the conditional verification unit 4. The time diagram of the device (Fig. 3) shows the signal 16 of the initial installation at the input; 12 devices; pulses 17 at the output of the generator 5 pulses; signal 18 at the output of the element And 8; the 1921 signals at the outputs of the first, fifth, and twelfth elements of AND 7. The microprogram control device operates as follows. To bring the device into the correct state, a signal 16 is transmitted to its input 12, as a result of which the register of 2 microcommands and the address register 3 are set to zero, and the reversible counter 9 sets to any given state other than zero and one. At the zero address from block 1, the micro-instruction memory is started on the micro-command and goes to the information inputs of the register of 2 micro-commands. Since the contents of the register of 2 micro-commands is zero, the zero signals are also present at the outputs of all elements 7, the signal 18 is formed in the result of the 18 signal. By the signal 18, the lock register 6 is set to one and the initial micro-command is entered into the register 2 of micro-commands . Each microinstruction consists of three parts — address, operational, and control. In addition, the microcommand field contains one bit of control of the reversing account of the count 9. The address of the microcommand contains the code used to determine the address of the next microcommand. The address part of the microcommand goes to the information inputs of the condition checker 4. The operation portion indicates the operation code that the operating circuits controlled by this firmware control device perform. The operational part of the microcommand enters output 10 of the device. In the control part of the micro-command, a set of micro-orders is specified, with. In which the implementation of the operation: specified in the operating part is carried out. In the account control bit, the counting direction (with the addition or subtraction of one) of the reversible counter is set. For example, to execute: three micro-commands carried in register 2 microcommands are necessary. Moreover, a single signal must be present in the shadow of the first, third iH of the third micro-tact, for example, at the outputs of the first, fifth and twelfth elements And 7, respectively. Therefore, on the first, fifth, and twelfth control outputs of the register 2 micro-commands, there are single signals, and the others are zero. Then, during the first peace, a single signal 19 is present at the output of the first element 92, as a result of which all subsequent elements And 7 are closed. In the second micro-clock pulse 17 and in the presence of a single signal at the first setup input, the first digit of lock register 6 is set to zero. In addition, by their i-pulse 17 and in accordance with the value of the count control bit in the micro-command field, the first unit is added or subtracted from the content of the reversible counter 9. The direction of the account in the account control bit is set so that after the execution of the entire microcommand, i.e. After adding or subtracting the number of units from the reversible counter 9 to the contents in accordance with the number of micro-orders, the reversible counter 9 did not drop or not overflow. The first element And 7 is closed, opening all subsequent elements And 7 by itself4. Since the second, third and fourth elements of And 7 are covered with zero signals from the control outputs of the microcomputer register 2, a single signal 20 is generated at the output of the fifth element And 7. In the third By the pulse 17, the second unit is added (subtracted from it) to the contents of the reversible counter 9, and the fifth bit of the lock register 6 is set to zero. As a result, a signal 21 is outputted at the output of the twelfth element 7. In the next micro tact, the last third unit is added (subtracted from it) to the contents of the reversible counter 9 in accordance with the number of micro orders placed in the microcommand under consideration. Set at zero the twelfth. the bit of lock register 6 is closed by the twelfth element AND 7 and zero signals are present at the outputs of all elements AND 7. A signal 18 is generated, as a result of which the blocking register 6 is set to the initial single state, and the next micro-command is entered into the micro-command register 2. Up to this point in time, by the address part of the current microcommand in the condition checking unit 4, the address of the next microcommand in the

depending on the values of the signal conditions coming from the operating circuits to the input 11 of the device. The pulse 17 resulted in the entry of the address formed by the unit 4 for checking the condition into the address register 3, as a result of which the corresponding micro-command was selected from the micro-command memory block 1. Thus, the signal 18 recorded in register 2 of the microinstruction is prepared in advance.

As each microcommand is executed, the counting counter 9 is generated. Moreover, the contents of the counting counter 9 linearly increase (when added) not the income before overflow, and then linearly

decreases (when subtracted) is not income to zero. If the correct flow of the firmware is violated, the controlled counting mode of the reversible counter 9 is also disturbed, with the result that it either overflows or is zeroed. At the same time, the overflow (loan) signal comes from the overflow output of the reversible counter 9 to the output 14 of the device, which signals the error.

Thus, the proposed device has greater reliability compared with the known device, since, in contrast, it controls the progress of the microprogram execution.

FIG. 2

FIG. Have

Claims (1)

FIRMWARE CONTROLLING ³ OTHER DEVICE according to ed. St.SSSR No. 949657, characterized in that, in order to increase its reliability by monitoring the progress of the microprogram, it additionally contains a reversible counter, the control input of which is connected to the control output of the micro register register, counting the input of the reverse counter is connected to the output of the clock generator, the overflow output of the counter is connected to the output of the device malfunction. q ns 1 1084792