SU1109727A1 - Information input device - Google Patents

Abstract

DEVICE FOR INPUT OF INFORMATION, containing the first, second and third registers, the first generator of single pulses, the generator of pulses, the distributor of pulses, the first decoder, the first group of drivers, the first, second, third and fourth groups of elements AND, element NAND, first element And, the first counter, the inputs of the group of the first register are the inputs of the device group, the input of the first register is connected to the output of the first generator of single pulses, the first input of which is the input of the device, and the second input and the first od distributor connected to the output pulses of the pulse generator, the outputs of the first register are connected to inputs of the first decoder, the outputs of the first group are connected to the input of the first group. and the outputs of the second group - with the inputs of the second register group, the input of which is connected to the first input of the pulse distributor, the first output of the second register connected to the first inputs of the AND AND first group elements and the first input of the NAND element, the second input of which, the first inputs of the AND elements of the second group and the first inputs of the elements of the third group and the first input of the first element I are connected to the second output of the second register, the second input of the first element I is connected to the second output of the pulse distributor, the output of the element AND NOT connected to the first the inputs of the elements of the fourth group, the second inputs of KOTopi.ix are connected to the outputs of the shapers of the first group, the third BKDG.1 - to the third output of the pulse distributor, the outputs of the elements of the fourth group are connected to inputs 8 (L of the third register whose inputs are connected to the second inputs elements of the first group and the second inputs of the elements of the second group, the fourth output of the pulse distributor is connected to the third inputs of the elements of the first and second groups, the second inputs of the elements of the third group, the outputs of the elements And p The first group is connected to the inputs of the group of the first counter, the input of which is connected to the output of the first element AND, the outputs of the counter are connected to the third inputs of the elements AND of the third group, the outputs of which are the outputs of the first group of the device, the outputs of the elements And the second group are the outputs of the second group of device characterized in that, in order to improve speed, the device contains a second decoder, the first, second and third elements of the IL, the element is NOT, the second, third and fourth elements are AND, the second generator of single imp pulses, the second counter, the inputs of the second group

Description

the decoder and the first element OR are connected to the inputs of the device group, the element input is NOT connected to the device input, and the output is connected to the first input of the second element AND, the output of the first element OR is connected to the second input of the second element AND, the output of which is connected to the first input of the second single pulse generator , the second input of which is connected to the output of the pulse generator, the output of the second generator of single pulses is connected to the input of the second counter, the inputs of which group through the second group of drivers are connected to you The signals of the second decoder are connected to the second element OR, the second input of the fourth element I is connected to the sixth output of the pulse distributor, the second input of the third element And is connected to the fifth output of the distributor pulses, the output of the third element And is connected to the second input of the second counter, the output of the fourth element And is connected to the first input of the third element OR, the second input of which is connected to the output of the first g generator of single pulses, the output of the third OR gate is connected to the input of the distributor vtrym pulses.

The invention relates to automation and computing technology and can be used in specialized computers, including numerical control devices,

J A device for inputting information is known, which contains the first, second and third registers, the single pulse generator, the pulse generator, the frequency divider, the pulse distributor, the decoder, the first, second, third and fourth groups of And elements, the counter, the And elements. This device allows enter information from both the keyboard and automatic J

However, the device has a low response rate because it does not allow the input of compressed information.

The closest to the invention in its physical nature is a device for inputting information containing the first, second, and third registers, the first single pulse generator, the pulse generator, the pulse distributor, the first decoder, the first group of drivers, the first, second, third} and fourth groups AND elements, NAND element, AND first element, first counter, the inputs of the first register group are the inputs of the device group, the first register input is connected to WY

the course of the first generator of single pulses, the first input of which is the device input, and the second input and the first input of the pulse distributor are connected to the output of the pulse generator, the inputs of the first register are connected to the inputs of the first decoder, the outputs of the first group of which are connected to the inputs of the first group of drivers, and the outputs the second group - with the inputs of the second register group, the input of which is connected to the first output of the pulse distributor, the first output of the second register is connected to the first drifts of the elements AND the first bar the first input of the element, the first inputs of the elements AND of the second group, the first inputs of the elements AND of the third group and the first input of the first element I are connected to the second output of the second register, the second input of the first element I connected to the second output of the pulse distributor , the output of the element is NOT connected to the first inputs of the elements AND the fourth group, the second inputs of which are connected to the outputs of the drivers of the first group, the third inputs with the third output of the pulse distributor, the outputs of the elements AND the fourth group s are connected to the inputs of the third register, the outputs of which are connected to the second inputs of the elements of the first group and the second inputs of the elements of the second group, the fourth output of the distributor pulse connected to the third inputs of the elements of the first and second groups, the second inputs of the elements of the third group, the outputs of the elements And the first group is connected to the inputs of the group of the first counter, the input of which is connected to the output of the first element I, the output of the counter is connected to the third inputs of the elements AND of the third group, the outputs of which are the outputs of ne group howling device elements and outputs of the second group are the outputs of the second group device 2. Disadvantages ievestnogo devices are limited by applying region caused by the impossibility of the input compressed information, and, consequently, low speed. The purpose of the invention is to increase the speed of the device. Achieving this goal is ensured by the fact that the device for entering information contains the first, second and third registers, the first generator of single pulses, the generator of pulses, the distributor of pulses, the first decoder, the first group of drivers of the first, second, third and fourth groups of elements And , element AND-НЁ, element И, the first counter, the inputs of the group of the first register are the inputs of the device, the input of the first register is connected to the output of the first generator of single pulses, the first input of which is the input of the device, the second input and the first input of the pulse distributor are connected to the output of the pulse generator, the outputs of the first register are connected to the inputs of the first decoder, the outputs of the first group of which are connected to the inputs of the first group generator, and the outputs of the second group - with the inputs of the second register group, the input which is connected to the first output of the pulse distributor, the first output of the second register is connected to the first inputs of the AND elements of the first group and the first input of the NAND element. the second input of which, the first inputs of elements AND of the second group, the first inputs of elements AND of the third group and the first input of the first element AND are connected to the second output of the second re-. the gistra, the second input of the first element AND is connected to the second output of the pulse distributor, the output of the element IS NOT the connected to the first inputs of the elements AND of the fourth group, the second inputs of which are connected to the outputs of the drivers of the first group, the third inputs to the third output of the pulse distributor, the outputs of the elements AND the fourth group is connected to the inputs of the third register, the outputs of which are connected to the second inputs of the elements AND of the first group and the second inputs of the elements AND of the second group, the fourth output of the pulse distributor With the third inputs of the elements AND the first and second are the outputs of the second group of the device, the second decoder, the first, second and third elements OR, the element NOT, the second, third and fourth elements AND, the second generator of single pulses, the second groups, the second inputs of elements And the third group, the outputs of the elements And the first group is connected to the inputs of the group of the first counter, the input of which is connected to the output of the first element And, the outputs of the counter are connected to the third inputs of the elements AND of the third group, the outputs of which are outputs and the first group of device, the outputs of elements AND the second group of the counter, the inputs of the second decoder group and the first element OR are connected to the inputs of the device group, the element input is NOT connected to the device input, and the output is connected to the first input of the second element AND, the output of the first element OR is connected to the second input of the second element And, the output of which is connected to the first input of the second generator of single pulses, the second input of which is connected to the output of the pulse generator, the output of the second generator of single pulses is connected to the input the house of the second counter, the group's inputs through the second group of drivers are connected to the outputs of the second decoder, the outputs of the counter are connected to the inputs of the second element OR, the first inputs of the third and fourth elements AND are connected to the output of the second element OR, the second input of the fourth element AND is connected to the sixth output pa a pulse distributor, and the second input of the third element I is connected to the fifth output; it distributes pulse bodies, the output of the third element I is connected to the second input of the second counter, the output of the fourth element connected to the first input of the third OR gate, a second input coupled to an output of the first single-pulse generator, the output of the third OR gate is connected to the second input of the distributor pulses. The drawing shows a block diagram of the proposed device. The device contains the first re, the gistr 1, the input 2 of the device group, the first generator 3 single pulses, the device input 4, the generator 5 pulses, the distributor 6 pulses, the first decoder 7, the first group of elements OR 8, the second register 9, the first group of elements AND 10, the element AND-NOT 11, the second 12 and the third 13 groups of elements And, the first element And 14, the fourth group of elements, And 15, the third register 16, the first counter 17, the output of the first 18 and the second 19 groups of the device, the second decoder 20, the first element OR 21, the element NOT 22, the second element AND 23, the second generator 24 single pulses, the second counter 25 the second group of elements OR .26, the second element OR 27, the third 28 and the fourth 29 elements AND, the third element OR 30. The device works as follows. Compression of information is carried out in the event that the sequence is entered the same characters, and the number of them is more than two. A number indicating the number of identical characters is entered in front of the compressible number, and its encoding is carried out with a hexadecimal & 1 number. The difference is that a number indicating the number of identical symbols is not accompanied by a sync pulse. In each cycle, the input character is fed from input 2 of the group to register 1, decoder 20 and element OR 21. At the same time, input 4 to the generator 3 single-pulses and the element NOT 22 receives a sync pulse (if it is generated by the control circuit

or there is a punched hole in the sync track of a punched tape). To the second generator input 3 single pulses and 6 pulses in this cycle are not

is produced. In the seventh cycle, the input symbol is the compressible information symbol. The limiter 6 pulses is supplied by the i clock pulse series, which is generated by the generator 5 pulses. In each cycle, the pulse distributor performs six cycles. At the first cycle, the decoder 7 analyzes the state of register 1 and, together with the NAND element 11, generates a signal for the absence of overhead information. In the second cycle, the four lower bits of register 1 through the decoder 7, the group of elements OR 8, and the group of elements And 15 arrive at the four lower registers 16. From the second to the sixth cycles of the first cycle, nothing is done. Register 16 is made shifting by four positions in the direction of the higher bits. The decoder 7 and the group of elements OR 8 convert the character code into a hexadecimal code. Entering the characters of the address in the second, third and fourth cycles is done in the same way as entering a character in the first cycle. In the fifth cycle, the character of the transmission of the address is entered. With this, with the arrival of a clock pulse on the inputs of 4 groups, the generator of 3 single pulses produces a signal, -. the decisive record of the character of the transfer of the address to the first register 1. At the same time, the pulse distributor 6 is started. In the first cycle, the decoder 7 generates a signal that sets the first bit of the register 9 to one state. The element AND NOT 11 generates a signal prohibiting the recording of information in the register 16, produced by the second cycle. In the third cycle, the address is recorded from register 16 to counter 17 through a group of elements AND 10. In the next three cycles of this cycle, nothing is done. In the sixth cycle, the number of compressible information is entered (4). From the inputs of the 2nd group, the information enters the decoder 20 and the element OR 21. The element OR 21 together with the element NOT 22, the element AND 23 and the generator 24 of single pulses produce a signal allowing the recording of information from the decoder 20 through the group by the element OR 26 to the counter 25. Starting Distribution The order of operation at this is the same as in the first four cycles of the first four cycles. In the fifth cycle of the seventh cycle, the OR 27 element generates, together with the AND 28 element, the modification signal of the counter 25. In the sixth cycle of the seventh cycle, the And 29 element generates a return signal of the distributor 6 pulses. In this case, the device performs three cycles in succession. In the last cycle, the counter 25 is zeroed out and the return of the distributor 6 does not follow. Thus, in one cycle of inputting a character from a keyboard or carrier and formation, the four lower bits of register 1 are rewritten to register 16 four times, since the number of compressible information is four. In the eighth and ninth cycle, the input device works the same as in the first four cycles, i.e. On a sync pulse arriving at input 4, a generator of 3 single pulses generates a signal on which information from inputs 2 of the group is written into register 1. At the same time, the distributor 6 pulses are started. In the first clock, the decoder 7 analyzes the state of the register t and confirms the zero state of the register 9. In the second clock, the four least significant bits of register 1 from the element group OR 8 are recorded in register 16 by the AND 15 element group. The contents of register 16 are preliminarily shifted four positions in the direction of senior | bits. Nothing is produced in cycles three through six. In de, from that cycle, from the inputs 2 of the group, a recording attribute is received, which is written to register 1 according to the signal generated by the generator 3 of single pulses. At the same time, the distributor 6 pulses is started. The decoder 7 analyzes the state of register 1, and the result of the analysis is written to register 9 in the first clock cycle. By the second clock, writing to register 16 is not performed, since H-NE 11 generates an overhead signal prohibiting this record. By the third cycle, the contents of register 16 and counter 17 through the groups I 12 and I 13 enter the outputs of the first and second groups. In the fourth clock cycle, the AND 14 element generates a signal to modify the address of the counter 17. Nothing is produced in the fifth and sixth clock cycles of this cycle.

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Claims (1)

DEVICE FOR INFORMATION INPUT, containing the first, second and third registers, the first single pulse generator, pulse generator, pulse distributor, the first decoder, the first group of formers, the first, second, third and fourth groups of elements AND, the AND element, the first AND element , the first counter, the inputs of the first register group are the inputs of the device group, the input of the first register is connected to the output of the first single pulse generator, the first input of which is the input of the device, and the second input and the first input are the pulse distributor is connected to the output of the pulse generator, the outputs of the first register are connected to the inputs of the first decoder, the outputs of the first group of which are connected to the inputs of the formers of the first group,. and the outputs of the second group - with the inputs of the second register group, the input of which is connected to the first input of the pulse distributor, the first output of the second register is connected to the first inputs of the AND elements of the first group and the first input of the AND-NOT element, whose second input, the first inputs of the AND elements of the second group and the first inputs of the AND elements of the third group and the first input of the first AND element are connected to the second output of the second register, the second input of the first AND element is connected to the second output of the pulse distributor, the output of the AND gate is NOT connected to the first by the strokes of the elements of the fourth group, the second inputs of which are connected to the outputs of the former of the first group, the third inputs are the third output of the pulse distributor, the outputs of the elements of the fourth group are connected to the inputs of the third register, the outputs of which are connected to the second inputs of the elements of the first group and the second inputs of the elements And the second group, the fourth output of the pulse distributor is connected to the third inputs of the elements And the first and second groups, With the second inputs of the elements And the third group, the outputs of the elements And the first group connected to the group inputs of the first counter, the input of which is connected to the output of the first AND element, the outputs of the counter are connected to the third inputs of the AND elements of the third group, the outputs of which are the outputs of the first device group, the outputs of the elements AND of the second group are outputs of the second device group, characterized in that , in order to improve performance, the device contains a second decoder, the first, second and third elements OR, the element NOT, the second, third and fourth elements AND, the second second pulse generator, the second count uk, the second group of inputs 7ZZ6011 of the decoder and the first OR element are connected to the device group inputs, the element input is NOT connected to the device input, and the output is connected to the first input of the second AND element, the output of the first OR element is connected to the second input of the second AND element, the output of which is connected to the first input of the second generator single pulses, the second input of which is • connected to the output of the pulse generator, the output of the second single pulse generator is connected to the input of the second counter, the group inputs of which are connected through the second group of formers s with the outputs of the second decoder, the outputs of the counter are connected to the inputs of the second OR element, the first inputs of the third and fourth elements AND are connected to the output of the second OR element, the second input of the fourth element And is connected to the sixth output of the pulse distributor, the second input of the third element And is connected to the fifth the output of the pulse distributor, the output of the third AND element is connected to the second input of the second counter, the output of the fourth AND element is connected to the first input of the third OR element, the second input of which is connected to the output of the first a single pulse generator, the output of the third OR gate is connected to the second input of the pulse distributor.