SU1176331A1 - Device for correcting failure in n-bit ring shift register - Google Patents

Abstract

DEVICE FOR CORRECTION OF FAILURE IN P-BIT RING DRIVER REGISTRY, containing clock generator, first AND element, delay element, AND element, first OR element, two-digit counter, clock output of the clock generator connected to the clock input of the r-digit ring register shift, n outputs of the delay element connected to the first inputs of the elements And the first group, the second inputs of which are connected to the outputs of the bits of the controlled | l-discharge ring register shift, the output of each element And the first group is connected to the corresponding input of the first OR element, the output of which is connected to the counting input of a two-bit counter, the output of the first bit of which is connected to the first input of the AND element, the second input of which is connected to the nth output of the delay element, the output of the AND element connected to the input The first bit settings of the girth ring annular shift register are differently because, in order to increase the noise immunity, a n digit counter, a decoder, the second group of elements of Andov elements, the second element OR, and the overflow output of the two-bit counter is connected to the first inputs of elements AND of the second group, the first input of the second element OR is connected to the (n +) m output of the delay element, the second input of the OR element is connected to the output of the n-th digit of the controlled n-bit ring shift register , the output of the second element OR is connected to the reset input of the N-bit counter, the counting input of which is connected to the output of the clock pulse generator, the information outputs of the N-bit counter are connected to the information inputs 00 of the decryptor Pa, the second inputs of elements And from the second group are connected to the corresponding outputs of the decoder, the output of each element And the second group is connected to the reset input of the corresponding) n-bit discharge ring-shaped shift register.

Description

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The invention relates to the technical means intended for use in control devices, automation and information measuring equipment, in particular in control systems with sequential polling of monitored objects. Ring distributors (CS) are used as elements that provide a sequence of polling when monitoring objects (sensors), i.e. one true I should circulate in the CD, and not false because of the disturbing influences in. CD and because of the disappearance of the true 1.

The aim of the invention is to improve noise immunity.

The drawing shows a block diagram of a device for correcting faulty codes in the RS.

The device contains KP 1 consisting of triggers, a group of elements AND 2-5, a second group of elements AND 6-9, outputs 10-13 delay element 14, the first element OR 15, a two-bit counter 16, a decoder 17, h-bit the counter 18, the generator 19 clock pulses, n + 1 output 20 of the delay element 14, the element And 21, the second element OR 22.

The device works as follows.

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Upon the arrival of the next clock pulse, given by the clock generator 19, true 1 advances to switch 1 in the next slot,

5, the content of bit counter 18 is incremented by one and records the cell number KP 1, in which 1 is true, and using delay line 14, AND 2-5 elements and OR 15 element, the states of KP 1 flip-flops are polled. true only 1 circulates, then in each clock cycle in the two-digit bottom of the counter 16 only

15 is the first bit, and at the end of the clock cycle, the counter 16 is set by the signal from the delay element 14 to the zero state. When one or several false ones appear, the second bit of the two-bit counter 16 is triggered, the signal of which, through the second group of elements AND 6-9, controlled by the decoder 17, resets all triggers KP 1 to the zero state, of the trigger that is 1 and whose number is determined by an AND-bit counter 18. This trigger is blocked from being reset by the corresponding

- an additional element And, also controlled by a decoder 17.

Claims (1)

DEVICE FOR CORRECTION OF FAILURE IN A P-DISCHARGE RING SHIFT REGISTER, containing a clock pulse generator, a first group of AND elements, a delay element, an AND element, a first OR element, a two-bit counter, the output of the clock generator being connected to the clock input of the n-bit ring shift register , η of the outputs of the delay element are connected to the first inputs of the elements And of the first group, the second inputs of which are connected to the outputs of the bits of the controlled P-bit annular shift register, the output of each element And ne the first group is connected to the corresponding input of the first OR element, the output of which is connected to the counting input of a two-digit counter, the first discharge of which is connected to the first input of the And element, the second input of which is connected to the nth output of the delay element, the output of the And element is connected to the input of the mouth the first category of the η-bit annular shift register, characterized in that, in order to improve noise immunity, an η-bit counter, a decoder, a second group of AND elements, a second OR element, and an output a two-digit counter is connected to the first inputs of AND elements of the second group, the first input of the second OR element is connected to the (n + 1) -th output of the delay element, the second input of the OR element is connected to the output of the ηth discharge of the controlled η-bit ring shift register, output the second OR element is connected to the reset input of the P-bit counter, the counting input of which is connected to the output of the clock pulse generator, the information outputs of the P-bit counter are connected to the information inputs of the decoder, the second inputs are Tov and second groups are connected to respective outputs of the decoder, the output of each AND gate of the second group is connected to the reset input of the respective bit of the n-bit circular shift register.