SU1182425A1 - Digital apparatus for measuring paramters of harmonic signals - Google Patents

Abstract

DIGITAL APPARATUS MEASURING PARAMETERS harmonic signals comprising two analog-converter, the first inputs of which are input devices, the control unit samples whose input is connected to one of the device inputs and first and second outputs - to the respective second inputs of analog-converters, driver time Intervals, the output of which is the output of the device, a clock pulse generator, two keys and two digital sine-cosine function converters, n The left inputs are connected to the outputs of the corresponding analog-digital converters, the second inputs are connected to the outputs of the sampling control unit, the third inputs are connected to the output of the clock generator through keys, the first outputs are connected to the inputs of the time generator and the corresponding inputs of the corresponding keys, the second outputs are device outputs including the inputs of the keys are connected to the third output of the block of relaxed samples, characterized in that, in order to expand its functionality, the multiplication unit, the third digitally sine-cosine function converter, the voltage and current sample sign registers, the transform control unit, the multiplication and transfer control unit, the phase clock generator and the third key are given, the first and second inputs of the multiplication unit are connected to the second outputs the first and second digital sine-cosine functions (L-transducers, the third input is connected to the first output of the multiplication and transfer control node, the output of the multiplication unit is connected to the first the input of the third digital sine-cosine function converter is the output of the device, the second input of this converter is connected to the output of the clock pulse generator via a third key, the third input of this converter is connected to the second output of the multiplication and transfer control node, the first and second outputs; said converter are device outputs, first inputs; counting registers are connected; the corresponding analog digital signal converters, the second ones (the INPUTS of the sample sign registers are connected respectively to the first and second outputs of the sampling control unit, the outputs of the register of counts of counts are connected respectively to the first and second inputs

Description

l time intervals, the paired and second inputs of the conversion control unit are connected respectively to the first and second outputs of the time interval generator, the third input of the conversion control node is connected to the third output of the multiplication and transfer control node, four; the second input of the conversion control node, the second input of the control node

multiplying and transferring and the sixth input of the time interval generator is connected to the output of the phase clock pulse generator, the first output of the conversion control unit is the output of the device, and its second output is connected to the control input of the third key, the second input of the multiplication control node and the transfer is connected to the third output of the block sample management.

The invention relates to a measuring technique and can be used in information and measuring systems for measuring the amplitude values of voltage and current, the phase angle between them, the total, active and reactive power of harmonic signals in continuous and pulsed modes. The purpose of the invention is to expand the functionality by measuring the values of active, active and reactive power. Fig. 1 shows a block diagram of a digital device for measuring parameters of harmonic signals ;. 2 is a block diagram of a digital sine-cosine fuction transducer; FIG. 3 is a block diagram of a time generator; time intervals; 4 is a flow chart of a transform control node; Fig. 5 is a block diagram of the multiplication and transfer control node (Fig. 6 (a-k)) - timing diagrams explaining the operation of the device; Fig. 7 is the truth table of the node determining the phase angle values. . . The digital device for measuring the parameters of the harmonic signals contains two analog-to-digital converters 1 and 2, a sample control unit 3, three digital sine-cosine functions of the converter 4-6, a multiplication unit 7, a generator of 8 clock pulses, a generator of 9 clock pulses of the phase, registers 10 and 11 characters of voltage and current samples, shaper 12 time intervals, conversion control node 13, multiplication and transfer control node 14, switches 15-17, inputs 18 and 19, and device outputs 20-26, inputs 27-29, and outputs 30 and 31 functional converters 4-6, inputs 32-37 and outputs 38-40 of the imaging unit 12, inputs 38, 39, 41 and 42 and outputs 43 and 44 of node 13, ia also inputs 45 and 46 and outputs 47149 of node 14. Information inputs 18 and 19, the devices are connected to the information inputs of the analog-digital converters 1 and 2, in addition, one of the device inputs 18 is connected to the sample control unit 3. The outputs of analog-to-digital converters 1 and 2 are connected to information inputs of registers 10 and 11 digit counts and information inputs 27 of digital sine-cosine function converters 4 and 5, whose outputs 31 are multiplications 7 and outputs 20 and 21 amplitude values voltage and current signals of the device, and the outputs 30 are connected to the inputs 34 and 36 of the generator of 12 time intervals and the switching off inputs of the keys 15 and 16. The first and second outputs of the sampling control unit 3 are connected to the control inputs ana digital-to-digital converters 1 and 2, inputs 28 for controlling the installation of functional converters 4 and 5, and second inputs for entering characters of registers 10 and 11, and the third output of unit 3 is connected to the enabling inputs of keys 15, 16, the gate input 35. Shaper 12 and the first input 5 node 14 controls the multiplication and transfer. The output of the generator 8 clock pulses conversion is connected to the inputs of the keys 15 and 16, the outputs of which are connected to the inputs 29. the clock pulses convert functional converters 4 and 5, as well as to the input of the key .17 whose output is connected to the input 29 of the third functional converter 6, the outputs of the registers The 10 and 11 characters of the voltage and current samples are connected to the inputs 32 and 33 of the generator 12, the third output of which AO is the output 23 of the device phase sign, and the first and second codes 38 and 39 are connected to the first and second inputs of the control unit 13 Yeni transformation. The output of the generator 9 phase clock pulses is connected to the input 37 of the generator 12, the fourth input 42 of the node 13 and the second input 46 of the node 14 of the multiplication and transfer control. The third input of multiplication unit 7 is connected to the first output 47 of node 14, and the output of unit 7 is connected to the information input 27 of digital-functional converter 6 and is the device output 22 of the apparent power value. The installation control input 28 of the functional converter 6 is connected to the second output 4 of the node 14, the outputs 31 and 30 of the functional converter 6 are the outputs 25 and 26 of the device of the values of reactive and active power, respectively. The third input 41 of the conversion control unit 1 is connected to the third output 49 of the multiplication and transfer control node 14. The first output 43 of the control unit 13 of the transform is output 24 of the device of the phase code, and the second output 44 of the node 13 is connected to the control input of the key 17. The digital sine-cosine function converter (4-6) contains the register 50 of the sinus component, register 51 cosine component and four adders 52-55 The information inputs 27 of functional converters 4 and 5 are connected to the installation input of the register 50 of the sine component and the installation input of the register 51 cosine component. In the functional converter 54, the information input 27 is connected only to the setup input of the register 51, and the setup input of the register 50 is connected to the O bus. The installation control input 28 in the functional converters 4 and 5 is separately connected to the register installation control input 50 and the register control input 51, and in the converter 6, the inputs of the register setting control are connected together. Clock input 29 is connected to the pulse inputs of registers 50 and 51 of the sine and cosine components in all functional converters in the same way. The outputs of the bits of the register 50 of the sinus component are connected to the inputs of the corresponding bits of the adders 52 and 53 and shifted () to the lower bits with the inputs of the bits of the adder 54 and are the output 31 of the function transducer of the amplitude value of the signal in converters 4 and 5 and the reactive power values in the converter 6. The outputs of the bits of the register 51 of the cosine component are connected to the inputs of the corresponding bits of the adders 53 and 54 and shifted (p + l) to the bits of the younger bits with the inputs of the bits of the adder 55 and are the output 30 of the function converter of the active power value in the converter 6, and in the converters 4 and 5 the output is the sign bit register. The outputs of the bits of the adder 54 are connected with a shift by p bits, towards the younger ones to the inputs of the bits of the adder 52. The outputs of the bits of the adder 52 are connected to the inputs of the corresponding bits of the register 50 of the sinus component. The outputs of the bits of the adder 55 are connected with a shift by p bits towards the younger ones to the inputs of the bits of the adder 53. The outputs of the bits of the adder 53 are connected to the inputs of the corresponding bits of register 51 of the cosine component. Shaper 12 time intervals (FIG. 3) Contains the decoder 56 control commands, shapers 57 and 58 time intervals of the voltage and current phase, switching circuit 59 switching difference trigger 60, decoder 61 minimum difference intervals, decoder 62 characters, inverter 63 and shaper 64 pulses of phase angle. The first and second inputs 32 and 33 of the driver 12 are connected to the inputs of the decoder 56, the first output of which is the output 39 of the command Pro m / reverser driver 12, the second output of the decoder 56 is connected to the inputs of the driver 64 directly and through an inverter 63, the third output of the decoder 56 connected to the first input of the decoder 62. The third 34 and five 36 inputs of the imaging unit 12 are connected respectively to the first inputs of the formers 57 and 58, and the fourth input 35 is connected to the second inputs of both the formers 57 and 58. The outputs of the formers 57 and 58 are connected with the inputs of the switching circuit 59 and the decoder 61. The output of the switching circuit 59 is connected to the C input of the flip-flop 60, whose output and inverse outputs are connected to the second inputs of the switching circuit 59, and also connected to the second input of the decoder 62 and its own D input respectively. The output of the decoder 62 is the output 40 of the sign of the phase of the former 12. The sixth inlet 37 is connected to the inlets of the former 64, the remaining inputs of which are connected to the first and second outputs of the decoder 61, the output of which is the output 38 of the pulses of the phase unit 12 of the body. Conversion control node 13 (Fig.4) contains a phase counter reversing counter 65, counter zero state decoder 66, counter 67 trigger delayed by a phase time interval, inverter 68, coincidence circuit 69, or pulse control circuit 70 and two circuits 71 and 72 coincidentally controlling the reset of the counter. The first input 38 of the node 13 is connected to the first inputs of the matching circuit 69 and the OR circuit 70, the second input 39 of the node 13 to the second input of the matching circuit 69 and the first input of the matching circuit 71 directly and. through the inverter 68 with the second input of the OR circuit 70 and the first input of the circuit 72 coincidence, the third input 41 of the node 13 - with the fourth input of the I-UIK circuit 70 and the installation input of the single state of the trigger 67, the fourth input 42 of the node 13 - with the third input of the circuit OR 70. The outputs of the coincidence circuit 69 and the OR circuit 70, the control switching of the phase pulses, are connected respectively to the forward and reverse counts of the phase angle counter 65. The outputs of matching circuits 71 and 72 controlling the initial installation of the counter are connected to the corresponding inputs of the installation in the state O and 180 of the counter 65. The output of the counter 65 is the first output 43 of the node 13 of the phase angle and connected to the input of the decoder 66. The output of the decoder 66 is connected to the setup input to the zero state of the trigger 67, and the trigger output is the second output 44 of the delayed phase interval of the conversion control unit 13. The multiplication and transfer control unit 14 (FIG. 5) contains a multiplication interval counter 73, a second conversion interval counter 74, a multiplication interval trigger 75, a second conversion interval trigger 76, a multiplication unit transfer pulse decoder 77, a functional converter setter decoder 78, two keys 79 and 80 and the one-shot 81. The first input 45 of the node 14 is connected to the installation input of the single state of the trigger 75 via the Si one-shot, the second input 46 of the clock pulses is connected to the inputs of both counters via the keys 79 and 80 the key input 79 is with the trigger output 75, and the key control input 80 with the trigger output 76, the key 79 output is the first output 47 of the multiplication and transfer control unit 14. The output of the high bit of the counter 73 is connected to the input of the zero-state setting of the trigger 75 and the single-state setting of the trigger 76: The outputs of all bits of the counter 73 are connected to the inputs of the decoders 77 and 78. The output of the decoder 77 together with the output of the key 79 ow The first output 47 of node 14, the output of the decoder 78 - the second output 48 of node 14, the output of the trigger 76 - the third output 49 of the node 14. The output of the key 80 is connected to the input of the counter 74, the output of the higher bit of which is connected to the trigger 76 The device is working next way.

The input signals of the voltage U and the current L are supplied to the information inputs 18 and 19 of the device, from where it is fed to the information inputs of the analog-digital converters 1 and 2, and one of the signals, for example, U is fed to the input of the sampling control unit 3. Correspondingly, the frequency of the input signal, block 3 sets the moments of samples of the instantaneous values of the input signals with pulses i and C separated from each other by a time equal to the duration of a quarter of the repetition period of the input signal, which corresponds to the phase angle, wound 90 (FIG. 5 a, b) . After a time sufficient to convert the input signal into a digital code, after a pulse ig, a pulse is generated to control the installation of the sine-component registers of functional converters 4 and 5, and after a pulse 90, a control pulse of the installation of registers of the cosine component of functional converters 4 and 5. Sample control pulses are fed to the control inputs of analog-digital converters 1 and 2, and the control pulses for setting the registers are fed to the inputs 28 of functional converters 4 and 5, and to the inputs of entering the characters of the registers 10 and 11. At the indicated times, analog-digital converters 1 and 2 convert the input signals into a digital code, while through the information inputs 27. the absolute values of the samples corresponding to the moment t (j) 6 registers 50 sine component, and the absolute values of the samples corresponding to the moment 90 in the registers .51 cosine components of the functional transducers 4 and 5. At the same time, the registers 10 and 11 are counted from the outputs of the corresponding ADCs in current and voltage.

After the samples have been taken and entered into the registers, the sample control unit 3 generates the enable signal of the first functional transformation, which is fed to the inclusive inputs of keys 15 and 16. This allows the conversion clock pulses, developed by the generator 8, to pass through the keys

15 and 16 to the inputs of 29 clock pulses of functional converters 4,5. With the arrival of clock pulses on the functional converters, the process of the first sine-cosine functional transformation begins, at which the values entered in the registers of the sine components start to increase according to the sine law, and the values entered in the registers of the cosine components start to decrease according to the cosine law ( Fig.5 g, d, e, k). In this way, .

5, with each conversion cycle, it is as if the vectors U and 3 are rotated through a certain angle LSR to the position of the zero phase (Fig. 5a). The input of the conversion clock to the functional converters in time is uniform, and therefore the rotation of the vectors is uniform in time. Time intervals from the beginning

5 transformations up to the moments when the vectors reach the zero phase indicate the phase angle between the vectors cf.

Sine cosine transform

0 with the absolute values of the samples is made within one quadrant, and the determination of the phase angle between the vectors is made depending on the signs of the samples according to the table in Fig. 7.

The signal that the vector has reached the zero phase value is a change in the sign in the sign bit of the core of the cosine component 51

functional converter A. . or 5 (P ,, P). The outputs 30 of the sign bits of the registers 51 functional converters 4 and 5 are fed to

5 shaper 12 time interval and the switching off inputs of the keys; 15 and 16. Therefore, when each of the vectors reaches the zero phase, the conversion clock pulses to this functional converter, as well as the further rotation of the vector, stop, in the registers 50 of the sinus components, the amplitudes of the vectors are set. Vokody 31 registers 50 sine components of functional converters 4 and 5 are the outputs of the amplitude values of the voltage signals U and the current I of the device

(exits 20 n 21). The driver 12, by changing the signs of the registers 51 of the cosine components of the functional converters 4 and 5, depending on the sample signs from the frequencies 2i and f received from the generator 9 phase clock pulses, generates a certain number of phase pulses and a command for counting and initial setting the phase counter with in order to make the correct determination of the phase angle between the voltage and current vectors by the rules indicated in Fig. 7. Signs of counts from the register of signs 10 and 11 arrive at the first 32 and second 33 inputs of the splitters 12, on the basis of which at the first output of the decoder. a direction command is generated: a setup for the initial installation of the ase forward / reverse switch, which enters output 39 of the driver 12. On the second output of the decoder 56, a summation command or subtraction of phase angles is generated (tpq + (f-) / (V} - (j );) and at the third output, a preliminary signal of the phase sign. At the third 34 and fifth 36 inputs of the former 12, the signals of the cosine of the components of the 30 outputs of the functional converters 4 and 5, which make up the strobe-pulse of the first fun1, equator converter Locale 3. Of these signals, the formers 57 and 58 form the time interval Е.1 i (. and i (n- proportional to the phase angles of the voltage and current vectors with respect to the calculation moment). From the outputs of the formers 57 and 58, the signals, on the one hand, arrive at the inputs of the difference sign determining control node (from (, - (Oj consisting of switching circuit 59 and trigger 60, on the other hand, to decoder 61 inputs, which extracts the minimum interval signals from incoming icpy and their difference interpolation (itf -icf ,) Depending on which interval of 10, and .tin- is greater, trigger 60 uses a switch 59 to generate a difference sign signal (Cft, -tf,). T s1 (,,, Te ((f, 4f;) 0, then the trigger 60 is set to state O. Based on the signal from the output of the trigger 60 and the signal from the third output of the decoder 56 to the decoder 62, the signal of the phase sign is outputted AO of the generator 12, the device with output 23 of the device. The sixth input 37 of the generator 12 from the generator has 9 phase clock pulses - clock pulses with a frequency and double frequency 2i are received. These pulses arrive at the corresponding inputs of the fan 64, which is commanded

  H; ) coming from the second output of the decoder 56 directly and through the inverter 63, based on the pulse duration i (r, and coming from the outputs

I TP1 h I

decoder 61, generates the number of clock pulses of the phase, proportional to the sum or difference of the phase angles (2 i. biqi) k (tf 4-qi;) ,,. К (Ч „Ч;). These pulses come from the output of the former 64 to the first outlet 38 of the former 12.

The presence of a separate generator 9 phase clock pulses is necessary to obtain a phase reading in degrees, FOR WHICH it is not feasible times the 1st scale of the pulses of the generator 8 conversion.

The phase pulses from the first output 38 of the generator 12 time intervals are fed through the first input 38 of the conversion control section 13 to the forward or reverse counting inputs of counter 65. Switching pulses to the counter inputs are controlled by the coincidence circuit 69 or the OR 70 circuit, depending on the command Pr the MO / reverse input to these circuits from the second input 39 of the node 13. At the command PRomo / reverse, the initial state of the counter 65 is preset through the diagrams 71 and 72 of the match according to the rule for determining the phase depending on the signs readout The phase angle counter 65 counts the phase pulses and its final state corresponds to the phase angle between the voltage and current vectors in degrees. From the output of counter 65, the parallel binary-decimal code of the phase angle goes to output 43

conversion control unit 13, and from there to the output 24 of the device. The determination of the phase angle and the amplitude values of the voltage and current is made during the first functional conversion. At the end of the first functional transformation on the falling edge of the strobe pulse of the first transformation coming from the sampling control unit 3 to the first input 45 of the multiplication and transfer control unit 14, the one-shot 81 produces a pulse of setting the trigger 75 of the multiplication interval to a single state. From the moment the trigger 75 is set to one, the clock pulses from the second input 46 of the node 14 through the key 79 to the input of the counter 73 and to the output 47 of the node 14 are allowed, which then go to the third input of the multiplication unit 7 as clock pulses for performing a multiply operation. The output 47 of node 14 receives the first multiplication interval pulse allocated by the decoder 77 according to the state of the counter 73, which serves to enter in the registers of the multiplication unit 7 of the amplitude values of the voltage and current entering the first and second inputs of the unit 7 from outputs 31 registers 50 sinus components of functional converters 4 and 5 of the voltage channel and the current channel. .After transferring the amplitude values, the multiplication operation begins by block 7 on the USEG multiplication pulses, arriving from the first output 47 of node I 14. The receipt of the multiplication clock pulses continues until jioKa does not overflow the multiplication interval 73, resulting in a signal from the output of the most significant bit of the counter 73, the trigger 75 of the multiplication interval is set to the zero state and the passage of clock pulses through the key 79 to the multiplication unit 7 and the counter 73 stops. On this, the multiply operation is terminated c and the result of multiplying from the output of block 7 enters the output 22 of the device as an apparent power value iri, and is also entered into the register 51 of the cosine component of the function converter 6. The momentum of transferring the value of the apparent power to the register 51 and setting the function converter to zero value 50 6 is fed to the setup input 28 from the second output 48 of the multiplication control node 14, and transfer, where it is generated by the decoder 78 according to the final state of the multiplier interval counter 73. The output signal from the station At the same time, the counter 73 is simultaneously set to the zero state of the trigger 75 and the trigger state 76 of the second functional transformation interval is set to one. By setting trigger 76 to a single state, the signal from its output allows the arrival of phase clock pulses to the counter 74 of the second functional conversion interval through key 80 from input 46 of node 14. Trigger 76 is in single state until it overflows the counter 74 of the interval of the second conversion and the signal from the output of the most significant bit of the counter do not return it to the zero state, after which the further arrival of pulses to the counter 74 ceases. The output signal from the trigger 76 of the second conversion interval goes to the third input 49 of node 14, and from it to the third input of the node 13. At node 13, the signal of the second functional conversion interval comes from the third input 41 to the fourth input of the OR circuit 70 and simultaneously sets the unit state trigger trigger 67 delayed phase time interval. The control signal at the fourth input of the OR 70 circuit allows the arrival of clock pulses of the phase from the input 42 of node 13 through the circuit OR 70 to the counting input of the counter 65 of the phase angle. When the number of phase clock pulses equal to the state of the phase counter is input to the counting input, the counter returns to the zero state, the decoder 66 of the zero state of the counter generates a trigger setting signal 67 to the zero state. In this way, the trigger 67 is in the unit state such time 1 (| which takes the interval it. The delay .iq of the signal seemed to take place for the time required to perform the multiplication operation. The signal "from the trigger output 67 goes to the output 44 of node 13, it is sent to the control input of the switch 17. This signal permits the passage of conversion clock pulses from the generator 8 to the third input 29 of the functional

converter 6 through key 17 A second sine-cosine functional transformation occurs as a result of which the apparent power vector is rotated & in the functional converter 6 by an angle (f (Fig.5 and K). As a result, the registers of the functional converter 6 are set to the values of the reactive Ulsin q of the active UIcosСР signal power. These values from the outputs 30 and 31 of the functional converter 6 go to the outputs 25 and 26 devices.

Thus, two instantaneous values of the voltage signal (J and two instantaneous values of the signal i, separated by a quarter of a period from each other, using the proposed device, are used to comprehensively measure the parameters of two harmonic signals: the amplitude values of the voltage U and the current T., as well as the phase angle between the signals of the values of apparent S, reactive Q and active power R. Measuring the parameters of the signals is possible both in continuous and in pulsed modes.

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Claims (1)

DIGITAL HARMONIC 'SIGNALS MEASUREMENT DEVICE device, containing two analog-digital converters, the first inputs of which are device inputs, a sampling control unit, the input of which is connected to one of the device inputs, and the first and second outputs - to the corresponding second inputs of analog-to-digital converters, intervals, the output of which is the output of the device, a clock generator, two keys, cha and two digital sine-cosine functional converters, the first inputs which are connected to the outputs of the corresponding analog-to-digital converters, the second inputs - with the outputs of the sampling control unit, the third inputs - with the output of the clock generator through the keys, the first outputs are connected to the inputs of the time slot generator and including the inputs of the corresponding keys, the second outputs are device outputs, including The key input inputs are connected to the third output of the sampling control unit, characterized in that, in order to expand the functionality, a multiplier block is introduced into it a third digital sine-cosine functional converter, voltage and current sample sign registers, a conversion control unit, a multiplication and transfer control unit, a phase clock and a third key, the first and second inputs of the multiplication unit being connected to the second outputs of the first and second digital sine-cosine functional converters, the third input is connected to the first output of the node, control the multiplication and transfer, the output of the multiplication unit is connected to the first input of the third digital s the cosine functional converter is the output of the device, the second input of this converter is connected to the output of the clock pulse generator through the third key, the third input of this converter is connected to the second output of the multiplication and transfer control unit, the first and second outputs of the converter are the device outputs, ^ the first the inputs of the `` registers of counting signs are connected to the outputs of the corresponding ans.logo '' digital converters, the second ω with: 1182425 A, the inputs of the sample sign registers are connected respectively with the first and second outputs of the sampling control unit, the outputs of the sample sign registers are connected respectively with the first and second input of the generator 1182425 for time intervals, the first and second inputs of the conversion control unit are connected respectively with the first and second outputs of the shaper time intervals, the third input of the transformation control unit is connected to the third output of the multiplication and transfer control unit, the fourth input of the conversion control unit In addition, the second input of the multiplication and transfer control unit and the sixth input of the time slot generator are connected to the output of the clock generator ^: phase output pulses, the first output of the conversion control unit is the output of the device, and its second output is connected to the control input of the third key, the second input of the control unit the “shearing” mind is connected by a transfer to the third output of the sampling control unit.