SU1688198A1 - Tester for determining peak duration and trialngular video impulse amplitude - Google Patents

Abstract

The invention relates to a pulse technology and can be used in measuring devices. The purpose of the invention is to extend the functionality by determining the temporal position of the maximum of not only symmetrical, but also asymmetrical triangular video pulses and ensuring the measurement of their amplitude. To achieve the goal, a device containing voltage divider 12, comparators 8.9, differentiation elements 10.11, elements NOT 25, 26, elements OR b. triggers 5, 21-23. adders 30, 33, block 28 at m-knife, delay elements 7.39, groups of elements 51, and a generator 35 linearly varying

Description

(L

with

but

X

x

her x

voltages, switches, 44, peak detectors, trigger 24, inverters 27,31,3,40,41, multiplication blocks 29,36, 37, division blocks 45,46, matching amplifiers 47.48, analog-digital converters 49, 50. The operation of the device is based on a linear approximation of the front and the fall of the video pulse by two points obtained by crossing the reference voltages formed at the input and output of the divider 12. The intersection moments are separated by comparators 8.9 and

The invention relates to a pulsed technique and can be used in measuring devices.

The purpose of the invention is to expand the functionality by determining the temporal position of the maximum of not only symmetrical, but also unbalanced triangular video pulses and providing measurement of their amplitude.

The drawing shows a block diagram of the device.

The device includes bus 1 Start bus 2 Stop, input bus 3, first bus 4, reference voltage, first trigger 5, first element OR 6, first delay element 7, first and second comparators 8 and 9, first and second differentiation elements 10, 11 , divider 12 voltage, first, second, third, fourth keys, first, second, third, fourth peak detectors 17-20, second, third, fourth, fifth triggers 21-24, first and second elements NOT 25 and 26, the first inverter 27, the first and second blocks 28, 29 multiplying, the first adder 30, the second inverter 31, the third inverter the torus 32, the second and third adders 33 and 34, the generator 35 of linearly varying voltage, the third and fourth blocks 36 and 37 multiplication, the fourth adder 38, the second delay element 39, the fourth and fifth inverters 40 and 41, the fifth adder 42 , second element OR 43, fifth key 44, first and second division blocks 45 and 46, first and second matching amplifiers 47 and 48, first and second analog-digital differentiators with 10.11 differentiations. A linear time scale is generated by a generator 35. Triggers 21-24, keys 13-16

and peak detectors G / -20 provide for the fixation of voltages corresponding to moments of voltage crossing the input pulse of the reference levels. The remaining blocks provide the calculation of the abscissa and ordinate of the intersection point of the two approximable direct, i.e., the temporal position of the maximum of the triangular video pulse and its amplitude. 1 il.

five

0

0

5 0 5 0 5

I

formers 49 and 50, the first and second groups 51, 52 of elements AND, the third element OR 53, the first and second output buses 54, 55, the second bus 56 of the reference voltage.

Bus 1 is connected to the trigger input of the generator 35, bus 2 is connected to the first drive of the first element OR bis by stopping the input of the generator 35, the output of which is connected to the signal inputs of keys 13-16. The input bus 3 is connected to the first passages of the first and second comparators 8 and 9, the bus 4 is connected to the second input of the second comparator 9, to the first input of the first multiplication unit 28 and to the input of the divider 12, the output of which is connected to the first input of the second multiplication unit 29 and the second input of the first comparator 8. The outputs of the first and second comparators 8 and 9 are connected to the inputs of the first and second differentiation elements 10 and 11, respectively. The output of the second differentiation element 11 is connected to a single turn of the third trigger 22 and through the second element NOT 26 to a single input of the fourth trigger 23. The output of the first differentiation element 10 is connected to a single input of the second flip-flop 21, and through the first element NOT 25 to a single input of trigger 24 and the inputs of the second delay element 39.

The inverse outputs of the flip-flops 21-24 are connected to the control key inputs, respectively, the outputs of which are connected to the signal inputs of the peak detectors 17-20, respectively, the control outputs of which are combined and the HORD w from the element OR 6. The output of the first peak detector 17 is connected to the rgrv input the third multiplication block 36 and through the first inverter 71 - g. the first input of the first adder 30; The output of the second peak detector 18 is connected to the first input of the fourth multiplication unit 37 and through the second inverter 31 to the first input of the second totalizer 33- and third output of the peak detector 19 is coupled to second inputs of the second 33 and fourth summation block 3 & multiply. The output of the fourth peak detector 20 ccc dinene with the second inputs of the first adder 30 and the fourth multiplication unit 37. The output of the first adder 30 through the third inverter 32 is connected to the first input of the third adder 3 - to the second input nepsoi of the multiplication unit. The output of the second adder 33 is connected to the second inputs of the gre of the adder G 1 and the second multiplication unit 29. The outputs of multiplication unit 28 and 29 are connected respectively to the first and second inputs of the fourth adder 38, the output of which is connected to the input of the depot of the first big battery; (5 divisions. The third output, on the sum 3, through the fourth input, Z0 is connected to the first input of the second element OR in, the second the input of which is connected with the output of the fifth key h -t, the sigms input of which is connected to the VTO1 of the school 56, and the control input with the inverse output of the first trigger 5. The output of the second element OR 3 is connected to the input of the divider block V3, 6 divisions. The outputs of blocks 36 and 3 / multiplied by and, the second one is direct, and the first one through the fifth inverter 1 is connected to the inputs of the fifth adder 2, the output of which is connected to the input of the splittable second division block 6. The outputs of the division blocks 5 and 6 are connected through analogous amplifiers 7 and 8 digital converters k $ and 50, the outputs of which are connected bitwise with the first inputs of groups of elements And 51, 52, the second inputs of which are combined and connected to the output of the second delay element 39. The outputs of group 52 of the elements And are connected in bit with the output bus 55. The outputs of group 51 of the elements of And are connected in bit with the output bus 5 and with the inputs of the third element OR 53,

0

five

The output of which is connected to the PTOR module of the element OR 6, the output of co-G 1 is connected to the input of the first and 7 delays and to the zero-PUT of the erg trigger. The output of the delay element 7 is connected to the zero inputs of the triggers. Adders 3, 33, 3, 38, 7 can be implemented as a two-input summing amplifier that implements the operation

1% u -,

i (

where k is the weighting factor, subsequently adopted odnochkovym for all adders. Blocks 28, 24, 36, 37 multiplications can be implemented as a multiplication device on quadrants implementing the operation

willows kЈUB 1 iwh g,

where k 1 / UHOW- is the same for all

multiply blocks.

Blocks 5, 6 divisions - in the form of any of the division schemes, which ialize the operation

thirty

U,

its

, / 1 VX )

five

0

five

0

five

where k 1 k2 is the same for all

rtj octave delieur Investors 27, 31, 32,, k - in the form of an inverting amplifier. In addition, the secondary circuits of the flip-flops 5, 21-2, And 51, 52 epimets contain diode isolation circuits, negative polarity pulses, and low-frequency filters (capacitors), which ensures their operation in a pulsed mode.

The essence of the device operation is that the linear approximation of the front and the fall of the video impulse is carried out by two front and fall points, obtained at the moments of the last two fixed thresholds crossing, the resulting direct extrapolated to the intersection, the abscissa of the intersection shows the temporal position of the video impulse, and the ordinate of the intersection gives the amplitude value,

We will find the relations allowing to determine the abscissa and ordinate of the point of intersection of two straight lines

The equation of a line passing through two points of the front can be represented as:

U (t (UjLI-Mt-t-UUl-I-UUl, t - t,

where t.j, te are the moments of time of intersection of the front with the voltage levels U, UU, respectively.

Similarly, the equation of a straight line passing through two points of decay:

and (t) ilLi-iMЈ.t.ti.: - tiut r

and&

wh

 - the moments of time of intersection of the decay of the video pulse with the levels of U and U, respectively.

reading that at the point of intersection / u the ordinates are the same, we write:

(U.-.. T,

(Ui JJiit

Hh

from where

t - (ttyL t tty) /

t4 - C

H - t

,, Vg - U U, .t.

 4 - t, t - t -tj + t -t

For triangular video pulses, the amplitude value is the ordinate of the intersection point, which is easy to determine by substituting the found value of t, 0 into the equation of any direct line. Wherein

and () x w h-h () x

t) - 44-t, + tt-t4

w Ui (tj.) - U (t2 - tz.), H - t, - t3 -H t2

The device works as follows.

In the initial state, the triggers 5, 21-24 are reset. Peak detectors 17-20 reset. Unit levels from the inverse outputs of the triggers close the keys. Unit level with inverse output first

the trigger 5 closes the fifth patch M, allowing the reference voltage to flow from the bus 56 to the inputs of the divider of blocks 5 and 6 of the division to eliminate the division by zero operation. Gene

The rator 35 is stopped, and at its output is zero voltage. The bus 4 is supplied with the voltage value of the second threshold measurement U2, from which the voltage of the first measurement threshold V is generated using the divider 12. The voltage measurements of the measurement thresholds U and U1 are fed to the second inputs of the comparators 9 and 8, the outputs of which are due to no

0 the voltage on the input bus 3 is set to zero levels, as well as to the first inputs of blocks 28 and 29 multiplications,

The device is triggered by a pulse on bus 1, which is fed to the starting input of generator 35. The latter forms a voltage of the form:

five

U

8S

kt

l

those. timescale.

Ueb voltage (K through public keys is applied to peak detectors 17-20, which track

its meaning.

The occurrence of voltage at the outputs of peak detectors 17-20 causes transients in the associated elements, which are of no interest, since they only lead to the appearance of unused codes at the outputs of analog-to-digital converters 9 and 50.

When the voltage of the front of the video pulse entering the input bus 3 reaches the voltage of the first measurement threshold, a single positive voltage jump appears at the output of the first comparator 8,

wherein the first differentiation element 10 forms a positive polarity pulse, which translates the second trigger 21 into a single state. The negative polarity pulse appearing at the output of the NOT 25 element is eliminated by the input circuits of the 2k and 23 flip-flops and And 51, 52 elements. The zero level with inverse. the second trigger output 21 times

connects the first switch 13, which causes the voltage kt to be fixed at the output of the first peak detector 17, where t is the instant of intersection of the first measurement threshold by the deo impulse of the first measurement threshold.

When the voltage of the video pulse front reaches the second measurement threshold U at the output of the second comparator 9, a single positive voltage jump appears from which the second differentiation element 11 forms a positive polarity pulse that translates the third trigger 22 into a single) 5 state . The negative polarity pulse from the output of the He element 26 is canceled by the input circuits of the fourth trigger 23. The zero level from the inverse output of the third trigger 22 opens the second switch 1, which leads to a fixation at the output of the second peak voltage detector 18 kt, where tЈ - the moment when the front of the video pulse crosses the second measurement threshold 25.

When the voltage drops across the video pulse of the voltage of the second measurement threshold U, a single negative voltage jump appears at the output of the second comparator 9, from which the second differentiation element 11 forms a negative polarity pulse that suppresses the input circuits of the third trigger 22. The pulse of the positive field the second element HE 26 translates the fourth trigger 23 into a single state. The zero level from the inverse output of the fourth trigger 23 opens the third key 15, which leads to a fixation of the voltage ktj at the output of the third peak detector 19, where t is the moment when the second impulse 45 of the measurement threshold crosses the drop.

When the voltage crosses the voltage drop of the voltage pulse} q of the first measurement threshold, the output of the first comparator 8 is a single negative voltage drop, from which the first differentiation element 10 forms a negative polarity pulse, which is damped by the input circuits of the second trigger 55 21. A positive polarity pulse from the output of the first HE element 26 translates the fifth and first triggers 2k and 5 into a single state and act 30

35

40

em to the input of the second element 39 for - holding. The zero level from the inverse output of the second flip-flop 2 opens the fourth key 16, which causes the fourth peak voltage detector 20 to be fixed at the output kt4, where C4 is the moment of intersection of the first measurement threshold with the video pulse. The zero level from the inverse output of the first trigger 5 opens the fifth key kk, which ensures that non-zero voltage is supplied to the inputs of the divider blocks k $ and 46 divisions only from the output of the third adder 3k.

Further operation of the device will be considered at the time of completion of transients in its elements.

The fourth multiplication unit 37 forms at its output a voltage proportional to the product of the voltages from the outputs of the second and fourth peak detectors 18 and 20:

2

U

6WX-57

 k

Vtt4

45

The third multiplication unit 36 forms, at its output, a voltage that is proportional to 30 times the product of the voltages from the outputs of the first and third peak detectors 17 and 19

JebfX.36C k L2HC3)

which is inverted by the fifth inverter k and supplied in conjunction with the voltage and. ,,,, a, to the inputs of the fifth totalizer. you are

ra2, at the output of which a voltage is formed proportional to the sum of the input voltages

,one

ivykh.4ge kik

-t.V,

which is fed to the input of the divisible second division 6 block.

The first adder 30 forms at its output a voltage proportional to the sum of the voltages from the output of the fourth peak detector 20 and the inverted voltage from the output of the first peak detector 17:

U

out "about

-k k, (t4 -t,),

which is inverted by the third inverter 32 and fed to the second input of the first multiplying unit 28 and to the first input of the third adder 3,

the second input of which has a voltage from the output of the second adder 33

Wj3 k Mch -Ch,

which leads to the formation of the output of the third adder 34 voltage

U

 -k k, (t -t, -t, + t2) 10

EXIT 34 which is inverted by the fifth inverter 40 and through the second element OR 43 is fed to the input of the divider of the blocks 45 and 46 of the division.

The division block 46 forms at its output a voltage proportional to the quotient of the stresses acting on its inputs.

 Ii i a 4ti :: -LЈ2L

ivykh.4b k k (t4 - t3 + t2T

 considering that k3 1 / kz,

 kltlt4 -tLt3)

ivyh46, -t3 + t2)

The multiplication unit 28 forms a voltage at its output.

UBb, X.28 -V, and block 29 multiplying

 ivyh k k, k2V4 - 1

which leads to the formation of the output of the fourth adder 38 voltage

U

vy.G (t4 -t,) -40

,

which is fed to the input of the dividend first division block 45 .45

The block 45 division forms at its output voltage

 (t4 itO-Uilta-tz.) U6bix.45 (t4)

Uz (,) - ()

 h

Amplifiers 47 and 48 are designed to match the output dynamic range of dividing blocks 45 and 46 with the input dynamic range of analog-digital converters 49 and 50. When the dynamic ranges coincide for the considered case, the gain of the matching amplifier 48 is equal to, and the matching amplifier 4 is one which allows to obtain at the output of the analog-digital converter 50 a code for the temporary position of the video pulse:

t u 0 t4 -t1 -t, + tz

and the output of the analog-digital converter 49 is the amplitude code for triangular and sawtooth video pulses

U

 .i.ti)

h - tr h

No

0

five

0

five

40

45

50

five

Pulse from the output of the second delay element Ze, delayed by the maximum transient time in the device elements, defined as the total response time of the adder 30, inverter 32, multiplication unit 28, adder 38, division unit 45, matching amplifier 48, analog-digital converter 51 , reads the codes in the belt position and the amplitude of the video pulse from the bit outputs of the analog-digital converters 49 and 53 and through the groups of elements And 51, 52 outputs them to the output buses 54Л 55. The pulses from the outputs of the group of element And 51 about The third element OR 53 is combined, and the received pulse through the first element OR 6 zeroes the first trigger 5 and the peak detectors G / -20, and is also fed to the input of the first delay element 7. A pulse from the output of the first ele ment / delay, which is delayed by the time of zeroing of the peak detectors 17–20, zeroes the triggers 21–24.

The device is ready to measure the temporal position and amplitude of the next video pulse,

Upon completion of measurements, a pulse is applied to the bus 2 of the device, which stops the generator 35, after the first element OR 6, the first trigger 5 and the peak detectors 17-20, as well as the peak delay element 7, triggers 21-24 are zeroed.

Device - in its original state

Thus, the device allows to determine the position of the maximum

I JI-3 1

and znamenny amplitudes for asymmetrical triangular video pulses.

Claims (1)

Invention Formula A device for determining the time position of the maximum and measuring the amplitude of triangular video pulses, comprising a voltage divider, first and second comparators, first and second differentiation elements, first and second elements NOT, first to third elements OR, first to fourth triggers, first and second adders, the first multiplying unit, the first and second delay elements, the first and second groups of elements AND, the first reference voltage bus connected to the input of the voltage divider, the input bus connected to the first and the inputs of the first and second co-drivers, whose outputs through the first and second differentiation elements, respectively, are connected to the inputs of the first and second elements, respectively, the output of the voltage divider is connected to the second input of the first comparator, the output of the first element is NOT connected to the input of the second delay element, the output of which connected to the first inputs of elements AND of the first group, the outputs of which are connected bitwise with the first output bus and with the inputs of the third element OR, the first inputs of the second group of elements AND interconnected, the output of the first element OR is connected to the zero input of the first trigger, characterized in that, in order to extend the functionality by allowing the determination of the temporal position of the maximum of not only symmetric, but also asymmetrical triangular video pulses and measuring their amplitude, generator of linearly varying voltage, from first to fifth keys, peak detectors from the first to the fourth, fifth trigger, from the first to the fifth inverters, blocks multiplying from the second to the hour tverty, the third through fifth adders, first and second dividing blocks, terminating the first and second amplifiers, first and second analog-to-digital converters, coupled to bus start triggering input generator linearly varying voltage bus Stop 0 0 i one 0 0 five 0 five  H connected,) with pgrvim PVM / II element) IIPI and with ogupnuy i n the st input of the generator is linear i rvn HIKI of the proper voltage, o; which is connected to the signal keys of the same fourth and fourth keys, the reference voltage bus being connected by the first step of the first smart block, the output of the voltage divider is connected to the first input of the second multiplication, the outputs of the first and second differentiation elements are connected to single inputs the second and third triggers, the outputs of the second and first elements are NOT connected to the single inputs of the fourth and fifth triggers respectively, the output of the first element is NOT connected to the single input of the first trigger a, the inverse outputs of the second to fifth triggers are connected to the control inputs of the first to fourth keys, respectively, whose outputs are connected to the signal inputs of the first to fourth detectors, the control inputs of which are connected to the output of the first OR element and the output of the first delay element the output of which, t is connected to zero inputs from the second to fifth triggers, while the output of the first peak detector is connected to the first input of the third multiplier multiplication and through the first inverter to the first input of the first summeto l, the output of the second peak detector is connected to the first input of the fourth multiplication unit and through the second inverter to the first input of the second adder, the output of the third peak detector is connected to the second inputs of the second adder and the third multiplication unit, the output of the fourth peak multiplier and the first adder, the output of which through the third inverter is connected to the first input of the third adder and to the second input of the first multiplication unit, the output of the second adder is connected to the second in The signals of the second multiplication unit and the third adder, the outputs of the first and second multiplication units are connected respectively to the first and second inputs of the fourth adder, the output of which is connected to the input of the divisible first division unit, the output of the third adder through the fourth inverter is connected to the first input of the second OR element, the second input which is connected to the output of the fifth key, the signal input of which is connected to the second bus of the reference voltage, and the control input to the inverse output of the first trigger, the output of the second IL element And connected to the inputs of the divider of the first and second dividing units, the output of the third multiplication unit through the fifth inverter is connected to the first input of the fifth adder, the second input of which is connected to the output of the fourth multiplication unit, and the output is connected to the input of the divisible second division unit, outputs the first and second dividing units through respectively the first and second matching amplifiers are connected to inputs, respectively, of the first and second analog-to-digital converters, the outputs of which are connected bitwise with the second inputs of the And elements, respectively, of the first and second , GROUPS, the first inputs of elements AND of the second group are connected to the output of the second delay element, and the outputs are bitwise connected to the second output bus, while the output of the third OR element is connected to the second input of the first OR element.