SU1753618A1 - Device for receiving signal of triple phase-shift keying - Google Patents

Abstract

The essence of the invention: the receiver contains phase detectors 1, 2, 3, 4, 5, 6, logic blocks 7, 16, 19, decoder 8, reference generator 9, five phase shifters 10, filter 11, adders 12, 17, block 18 single start-up, multipliers 13,14, block 15 synchronization. 1 hp ff, 4 ill.

Description

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Claims (2)

Claim 1. The receiver of the signals of three-fold phase manipulation by ed. No. 1492486, characterized in that, in order to increase the reliability of reception by improving the accuracy of estimating the magnitude of the mismatch between the phase of the received signal and the reference oscillator, a phase start block and a third logical block are introduced, and the outputs of the first logical block are respectively connected to the inputs of the phase start block and inputs the third logical block, the output of the cyclic synchronization and the clock output of the phase start block are connected respectively to the inputs of the cyclic and clock synchronization of the third logical block, the first, Torah and third outputs of which are vyhodamy'priemnika, and a fourth output connected to a third input of the adder. 2. The receiver according to claim 1, characterized in that the third logical unit consists of a decoder, three decoders, three reversible counters and an AND element, the inputs of the descrambler being the inputs of the third logical unit, the first, second and third outputs are connected to the inputs respectively, of the first, second and third decoders, the first outputs of which are the outputs of the third logic unit, and the second outputs are connected respectively to the inputs of the first, second and third reversible counters, the outputs of which are connected to the inputs of the element And, the output which is the fourth output of the third logical block, the clock inputs of the decoder and three decoders are the clock input of the third logical block, the cyclical input of which are the inputs of the cyclic synchronization of three decoders, and the clock inputs of the reversible counters.