SU321907A1 - DEVICE FOR SYNCHRONIZATION OF INCORPECTIVE BINARY RECEIVER DEVICES - Google Patents

Description

The invention relates to the field of radio engineering and can be applied to receive radio broadband noise-like signals.

A device for synchronizing non-coherent binary receivers is known that contains two synchronization channels, each of which consists of a multiplier, an integrator and an amplitude detector, a common adder for both channels, a pseudo-random sequence generator with a shift register, a clock generator, two balanced modulators and a harmonic oscillator.

In order to simplify the proposed device, the control inputs of the first balanced modulator are connected to the outputs k + 1 and n + 1 of the pseudo-random sequence generator register, and the control inputs of the second balanced modulator - with the outputs k-1 and p / register of the same generator. The voltages taken from the outputs of the register are inverse to each other.

The drawing shows a block diagram of the proposed device.

The device consists of multipliers / and 2, integrators 3 and 4, amplitude detectors 5 and 5, adder 7, balanced modulators 8 and I of generators 10, 11 and 12 of harmonic oscillations, pseudo-random sequence (PSP) and clock pulses with an adjustable follow frequency .

The principle of operation of the device is as follows.

Each balanced modulator from the SRP generator is supplied with voltages corresponding to both types of input signal "pauses -" packages. Thus, lagging voltages Ui and -f / 3 from bits to +1 and n + 1 are applied to the modulator 5 from the SRP generator register, and they are removed from the shoulders of the register triggers so as to be inverse to each other. Similarly, forward voltage Vz and -1/4 are applied to the modulator 9 from bits K – N H – 1. From the outputs of the channels, the voltage enters the adder 7, with the result that at its output a resultant adjustment characteristic is formed, similar to that obtained in a conventional four-channel synchronization scheme. The voltage from the output of the adder is applied to the controlled clock oscillator 12 and maintains the exemplary and incoming signals in the synchronization state. The equivalence on the resultant effect of the proposed synchronization scheme with a typical one can be easily shown when considering the voltage at the output of balanced modulators. Below are two tables that show the value of the voltage at the output of the modulator when voltage is applied to it from the SRP generator in various combinations.

The reduced matrices are equivalent to the following algorithm:

Uc (Vi + Us) U, (U2 + U,) 6out

On the other hand, this algorithm can be obtained from the basic for the well-known four-channel scheme by a simple transformation, by regrouping and combining members with the same sign. This allows us to conclude that the two synchronization schemes are equivalent to each other in the final effect.

Subject invention

A device for synchronizing non-coherent binary receivers, comprising

two synchronization channels, each of which consists of a multiplier, an integrator and an amplitude detector, a common adder for both channels, a pseudo-random sequence generator with a shift register, a clock generator, two balanced modulators and a harmonic oscillator, characterized in that, in order to simplify the device , the control inputs of the first balanced modulator are connected to the outputs to + 1 and n + 1 of the pseudo-random sequence generator register, and the control inputs of the second balanced modulator are connected The outputs with the k- / and p- / register of the pseudo-random sequence generator, the voltages taken from the outputs of the register, are inverse to each other.