SU577687A1 - Pulse signal regenerator - Google Patents

Description

(54) PULSE ALARM REGULATOR

The invention relates to a communication technique and can be used to reconstruct a bipolar digital signal attenuated in a linear path section of a communication system with pulse code modulation (PCM) in the form of J amplitude and temporal position.

A pulsed signal regenerator is known, which contains a correction amplifier and a series-connected clock extraction unit and a differentiation unit, the output of which is connected to the control inputs of the first and second decision units, the outputs of which are connected to the inputs of the bipolar pulse former 1.

However, the known regenerator has a low accuracy of regeneration of the pulse signal, which reduces the reliability of information transmission.

The aim of the invention is to improve the accuracy of the regeneration of the pulse signal.

For this purpose, five delay elements were inserted into the pulse signal regenerator, which contains a correction amplifier and series-connected clock extraction unit and a differentiation unit, E1YOUT of which is connected to the control inputs of the first and second decision blocks, the outputs of which are connected to the inputs of the bipolar pulse former, two multipliers, two keys and two prohibition elements, the outputs of which are connected to the information inputs of the corresponding decision blocks; while the outputs of the first (i second delay elements are connected to the corresponding inputs of the first multiplier, the output of which is connected to the information input of the first key, and its outputs are connected to the first inputs of the first and second prohibition elements, the second inputs of which are connected to the outputs of the second key, to the information input which is connected to the output of the second transceiver, the corresponding inputs of which are connected from the output to the third and fourth delay elements, and the output of the fifth delay element is connected to

input to the clock selection unit, the second output of which is connected to the control inputs of the keys, while the outputs of the correction amplifier are connected to the inputs of the corresponding delay elements.

FIG. 1 shows the structural electrical circuit of the proposed regenerator; in fig. 2 - voltage diagram at various points of the circuit.

The pulse signal regenerator contains a correction amplifier I and a taetine extraction unit 2 connected in series and a differentiation unit 3, the output of which is connected to the control inputs of the first and second decision blocks 4 and 5. The outputs of these blocks are connected to the inputs of the fi 6 bipolar pulses. The regenerator also contains five delay elements 7-11, two multipliers 12 and 13, two keys 14 and 15 and two prohibition elements 16 and 17, the outputs of which are connected to the information inputs of the corresponding decision blocks if, 5. At the same time, the outputs of the first and second elements delays 7, 8 are connected to the corresponding inputs of the first p "multiplier 12, the output of which is connected to the information input of the first key 14. The outputs of the last are connected to the first inputs of the first and second prohibition elements 16, 17, the second inputs of which are connected to the outputs of the second key 15 The information input of the second key 15 is connected to the output of the second multiplier 13, the corresponding, non-inputs of which are connected to the outputs of the third and fourth delay elements 9 10, and the output of the fifth delay element connected to the input of block 2, the second output of which is connected to the control inputs of keys C, 15, while the outputs of the correction amplifier I are connected to the inputs of the corresponding delay elements 7- II. The regenerator works as follows. The distorted pulse digital signal from the output of the correction amplifier 1 (see Fig. 2a), corresponding to the combination of +1, I, O, + 1, which must be restored by the regenerator, is fed to the inputs of delay elements 7-11 in the forward and inverted form , shift on their outlets by the value from O to T, where Te is the period of the clock frequency (see Fig. 26 - i). The signal processing starts at the moment when the leading edge of the pulse signal (duration T0) is at the end, and the falling edge - at the beginning of the delay elements 7-10, and continues for the duration of the read pulse TO, produced by the delay element 11 and block 2 ( see fig. 2k). With to TO, signal processing can be considered as occurring at a fixed time instant if, once per period To. With an appropriate choice of the weighting factors of the multipliers 12, 13, made in the form of resistance matrices, the signal is multiplied at discrete points on its copy. At the same time, at the output of the multiplier 12 there is a signal (see Fig. 2l), at the outputs of the key 14 at times to appear pulses of the corresponding polarity (see Fig. 2m, n). Further, in the absence of signals on the second inputs of the prohibition elements 16, 17, the pulses from the output of the key 14 enter the inputs of the decision blocks 4, 5 and are converted into a standard bipolar signal at the output of the driver with the help of test and reset signals (see Fig. 2 0-- y). Invention A pulse signal regenerator containing a correction amplifier and a series-connected clock extraction unit and a differentiation unit whose output is connected to control inputs of the first and second decision blocks, the outputs of which are connected to the inputs of a bipolar pulse former, characterized in that In order to improve the accuracy of the regeneration of the pulse signal, five delay elements, two multipliers, two keys and two prohibition elements are introduced, the outputs of which are connected to the information corresponding inputs of the corresponding decision blocks, while the outputs of the first and second delay elements are connected to the corresponding inputs of the first multiplier, the output of which is connected to the information input of the first key, the outputs of which are connected to the first inputs of the first and second prohibition elements, the second inputs of which are connected to the outputs of the second key , to the information input of which the output of the second multiplier is connected, the corresponding inputs of which are connected to the outputs of the third and fourth delay elements, and you the stroke of the fifth delay element is connected to the input of the clock selection unit, the second output of which is connected to the control inputs of the keys, while the outputs of the correction amplifier are connected to the inputs of the corresponding delay elements. Sources of information taken into account in the examination: 1. Levin, LS and others. Fundamentals of building digital transmission systems. M., “Holy, 1975, p. 17. 5g. 2