SU650077A1 - Microprogramme-control device - Google Patents

Description

BOM, lnoo in the second cycle of the machine, which ensures the flexibility of the firmware.

At the same time, there are algorithms, microoperations in which, by virtue of the axial symmetry of the tasks themselves, have symmetry in the sense that in one and the same machine cycles the same algorithms are performed in one algorithm and even micro-operations in another, and vice versa and as an example, one can cite geometrical interpretation algorithms for controlling two-coordinate objects, iaimer, graph-planning devices such as a coordinator, electron-beam installations and tubes, photo-diagonal installations; the tasks of topological designing of LSI photomasks, operations on matrices, trigonometric functions, etc.

In these cases, for each algorithm or its fragment, it is necessary to allocate its own memory array, while one algorithm can be simply converted to another by replacing even micro-operations with odd ones or vice versa. Failure to perform such transformations during the execution of the microprogram leads to an increase in hardware and complexity of the microprogram control device.

The purpose of the proposed firmware control device is to simplify the device. For this purpose, the symmetry attribute trigger, the element I, the inequality elements, the information register additionally contain a discharge of the symmetry attribute, and the output of the symmetry characteristic discharge of the information register is connected to the first input of the And element, the second input of which is connected to the third output of the clock generator. pulses, the output element And is connected to the counting input of the trigger sign of symmetry, the installation inputs in the "1 n" About which are connected respectively to the first and second inputs of the device va, the trigger output of the symmetry attribute is connected to the second input of each control element AND, the output of each control element AND is connected to the first input of the same inequality element, the second input of each unequality element is connected to the low-end output of the corresponding field of the information register, the output of each unequality element connected to the corresponding input of the opcode decoder of the same name.

The drawing shows a block diagram of the proposed device.

The device contains a generator of 1 clock pulses, an address element I 2, an address register 3, an address decoder 4, a microprogram memory block 5, an information register 6 divided into n fields 7

with control bit 8, bit 9 of symmetry attribute, decoder 10 operation code, output elements AND, element 12, trigger 13 of symmetry characteristic, control elements AND 14, unequalities 15, first input 16 of device, second input D / devices, group of outputs 18 devices.

When compiling microprograms, symmetric microoperations are encoded in such a way that their codes differ only in one, for example, low-order bit. Thus, even micro-operations are encoded with “zero in the lower order, and odd ones -. “Unit. In the control bits of the fields of the information register, for symmetric micro ops, the code "1" is written; for non-symmetric, "O." Finally, the code "1" is written into the bit of the symmetry feature 9 of the information register, when in the course of the microprogram execution it is required to make a transition from odd micro-irrations to even ones (or vice versa). Thus, each firmware

5 is compiled and implemented in block 5 of microprogram memory for one of two symmetric algorithms or their fragments. The proposed device works as follows.

0 Generator 1 generates four correct (non-intersecting) signal sequences, so that four consecutive signals / 1-7 from each series make one

5 cycle device. During the microtack TI, the address code from the information register 6 through the address elements And 2 is rewritten into the address register 3. During the microtakt Ha, the decoder is polled

0 addresses 4 and reading from block 5 of the microprogram memory of the corresponding word, which is entered into the information register 6. The codes from the output of the information register go to the corresponding decoder of operation code 10, the signals from which are transmitted to one of the inputs of the output elements 11. To the other inputs output elements And receive clocking signals GZ and T, with each of

These 0 signals combine valve groups of those fields whose microoperations are compatible and can be performed in one micro tact. The lowest bit of the code of each information field 7 is fed to the decoder 10 through the inequality element 15, to another input of which a signal is output from the control element I 14 that realizes the coincidence of unit levels at the outputs of the trigger 13 and the corresponding control bit 8.

Assuming that the trigger 13 by the signal on Bus 17 was set to the "zero state", then the "zero potential" is generated at the output of the control element I 14. In this case, the signal at the output of the inequality element 15 repeats the low-order value of the information field 7, i.e., all microoperations are performed as they are written in block 5 of the microprogram memory. Similarly, it occurs when the trigger 13 is in the "single state, and in the control bit 8, the code" O. Under the action of "unit levels at both inputs of control elements AND 14," unit potentials are also produced at their outputs. In this case, the codes of the lower bits of the information fields 7 are transmitted to the descriptors of the operation code by an inverse value, i.e., micro-operations that are symmetrical to the original are performed.

In the presence of a code. "1 in bit 9 of the symmetry feature during the micro tact with a TI signal from the output of the element 12 and fed to the counting input of the trigger 13, the latter switches to the opposite initial state and, therefore, the nature of the operations performed changes.

Introduction to the structure of the microprogramming device of new elements allows one of its main characteristics to be improved - to simplify the device, namely, to reduce the amount of lamps required for storing a specified number of microprograms. In the limiting case, when all the executed algorithms are symmetric, the memory volume reduction ratio is close to 2; the real values of this coefficient are in the interval between 1 and 2.

Claims (2)

Invention Formula jvlnKponporpaMMHoe control device containing a clock generator, an address register, an address decoder, an address element AND, a microprogram memory block, an information register divided into n fields, each of which contains a control bit, an AND control code, decoders of an operation code, n output elements, and, the bits of each bit of the information register, except the low bit, are connected to the corresponding inputs of the same name decryptor of the operation code, the output of each descrambler of the operation code n It is connected to the first input of the output element of the same name AND, the second input of each odd output element I is connected to the first output of the clock oscillator, the second output of which is connected to the second input of the even and even output cell I, the outputs of the output elements I are connected to the group of outputs of the device, the output control Each field of the information register is connected to the first input of a control element of the same name, And the third output of the clock generator is connected to the first input of an address element And, the second input of which is connected to the address output of the information register, the output of address element I is connected to the input of the address register, the output of which is connected to the input of the address decoder, the control input of which is connected to the fourth output of the clock generator, the output of the address decoder of the address is connected to the input of the metal microprogram memory, the output of which is connected to the input 11 of the information register, characterized in that simplify the device, the trigger of symmetry is entered into the device, the AND element, the inequality elements, the information register further contains the discharge of the symmetry attribute, the output of the discharge of the sign of the information register sphmetme is connected to the first input of the AND element, the second input is connected to the third output of the clock generator item output And connected to the counting input of the symmetry feature trigger, inputs ushaow in "1 and" and which are connected respectively to the first and second inputs ycipo.icTBa, the output of the symmetry feature trigger is connected to the second input of each equalizer element And, the output of the control element I is connected to the first input of the same-named inequality element, the second input of each element of the unequality is connected to the lower-order output of the corresponding field of the information register, the output of the cal-double element of the unequality is connected to the corresponding the main input of the code decoder of the operation code. Source information taken into account during the examination 1. USSR author's certificate No. 217724, cl. G 06 F 9/16, 1967. 2. USSR author's certificate 331387, cl. G 06 F 9/16, 1970.