SU720719A1 - Code to interval converter - Google Patents

Description

I

The invention relates to a pulse technique and can be used in automatic and computing equipment, in particular, in information output devices of computer systems.

A device for converting a code into a time interval is known which contains logic circuits, a counter, registers and an operator.

However, control is not provided in this device in order to prevent the passage of false information to the output of the converter.

It is also known a device comprising a serially connected counter, a circuit, adeny, a clock pulse generator, a comparison circuit connected by inputs to a storage register of convertible codes and to a counter, matching elements, the output of the first matching element whose control input is connected to the first output trigger control mode, is connected to the input of the storage register of convertible

codes and through the second match element - with the trigger input of indications, failures (indicator device), the first control mode trigger input is connected to the Beginning of the cycle circuit and through the delay element to the output of the third coincidence element, the control input of which is connected to the second Control mode trigger output , the second input of the latter: connected to the command circuit. Entering the code i, the output of the comparison circuit is connected to the input of the third coincidence element and via an inverter control input to the top of the coincidence element 2,

In this converter, despite the presence of a control circuit in it, do-. The accuracy of the output information is not sufficiently ensured, since the indicated scheme controls the transformations of the code already written to the register, but does not control the correctness of the input code and its writing to the register.

The aim of the invention is to maintain reliability.

The goal is achieved by the fact that a code converter in a time interval containing a serially stored code storage register, a counter, the first element H and an indicator, the output of the clock generator to the first input of the second element I connected to the second input of the counter, the output of the counter is connected to the first the input of the third element is And, and the second input of the second element And is connected with the second input of the indicator, the control mode activation block, the code verification block and the control signal generator generator are inserted waiting for the output of the second element and the second input of the first element, while the output of the code storage register is connected to the first input of the code storage register through the code verification unit and to the first input of the control mode activation unit, the second input of which is connected to the output of the first And element, the first the output of the control mode enablement unit is connected to the second input of the code storage register, the second and third outputs are respectively connected to the second inputs of the second and third elements, And,

Fig, 1 shows a functional diagram of the converter; in fig. 2 - time diagrams.

f. The converter contains the register of storage of the cop 1, the control mode activation block 2, the pulse counter 3, the code check block 4, the 5 clock pulse generator, And 6, 7 and 8 elements, output 9 buses, indicator 10, the check interval generator 11 and the input buses 12 and 13.

The converter works as follows

Please see below;

. The code to be converted from the bus 12 transmitted through block 2 is fed to the code storage register 1. From the control outputs of register 1, the recorded code is fed to the inputs of block 4 of the code check. In this specific implementation example, the code is checked for oddness.

If the converted code is correctly recorded in register 1, the code verification device 4 generates an Oddness signal that goes to the control input of the code storage register 1, allowing the rewriting of the recorded code into the 3-hour counter on the 2 mode unit

a control that issues a signal to the control inputs of the I6 element and the 1O indicator. In counter 3, to the input of which pulses are received from the generator of 5 clock pulses, a time interval is formed corresponding to the recorded code. From the output of the counter 3, the time interval through the element I7 comes in. And the output 9 of the converter. Element I8 is closed by a signal (zero level) from generator 11, and pulses from the output of counter 3 do not pass through the output of element I8 (Fig. 2a).

In the case of incorrect writing of the code in the code storage register 1, block 4 of the code check generates a signal Parity of which, received at the control input of register 1, prohibits rewriting of the recorded code into counter 3, and entering the control mode enable unit 2, proceeds converter to control mode.

Then the control mode enablement unit 2 breaks the chain of translation of the code being converted and issues a control code to the register, at its first input element I7 outputs a signal prohibiting the passage of information from counter 3 to output 9 of the converter, to the control inputs of element I6 and indicator 1O giving a signal enabling the passage of pulses from the generator 5 through the element I6 to the input of the generator 1 control interval and the passage to the indicator 10 of the signal element IV.

The check code is recorded in the code storage register 1. And the correctness of the record is checked by the code checker 4. In case of proper operation of retry 1, block 4 issues an Odd signal, I which allows overwriting of the control code in. Counter 3.

Counter 3 forms a time interval determined by the instant of the occurrence of a counter overflow pulse and corresponding to the control code. At the same time, the generator 11 generates a sequence of pulses, the repetition period of which is a control time interval, respectively. corresponding control code. The signals from the output of counter 3 and generator 11 are fed to the inputs of element I8, where they are compared in their temporary position.

Claims (2)

When the inverter is working successfully, these signals coincide (Fig. 26), the output of block I8 is a pulse that arrives at the 1O inpikator, causing the health of the signal to block 2, which turns off the control mode, and the converter goes into operation mode. If the test in the control mode shows the correct operation of the converter nodes, then the presence of the Parity signal was erroneously caused (in the code received from the bus, 12. If the control mode has a signal when the signal is Odd, the signals in the I8 circuit do not occur (Fig. 2c) the output pulse of this circuit is absent, the indicator 10 generates a signal Fault and the converter does not transfer to the operating mode. This indicates the malfunction of the counter 3. In the control mode, block 4 checks the code of the form Parity signal that you see There is a fault in the register 1 storing code, then the counter 3 forms a time interval that does not correspond to the control code and, therefore, on the I8 signal coincidence block I did not occur; details. Indicator device 10 generates a Fault signal. In block 2, turn on In the control mode, it is possible to force the control mode at the desired time. Claims of the Inverter Code Into {eemennoY interval containing serially connected code-storage register, counter, first element Both the indicator and the output of the clock generator and the first input of the second element I are connected to the second input of the counter, the output of the counter is connected to the first input of the third element I, and the second input of the second element I is connected to the second input of the indicator, characterized in that In order to increase reliability, a control mode enablement block, a code verification block and a control interval generator, which is connected between the output of the second element AND and the second input of the first element I, are entered into it, while the output of the register of the storage of the code A code verification block is connected to the first input of the code storage register and to the first input of the monitoring mode enable unit, the second input of which is connected to the output of the first AND element, the first output of the monitoring mode activation unit is connected to the second input of the code storage register, and the second and third outputs respectively, are connected to the second inputs of the second and third, elements I, Sources of information taken into account during the examination 1. Author's certificate of the USSR No 375777, cl. H 03 K 13/02, 04.10.71. I- .I 2. USSR author's certificate number 428551, cl. N OZ K 13/32 03.01.72. F (. Padcvtff / pe.iuf eleven. 8 / ШШ / / iiC / rhfJf / №Ht3ltJ / OfiW / Ar 5) Co6n adeffve sienolob 6) ffeco & fTcrde i e Cefeff Mo6 IT I U b sri / g 2