SU760077A1 - DEVICE FOR INFORMATION EXCHANGE I - Google Patents

Description

The invention relates to the field of computing technology and can be used in computers for exchanging information between RAM and external devices.

There are devices for exchanging information, intended for exchanging data between the RAM of a digital computer and external devices, containing an information register, an address register, a control word register, a device number register, a symbol register, a device number generator, an output register, and a request register [1].

The operation of these devices is controlled by the digital computer processor using indirect software control, whereby the information exchange process comprises three phases: exchange preparation, exchange itself, and exchange completion. The first and third phases are executed by software in the processor, while the second is performed by hardware in the exchange device.

When preparing for exchange with external devices, the processor generates control words, sends them to memory at fixed addresses and initiates the operation

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input-output, issuing the corresponding command to the exchange device. ' Direct exchange of information between the digital computer's storage device and external devices is carried out by the device itself

₅ exchange, which, for each request from these devices, reads control words from the digital computer’s storage device, analyzes them, modifies them and writes them back to the storage device, and transfers information from external devices to the storage device or vice versa.

The disadvantage of known devices is their low throughput, due to the need to use control words to control the volume of transmitted information, its ^addressing in memory and exchange modes, as a result of which in each session the exchange device repeatedly accesses the digital computer memory when reading and writing control words.

₂₀ The closest to the invention in terms of the essence of the technical solution is a device for exchanging information, containing an information register and an address register connected to a communication bus with storage

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minus device, exchange direction trigger connected by its input to the exchange direction bus, device number and switch number generators, information output register, request register connected to the communication bus with external devices, device number register, the input of which is connected to the output of the request register, and the output - to the inputs of the address register, device number and switch number generators. In addition, the device includes a control unit connected to the corresponding inputs and outputs of the word flag trigger, address register, exchange direction trigger, replacement flag generator block, control word registers connected by their inputs to the outputs of the information register and the symbol register connected to the input of the information register and to the outputs of external devices [2].

The disadvantage of this device is its low throughput.

The purpose of the invention is to increase the throughput of the device.

The stated objective is achieved by the fact that a write bus switch, a write address bus switch, an exchange direction switch, a requirement trigger, an OR element, and a priority node are introduced into a device containing an information register, an address register, an exchange direction trigger, the outputs of which are the corresponding communication outputs with the device memory, an output register, the input and output of which are respectively the first communication input with the device memory and the read output of the device, a requirement register, the inputs of which are the corresponding requirement inputs of the device, and a device number register connected by outputs to the corresponding inputs of the device number generator, the outputs of which are the corresponding address outputs of the device. In this case, the outputs of the demand register are connected to the input group of the priority node, the outputs of which are connected to the corresponding inputs of the device number register and the OR element connected by the output to the first input of the demand trigger, with the first groups of inputs of the write bus switch, the write address bus switch and the exchange direction switch, the second groups of inputs of which are, respectively, the write inputs of the device, the address inputs of the device and the exchange direction inputs of the device, and the outputs are connected, respectively, to the first inputs of the information register, the address register and the exchange direction trigger, the second inputs of which are connected to the second input of communication with the device memory, with the second input of the demand trigger, the output of the request register connected to the first input and the corresponding output of communication with the device memory,

with the first input of the priority node and the second input of the requirements register.

—The introduction of the specified nodes with the corresponding connections into a known exchange device allows for specialized

5 Information and control systems with a fixed volume of transmitted information for each external device, a fixed format for transmitted messages, and a fixed set of tasks performed by the digital computer eliminate the involvement of the digital computer processor in information exchange operations, assigning all information exchange functions directly to the exchange device. Addressing of transmitted information in the digital computer memory, control of external device selection, and the exchange mode are performed by the device itself, eliminating the need for control words.

For each of the external devices in the digital computer memory, a fixed 20 memory array is assigned and all information exchange is carried out by the exchange device outside the program, without the participation of the processor, through a common memory field in the digital computer storage device.

In each communication session with an external device ¹⁵ , the exchange device accesses the digital computer memory only once to read or write the information code.

The drawing shows a block diagram of the device.

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It contains a priority node 1, priority buses 2, write bus switch 3, write address bus switch 4, exchange direction switch 5, device number register 6, OR element 7, requirement trigger 8, device inputs and outputs 9, memory communication input and output groups, requirement register 10, output register 11, device number generator 12, exchange direction trigger 13, address register ₁₄ , information register 15, write inputs 16, address inputs 17, exchange direction inputs 18, requirement inputs 19, device address outputs 20, and read output 21.

- devices.

The device works as follows. 4$ External devices whenever

they are ready to receive or issue information, they send a request signal to the corresponding input 19 and simultaneously with it a signal of the exchange direction - to the corresponding inputs 18, the code of the number or feature of the requested parameter (the relative address of the parameter in the digital computer memory) - to the corresponding inputs 17 and, when entering into the digital computer, the entered information code - to the corresponding inputs 16. Signals with

55 inputs 19 are entered into register 10 and from the output of this register they are sent to the corresponding inputs of node 1. Node I priorities, analyzing the presence of requirements in

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register 10 and the selection of the highest priority one, generates a priority signal on the corresponding priority bus 2. The priority signal on bus 2, via the OR element 7, arms the requirement trigger 8, the signal from the output of which blocks the inputs of node 1 and register 10 and goes to the corresponding output 9. This same priority signal έ of bus 2, arriving at the input of register 6, enters into it the code of the number of the external device accepted for service.

At the same time, the priority signal on the corresponding priority bus 2 causes the entry of codes: from the corresponding inputs 16 through switch 3 into information register 15; from the corresponding inputs 17 through switch 4 into register 14; from the corresponding inputs 18 through switch 5 into trigger 13. The address code entered into register 14 is formed in switch 4 from the base address stored in switch 4 and the relative address received through the corresponding input 17 from the external device. Simultaneously with the signal of the exchange device request for service, received from the output of trigger 8, information from address register 14, exchange direction trigger 13 and from information register 15 is output to the corresponding inputs 9 - when information is entered.

Servicing of a request from the exchange device in the digital computer memory ends with the issuance of a reset signal at one of the inputs 9, which, arriving at the corresponding inputs of trigger 8, trigger 13, register 14, information register 15, and request register 10, resets them to their initial state. Simultaneously, using the same reset signal, device number generator 12, in accordance with the device number code arriving at its inputs from the output of device number register 6, generates a device number signal at one of its outputs, sending it to the corresponding output 20.

When information is output, the code read from memory is sent simultaneously to inputs 9, along with the reset signal. This code is then sent via output register 11 to read output 21, which is common to all receiving external devices. Information reception in the external device is strobed by the device number signal at the corresponding device number output 20.

The reset signal, by setting trigger 8 to its initial state, releases priority node 1 and register 10, after which the exchange device is released to service the next request from external devices for information exchange.

Thus, the exchange device performs parallel data exchange between the digital computer's memory and external devices in a time-sharing mode. For each external device request, the exchange device accesses the digital computer's memory only once—to write the input code or read the output code. The device's throughput increases and is limited only by the digital computer's memory access time.

Claims (1)

Claim A device for the exchange of information containing an information register, address register, trigger of the direction of exchange, whose outputs are the corresponding communication outputs with the device memory, the output register, whose input and output are the first communication input respectively with the device memory and the read output of the device , the register of requirements, the inputs of which are the corresponding inputs of the device requirements, and the register of the device number connected by the outputs with the corresponding inputs of the device number generator, out Which odes are the corresponding address outputs of the device, characterized in that, in order to increase the capacity of the device, a write bus switch, a write address bus switch, an exchange direction switch, a demand trigger, an OR element and a priority node are entered into it; to the group of inputs of the priority node, the outputs of which are connected to the corresponding inputs of the register of the device number and the OR element connected with the output to the first input of the requirements trigger, with the first commands of the write bus switch inputs, the write address bus switch and the exchange direction switch, the second groups of inputs of which are respectively device write inputs, device address inputs and device exchange direction inputs, and the outputs are connected to the first inputs of the information register, address register and exchange direction trigger respectively , the second inputs of which are connected to the second input of communication with the device's memory, with the second input of the requirements trigger, the output connected to the first input of the register ebovany and corresponding output communication with memory device ^ the first input of the priority node and the second input of the register of requirements. ’