SU809355A1 - Programmator for writing information into semiconductor storage elements - Google Patents

Description

The invention relates to computer technology, in particular, to information recording devices by burning jumpers in semiconductor memory elements used in permanent storage devices (ROM). Programmers are known for recording information into semiconductor memory elements 11J and 2. One of the known programmers contains a unit for generating a sequence of programming pulses of a certain amplitude and duration, which ensure that information is written into the memory element by alternately burning through the selected jumpers ll. In order to ensure that any jumpers are burned through, regardless of the technological variation of their characteristics, the programmers provide a sufficiently long pulse duration that is much longer than the average value of the actual jump jump time. The duration of the pause between pulses for reliable cooling of the memory element is usually set several times longer than the duration of the pulse. As a result, the total programming time of the memory element is excessively large, and for large-capacity memory elements (one kilobits per bit), it can be one or ten minutes. This is a serious disadvantage of the programmers when they are used in the mass production of equipment. The closest technical solution to the present invention is a software controller containing a PS1 unit, the first input of which is connected to the data input bus, the second input is connected to the output of the address counter and to the first output bus, and the third input to the first output of the monitoring and control unit, The second output of which is connected to the input of the common counter, the third output - with the first input of the data I / O unit, the second input of which is connected to the output of the memory block, the first input of the data input / output unit is connected to the first input of the control unit, and the second - to a second output bus, the third bus vshodnuyu 2 In a programmer programming pulses and pauses between them are fixed duration set by taking into account possible technological spread fusible jumpers memory cell characteristics. However, the actual burning time of most jumpers is one to two orders of magnitude shorter than the pulse duration. Since programming is performed sequentially, one jumper in one cycle, the total time of writing the program to the memory element is much longer than is really necessary (e, because the programmer's performance is not high enough.

The purpose of the invention is to increase the speed of the programmer.

To achieve this goal, the programmer contains a current sensor and an automatic cycle time varying block. At the same time, one output of the current sensor is connected to the third output bus and to the first input of the automatic change cycle block, the second input of which is connected to another output of the current sensor and the fourth output of the block. monitoring and control, the second and third inputs of which are respectively connected to the first and second outputs of the block automatically change the duration of the recording cycle.

At that, the block for automatically changing the recording cycle duration contains the pulse width generator connected in series, the inputs of which are connected respectively to the first 1 and second inputs of the block, the pulse width meter and the shaper of the pause duration, the second input of which is connected to the first output of the pulse width imager, the second output of which The first code of the generator of the pause duration is connected respectively to the first and second outputs of the block, and the second output of the generator of the length elnosti pause connected to the second input of the meter pulse.

FIG. 1 shows a programmer, a block diagram, FIG. 2 - block: block diagram of the automatic change of the duration of the recording cycle.

The programmer contains a block of 1 memory, a data input bus 2, a block of 3 .in a-output data, a connector 4 for connecting the programmer output buses, an address counter 5, a monitoring and control unit 6, respectively, first, second and third output buses 7, 8 9, the automatic change time unit 10, the write cycle duration, the pulse width shaper 11, the first and second output buses 12, 13 of the automatic change time unit 10, the pulse duration meter 14, the pulse duration 14, the shaper 15 pause time, current sensor 16, amplifier 17,

direct output 18 of the amplifier, inverse output 19 of the amplifier, first element I 20, second element I 21, oscillator 22 clock pulses, reversible counter 23, input 24 direct counting reversible counter 23, third element I 25, frequency divider 26, input 27 reverse counting the reversible counter 23, the decoder 28 of the zero state of the reverse counter 23, the inverse output 29 of the decoder.

The programmer works as follows.

Claims (2)

A memory element to be programmed is plugged into slot 4. At the command of the monitoring and control unit 6, the memory unit 1 is loaded onto bus 2 with a program (ROM codes) from some external device (reader from punched tape, etc.) or manually. With the help of the commands of the monitoring and control unit, the address counter 5 is reset, and the corresponding addresses of the memory unit 1 are selected. The data code from the set address of memory block 1 is transmitted to data input / output unit 3 and is fed to the corresponding inputs of connector 4. In an arbitrary state of the reversible counter 23 at the time of activation (the contents of the counter is not equal to O), the inverse output 29 of the decoder 28 has a signal logical 1, which opens the third element And 25, since the inverted output 19 of the amplifier 17 connected to the second input of the third element And 25 also has a signal of logical 1 (there is no signal at the input of the amplifier 17), as a result At the current counter of the reversing counter 23, the third element 25 and the frequency divider 26 begin to receive pulses from the generator 22 clock pulses with a frequency reduced by K times, where K is the division factor of the frequency divider 26. With each pulse, the number contained in the reversible counter 23 decreases by 1 until the reversible counter 23 clears and its contents become equal to 0. At this point, the logic levels at the outputs of the decoder 28 are reversed, resulting in the third element And 25 being locked , and on the second output bus 13, a Start signal appears, which enters the monitoring and control unit 6. On this signal, the monitoring and control unit 6 generates all the signals necessary for providing the programming mode of the memory element and arriving at connector 4, including the programming pulse on the third output bus 9. The programming current of the selected jumper starts to flow through bus 9 and current sensor 16 . The signal on the current sensor 16 triggers the amplifier 17, as a result, the second element 21 is unlocked, and pulses from the clock generator 22 begin to arrive at the input 24 of the forward counting of the reversible counter 23. The counting process of the forward counting 23 continues until 16 current is flowing programming current. When the switch is selected to be destroyed, the current in the bus 9 is stopped, the voltage drop across the current sensor 16 drops to O, and the amplifier 17 returns to its original state. In this case, the signal of the logical 1 from the inverse output 19 of the amplifier 17 arrives at the input of the circuit of the first element And 20. The signal of the logical 1 from the output of the current sensor 16 connected to the monitoring and control unit 6 is received at the other input of the first element 20, since the voltage the programming pulse continues to operate, despite the current cessation in the bus 9. As a result, the first element I 20 is unlocked and a stop signal appears on the first output bus 12 arriving at the control and monitoring unit 6. On this signal, the control and management unit 6 interrupts the programming mode of the selected jumper, removing control signals from the inputs of connector 4, including the voltage from the bus 9 of programming pulses. Thus, the termination of the program pulse and the transition to the pause is carried out immediately after the destruction of the selected jumper. In this case, the pulse duration has a random value determined by the characteristics of a particular jumper. At the moment of turning off the amplifier 17, the second element I 21 is locked, and the operation of the reversible counter 23 is canceled. In this case, it records a number proportional to the duration of the terminated pulse, i.e. The value of the duration of the programming pulse is stored in the digital code. The termination of the pulse and the setting of the amplifier 17 to the initial (zero) state results in unlocking the third element AND 25, since the contents of the reversible counter, 23 is not zero, and on the inverse output 29 of the decoder 28 there is a signal of logical 1. At the input 27, the counting of the reversible counter 23 begins to receive pulses from the clock generator 22 through the frequency divider 26. Since the frequency of these pulses is K times lower than the generator frequency of 22 clock pulses, the time required to clean the reversible counter 23 is K times longer than the time it took to fill it (i.e. the pulse duration). When reaching the zero state of the reversible counter 23, the output signals of the decoder 28 are inverted, as a result of which the third element I 25 is locked, and a Start signal arriving in block 6 of controls and controls appears on the second output bus 13. At this pause ends, and then the process is repeated with a different state of the address counter 5, set by the command of the control unit 6. l and control during the pause. As can be seen, the duration of the pause is K times the duration of the previous pulse, which ensures a constant value of the duty cycle of the programming pulses, i.e. unchanged value of the average power dissipated in the memory element of the ROM in the programming mode. This ensures the normal temperature mode of the ROM memory element in the process of recording information. The magnitude of the duty cycle, equal to (K + 1), can be changed in accordance with the requirements of the technical conditions for various types of elements of the PSM ROM and by changing the division factor K of the frequency divider 26. The use of the invention allows to significantly reduce the total programming time of the ROM and thereby improve the performance of the programmer. Thus, for example, when programming memory elements of the K556PE 4 ROM, the performance is increased by a factor of 2 compared to the known programmers. This makes it possible to significantly reduce the quantitative need for programmers and the number of service personnel. Claim 1. A programmer for recording information into semiconductor memory elements containing a memory block, the first input of which is connected to the data input bus, the second input is connected to the output of the address counter and to the first input bus, and the third input to the first output of the block monitoring and control, the second output of which is connected to the input of the address counter, the third output is connected to the first input of the data I / O unit, the second input of which is connected to the output of the PS1m ti unit, the first output of the data input / output unit is connected to the first the control and control unit, and the second to the second output bus, the third output bus, characterized in that, in order to improve the performance of the programmer, it contains a current sensor and a unit for automatically changing the recording cycle duration, with one output of the current sensor connected to the third the output bus and to the first input of the unit of automatic variation of the duration of the write cycle, to the second input of which another output of the current sensor and the fourth output of the monitoring and control unit are connected, the second and third inputs of which correspond It is connected to the first and second outputs of the automatic change cycle block. 2. A programmer according to claim 1, characterized in that the unit for automatically changing the duration of a recording cycle comprises successively connected pulse width drivers, the inputs of which are connected respectively to the first and second input inputs of the block, pulse width meter and driver pause duration, the second input of which is connected to the first output of the pulse width generator, the second output of which and the first output of the gap duration generator are connected to the first and second outputs of the block, respectively, and the second output of the gap duration generator is connected to the second pulse width meter input. Sources of information taken into account in the examination 1. A collection of abstracts of reports of the All-Union Scientific and Technical Conference of the Computer-76, h, 1, M., 1976. 2. For the FRG 2546713, cl. G 06 F 9/00, 1975 (prototype).  yyyy-i ::: - r-zzz-T f: - п Л t gi 29 f