SU970480A1 - Self-checking memory device - Google Patents

Description

output decoder, main word register, error correction block, control block, additional drive, address inputs and bit inputs and outputs of which are connected respectively to the outputs of the additional address block and to the output and | inputs of the additional bit block, with one of the outputs of the first decoder they are connected to the inputs of the main address block, and another output is connected to the inputs of the additional address block and the address input of the error correction block, the control input and output of which are connected to the first the outputs and inputs of the control unit, and the information input and output - with the outputs and inputs of the main bit block and one of the information outputs and inputs of the base word register, the other information inputs and outputs of which are the inputs and outputs of the device; world of test signals, additional word register, encoder, second. decoder and address register, the outputs of which are connected to the inputs of the first decoder and the address inputs of the associative drive, controlling output D which is connected to the second input of the control unit, and the information inputs and outputs are connected respectively to the outputs of the encoder with the inputs of the decoder, the output of which is connected to the first control input of the main register of the word, the second control input of which is connected the input of the register of the address, one of the outputs of which is connected to one of the inputs of the addressing signal generator, the other input and output of which are connected to the third output and the input of the control unit the fourth output Which is connected to the control input of the additional word register, one of the inputs and outputs of which are connected to the outputs and inputs of the additional bit block, the other input and output of the additional word register are connected respectively to the first input of the comparison circuit and the outputs of the main bit block and the main block inputs, the second input of the comparison circuit and the outputs of the test pattern driver, whose input is connected to the fifth output of the control unit, the sixth output of which is connected to the third the comparison circuit, the output of which is connected to the input of the encoder. FIG. 1 shows the proposed device, a structural scheme; on . Figures 2 and 3 are functional diagrams of the control unit and the address signal generator, respectively. The device (FIG. 1) contains an address registry 1, a first decoder 2, a main address block 3, a main redundant block 4, a main accumulator 5, an additional address block b, an additional bit block 7, an additional drive 8, a main 9 and an additional 10 fishing registers, error correction block 11, test signal driver 12, comparison circuit 13, address signal driver 14, control block 15, encoder 16, associative drive 17, second decoder 18. In Figure 1, address inputs 19 and information inputs and outputs are marked 20. Block control The event contains (Fig., 2) a generator 21 of rectangular signals, the first 22, second 23 and third 24 elements And, counter 25, third decoder 26 and element NOT 27. In figures 1 and 2 also the first 28, second 29 and the third 30 inputs of the control unit; the first 31, second 32, third 33, fourth 34, fifth 35 and sixth 36. outputs of the control unit. The address signal generator (Fig. 3) contains an n-bit binary counter 37, a parity check unit 38 and a switch 39. The counting and control inputs of the counter 37, the control inputs of the block 38 and the switch 39 are inputs. shaper. The counter overflow output 40 is one of the driver outputs, and the bit counter outputs, besides zero, and the switch output are the other driver outputs 41. The device works as follows. The main accumulator 5, with the number of failures, which are eliminated by the use of block 11, operates with error correction by means of correction codes. At a certain point in time, the situation occurs when the POWER of the correction code of block 11 is insufficient for normal operation of the main accumulator 5. At the same time, block 11 outputs a single signal to the input 28 of the control block 15. In parallel with the sampling of information from accumulator 5 and operation of block 11, an associative search is performed at register 1 address in associative accumulator 17. With this address in accumulator 17, a single signal is generated at its control output, which at input 29 of block 15 (Fig. and 2) prohibits the latter from entering the test control mode, and an error code is generated at the information output of the accumulator 17, which is decoded by the decoder 18 and fed to the register 10 to correct the information in this register. If there is an address in the accumulator 17, a single signal is formed at its control output, which by: input 29 of block 15 (Figures 1 and 2) prohibits, (the latter goes into the test control mode / and on the information output of the accumulator 17. This time, an error code is generated, which is deciphered by decoder 18 (Fig. 1) and fed into register 10. To correct the information in it.In the absence of a register address 1 in a hardener 17, a zero signal is given to the first output on the first output, which allows the block to go 15 test control mode. By a signal from block 1 1 at input 28 of block 15, the latter generates a zero signal at its output 25 (FIGS. 1 and 2), which block register 1 and register 10. Then block 15 connects the output of accumulator 5 to the inputs of register 9 with a signal at output 34 and delivers an enable signal on at the exit 33 to the shaper 14, the signals at the outputs 41 (FIG. 3) of which determine the address of the main accumulator cell; body 5, in which an error was detected, while the higher bits of the decoder 2 determine the address of the Crystal of the accumulator 5, in which this cell The shaper 14 generates a plurality of cell addresses that are in the faulty crystal at the power point 5, and for each of them the information is copied from the faulty crystal drive 5 to the additional memory 8. At the output signal. Yes 40 driver 14, which is fed to input 30, unit 15 is transferred to a test control mode, in which unit 15 together with driver 14 former 12, comparison circuit 13, encoder 16 and associative drive 17 provides test control of the faulty power chip 5. At the first stage - test control; (table) shaper 14 forms the even codes of the address set A1 (00 ... 00, 00 .- .. 11, 11 ... 11). In this case, the shaper 12 forms the zero test word (0 ... 0), which is written into the cells of the accumulator 5 belonging to the set A1. At the end of the first control stage (the appearance of a single signal at the output 40 of the generator 14, the block 15 proceeds to the second stage of the test control. At that, the block 15 at the output 33 outputs a signal to the input of the forKI1144, as a result of which the last one goes into the formation of odd codes A2 sets (table) of addresses (00 ... 01, 00 ... 10, .. 111..10). Shaper 12 thus generates a single test word (11. .. 11), which is written into cells belonging to the set A2 After the appearance of the signal at input 30 of block 15, it proceeds to the third stage, which A controller in which shaper 14 generates a plurality of addresses A1, shaper 12 forms a zero test word which goes to the second input of the comparison circuit 13 |, and information from accumulator 5 is fed to its first input. On the third input to the comparison circuit 13 This brings the comparison resolution resolution from block 15. At the output of the comparison circuit 13, the result of monitoring the faulty crystal of accumulator 5 is formed in the form of the error vector. If the codes of words on the first and second inputs of the comparison circuit 13 do not match, the error vector is fed to the input of the encoder 16, which generates the error code for the given cell and records it in the functional part of the associative accumulator 17. At the same time, the address code of the defective cell with Rchod register 1. The purpose and operation of the encoder 16, consider the following example. Let us assume that block 11 corrects one error in the word from the n bits of accumulator 5. The task is to double the power of the correction code, i.e. correct two errors. Therefore, the error vector in this case will contain C combinations of various code combinations. In order to reduce the associative accumulator 17 size, the encoder 16 encodes xadbination C, with a code of log log Su, which is significantly less than n, and accordingly reduces the hardware cost of the associative accumulator 17. After the appearance of a single signal at output 40 of the former 14, unit 15 proceeds to the fourth a control stage in which the driver 14 generates a plurality of A2 addresses, and the driver 12 is a single WORD and the control operations are performed, similar to the third stage of the control. In total, eight such steps are carried out in the monitoring process. The table shows the types and sequence of these stages. After the end of the eighth stage, the signal at the output of the shaper 14, block 15 organizes the overwriting of information from the accumulator 8 to the main accumulator 5 according to address 1M, formed by the shaper 14. Then the block 15 by the output signal, 2 organizes the repeated call to the auxiliary 5 at the address set by , WMD on register 1, and associative

Search in drive 17. When an address code corresponding to the address code of register 1 is detected, an error code appears at drive information 17 on drive 17, KOTopfctfi is decrypted by daiframer 18 and sent to register 10, i.e. the values of the defective bits of the word are corrected and the correct value of the information is output to the output 20 of the device.

The technical and economic advantage of the proposed device is that it allows without using an external digital computer to increase the power of the correction code, providing control and correction of information without reducing the information capacity, thereby increasing its reliability and information capacity compared to the prototype.

A1

Zero

A2 Single L2

t / Al Zero Al

Unit A2

A2

Unit D1

A1

A2 Zero

Single al

Al

Claims (2)

A 2 Zero Claim Formula A memory device with a troll containing a main drive, address inputs and bit inputs and outputs of which are connected respectively to the outputs of the Main address block and to the outputs and inputs of the main bit block, first decoder, main word register, block error correction, control unit, additional drive, address inputs and bit inputs and outputs of which are connected respectively to the outputs of the additional address block and to the outputs and inputs of the additional bit unit, with one of the outputs of the first decoder connected to the inputs of the main address block, and the other output is connected to the inputs of the additional address block and the address input of the correction block Write by Al Write by A2 Read by Al Read by A2 Record by Al A2 Recording Al reading Reading the A2 days of errors, the control of the input and output of which is connected to the first output and input of the control unit, and the information input and output are connected to the outputs and inputs of the main bit block and one of the information outputs and inputs of the main register of the word, other information inputs and the outputs of which are the inputs and outputs of the device, characterized in that, in order to increase the reliability and increase the information capacity of the device, an associative drive, an address signal generator, the circuit The test signal driver, the additional word register, the encoder, the second decoder, and the spread register, the outputs of which are connected to the inputs of the first decoder and address inputs of the drive associative, the output of which is connected to the second input of the control unit, and the information inputs and outputs are connected respectively with the outputs of the encoder and with the inputs of the decoder, the output of which is connected to the first control input of the main register of the word, the second control input of which is connected to the second output of the block Control and control to the digital input of the address register, one of the outputs of which is connected to one of the inputs of the address signal generator, the other input and output of which are connected to the third output and input of the control unit, the fourth output of which is connected to the control input of the additional register of the word , one of the inputs and outputs of which are connected to the outputs and inputs of the additional bit block, the other input and output of the additional register of the word are connected respectively to the first input of the comparison circuit and the outputs novnogo discharge unit and to the inputs of the main discharge unit, the second input of the comparison circuit and the output of the test signal, the input of which is connected to a fifth output of the control unit 7, the sixth output which is connected to the third input skhevl comparison, the output of which is connected to the input of the encoder. Sources of information taken into account in the examination 1. US Patent 3562709, cl. 340-146.1, publ. 1968. 2. USSR author's certificate I 618799, cl. G 11 C 29/00, 1978 (prototype).