TH22723A - "The link processor transmits in a series of streams that are the ideal field structure for conveying television information" - Google Patents

Abstract

High definition television signals are sent. Will be in the form of a series of data streams It is an ordered series of data fields (Fig. 1) with an irregular data rate. Due to different types of information, the headers did not have information. Each field is preceded by The sync field header is followed by 312 coordinated data segments, each containing its information header (FEC) on the receiver (Fig. 4). The sending processor (14) generates the dataset that Has a header in it And will work without interruption with a constant data rate While supplying the packaged data stream to a circuit network (17), which generates a series of data fields by inserting no data header data into that stream. The processor will perform well at a consistent data rate. Without having to modify the original data field structure To meet the circuit requirements, construct a data field structure. The result is achieved by transmitting data from the processor to a buffer / link circuit (46) that responds to the symbolic clock signal (SC) 3/8 in conjunction with the buffer full level. As defined The sending processor / decoder (86) involved in the receiver (Fig. 17) will work with the data field processor (75) and will perform the same uninterrupted operation with a constant data rate.

Claims (3)

1.A system for processing a series of digital data streams containing image data to generate an output stream representing a sequence of data fields, each containing M segments made up of (a) sections. N data segments where each section includes an informational range. And (b) a header field with different header ranges prefixed to the segment where M and N are integers and M are greater than N. Responds to the system clock (SC) and will consist of The processor sends (14) that responds to the input data to produce a set of lengthy data sets. A linker circuit (16) to receive the output data from the said sending processor. The circuit creates a data field structure (17) that operates at an irregular data rate. And responds to data from the aforementioned coupler circuit to generate the said output stream representing the sequence set of the said field. The above output stream will display the data range. And the header interval with different intervals and the output processor (18), where the processor sends it provides a series of output data to such linker circuits at a constant, constant data rate and a structuring circuit. The field will operate at such inconsistent data rates without interrupting the stream. 2. System according to claim 1, where the coupler circuit includes buffer (46) for Transmits information from the processor to the structure of the field. The transmitting processor passes the data to the buffer at a constant data rate and The buffer passes the data to the field construct circuit at an irregular data rate. 3. System according to claim 1, where the field constructor circuit retrieves data from the linker circuit. At an irregular data rate, and the coupling circuit retrieves data from the sending processor at a constant data rate, 4. System according to claim 2, where the circuit generates such data field structures in response to the signal. The clock of the said system The sending processor operates in response to a clock signal that is multiples of the SC 3/8 integer SC is the system clock, and the buffer is written in the form of data in response to the multiples. Which is an even number of the aforementioned SC 3/8 clock signal 5. System according to claim 2, where the buffer size is significantly less than the field of data and the integer is an even number 6. System in accordance with Clause 1 where such input data will be MPEG compliant data, such section header period will be included with tolerance-adjusted information. FEC section of the field. The headers contain sync field information, and the range contains 188 bytes. 7. System according to claim 1, where the data output from the aforementioned sending processor is in binary data. The clock signal of the SC system will be the symbol clock signal 8. The system according to claim 1 and also consists of A recording / playback device (15) is held in a path through which a constant data rate flows between the sending processors. 9. A system for processing digital data streams containing image data to produce an output stream representing a sequence of data fields, each containing a number of dimensions each. The section will include an informational range. And the header range And the header field with different header ranges in front of them. Which will consist of The processor sends (14) that responds to the input to form a set of data at a specified length. A linker circuit (16) to receive the output data provided by the sending processor. The circuit creates a data field structure (17) operating with irregular data rates. And responds to the data from the coupler circuit to generate an output stream representing the sequence of such data fields. The above output stream will display a range of data. And the header interval with different intervals and the output processor (18) where the processor sends it through a series of output data to the aforementioned link circuit at a constant data rate by Responds to the clock signal which is the TV integer multiplied of SC 3/8, where SC is the system clock signal 1 0. System according to claim 9, where each segment of the said segment includes its payload. Component D is an integer. The output processor includes an 8-VSB modulator. The information is transmitted in response to the SC 3/8 clock and the data range and between the data transmitted from the processor. D and E are integers, D is greater than E 1. 1. System according to claim 10, where D is 188 and E is 125. 1 2. System according to Clause 9, where each such segment segment includes its component D is an integer. The output processor includes an 8-VSB modulator. The information is transmitted in response to an SC 3/4 clock and a range of data. And between the data transmitted from the sending processor corresponds to the ranges D and E respectively of the said SC 3/4 clock signal, where D and E are integers, where D is less than E. 1 3. Clause 12 system where D is 188 and E is 438 1 4. Clause 9 system where each segment of the said segment includes its segment D is a number. integer The output processor includes a 16-VSB modulator. The information is transmitted in response to an SC 3/4 clock and a range of data. And between the data transmitted from the sending processor corresponds to the said SC 3/4 clock range, respectively, where D and E are integers, D is less than E 1 5. System Clause 14, where D is 188 and E is 125 1. 6. System in accordance with claim 9 and also includes recording / playback equipment (15) that are arranged in the path of the available data stream. A consistent data rate between the processors. 1 7. A connected and modulated digital data stream receiver system with visual signal information representing a sequence of data fields, each containing an M component. Based on (a) N data sections, each of which includes a range of data. And (b) the header field segment with the different header ranges that precede it, where M and N are integers and M are greater than N, which the system responds to. System clock signal (SC) and will consist of Input processor (72) to provide a demodulated stream that represents a sequence of data fields. And show irregular data rates A data field processor (75) to extract header information from the aforementioned demodulated stream to obtain such an irregular data-rate stream. Link circuit (84) to receive output data from the said field processor and transmit decoder (86) to decode the received data set from the linker circuit to produce the output. It is where the transmit decoder receives the data set from the coupler circuit at a constant, constant data rate, and the data field processor operates at that irregular data rate without interrupting the stream. 1 8. Systems according to claim 17, where the coupling circuit includes a buffer for the transmission of information from the said field processor to the transducer. The field processor passes the data to the buffer at an irregular data rate, and it passes the data to the decoder at a constant data rate. 9. System according to the claim. Article 18, where such data field processors will respond to the clock signal of such systems. The transmit decoder responds to the clock signal which is the multiples of SC 3/8 integer, which SC is the system clock, and the buffer reads the data in response to the multiples of the clock signal. SC 3/8 as mentioned 2 0. System according to claim 18, where the size of the buffer is significantly less than the data field. And such integers will be an even integer number 2. 1. System according to Clause 17 where such output data will be MPEG-compliant data. The header period of that section will be included. The FEC section of the header field contains the sync field information and 2. 2. System according to Clause 17, where such output data from the decoder sends. It is in the form of byte data and the clock signal of the SC system is the symbol clock signal 2. 3. System according to Clause 17 and also the recording / playback equipment (85) that is It is held in a path of a stream with a constant data rate between such linker circuits. 2 4. In a receiver for processing a series of digital streams that are modulated with video signal information that represents a sequence of data fields, each containing an M component. Based on (a) N data sections, each of which includes a range of data. And (b) the portion of the header field with different header ranges that precede it, where M and N are integers and M are greater than N, the data processing method consists of steps. Section of (a) demodulation (72) such stream to produce a demodulated stream with inconsistent data rates (b) extracting (75) header information from The stream is modulated without interrupting it. To produce an irregular data stream (c) decoding (86) the data from that stream generated in steps (b) at a constant, constant data rate and (d) conveying (84). ) Data from process (b) to process (c) at a constant, constant data rate 2. 5. A modulated digital stream processing receiver system with visual signal information displayed. Reaches a sequence of data fields, each containing a number of data fields, each of which includes a data range. And the header range And the header field sections with the different header ranges that precede them. Which will consist of An input processor (72) for providing a demodulated stream that represents the sequence of such data fields. And will show irregular data rates A data field processor (75) to extract the header information from the modulated stream to create an irregular data-rate stream. Link circuit (84) to receive output data from the said field processor and transmit decoder (86) to decode the received data set from the linker circuit to produce the output data where the The transmitted decoder rushes a series of data from the aforementioned link circuit at a constant data rate in response to the clock signal which is the multiples of the SC 3/8 integer, where SC is the system clock signal 2 6. In accordance with Clause 25, where each such segment range includes its payload, component D is an integer. The input processor includes an 8-VSB decoder. The transmit decoder receives a series of data from the coupler circuit in response to an SC 3/8 clock signal and range. information And no data of the stream received by the decoder from the linker circuit corresponds to the aforementioned SC 3/8 clock range, where D and E are integers, which D will have. A greater than E 2 7. Claim 26 system, where D is 188 and F is 125 2. 8. Claim 25 system, where each such portion segment includes the constituent payload. D will be an integer The output processor includes an 8-VSB decoder modulator. The transmit decoder receives the dataset from the coupling circuit in response to an SC 3/4 clock and range. information And no data of the stream received by the decoder sent from the link circuit corresponds to the aforementioned SC 3/4 clock channel, where D and E are integers, where D is smaller. Than E 2 9. Claim 28 system where D is 188 and F is 438 3. 0. Claim 25 payload system, where each such portion of the segment includes the part D. Will be an integer number The output processor includes a 16-VSB decoder modulator. The transmit decoder receives the dataset from the coupler circuit in response to an SC 3/4 clock and range. The data and no data of the stream received by the decoder transmitted by the coupler circuit correspond to the aforementioned SC 3/4 clock channels, where D and E are integers, which D have values. Less than E 3 1. System according to Clause 30, where D is 188 and F is 125 3 2. System according to claim 25 and also includes recording / playback devices (85) that are arranged in a path of a constant data-rate stream between such link circuits. And the aforementioned transmission decoder 3 3. In a receiver for processing a modulated digital stream containing visual signal information representing a sequence of data fields. Each is comprised of a number of data fields, each of which contains a data range. And the header range And the header field with the different header ranges that precede them. The data processing method consists of steps of (a) demodulation (72) such stream to produce a demodulated stream with inconsistent data rates (b) extraction ( 75) The header information leaves such a demodulated stream without interrupting it to create an intermittent data stream (c) decoding (86) data from that stream. Such data generated in (b) and (d) procedures (84) transfer data from process (b) to procedure (c) at a constant, consistent data rate. It responds to the clock signal which is the multiples of SC 3/8 integer, which SC is the system clock.