TH22723A - The processor linker transmits a set of data streams in a field structure suitable for conveying television information. - Google Patents

Abstract

The high-definition television signal being transmitted is in the form of a segmented stream of data fields (Figure 1) with an uneven data rate due to different timing patterns of the omitted header information. Each data field is served by a sync field header followed by 312 segmented fields, each with its own header information (FEC) at the receiver (Figure 4). The transmit processor (14) creates the segmented stream with the header and operates uninterrupted at a constant data rate while feeding the segmented stream to the network circuit (17), which creates the segmented field by inserting the omitted header information into the stream. Such a transmit processor operates at a constant data rate without needing to adjust the original field structure to meet the requirements of the field constructor circuit. This is achieved by passing the data from the processor to a buffer/link circuit (46) that responds to a 3/8 symbol clock (SC) with a specified buffer full level. The transmit/decoder processor (86) directly connected to the receiver (Figure 17) will work in conjunction with the field processor (75) and will perform the same uninterrupted operation with a constant, steady data rate.

Claims (33)

1. A system for processing a sequence of digital data containing visual information to produce an output stream representing a sequence of data fields, each consisting of M segments composed of (a) N data segments, each containing a data range and a header range, and (b) a header field with different header ranges preceding the data segments, where M and N are integers and M is greater than N. The system responds to the system clock signal (SC) and consists of a transmit processor (14) that responds to input data to produce a sequence of data fields of a specified length; a link circuit (16) to receive output data from the transmit processor; and a field constructor circuit (17) that operates at an uneven data rate and responds to data from the link circuit to produce the output stream representing the sequence of data fields. The output stream represents the data ranges. and the header section with different time intervals and the output processor (18) where the processor sends such a set of output data to such a link circuit at a constant constant data rate and such a field constructor circuit operates at such an inconsistent data rate without interrupting such data streams. 2. A system under claim 1 in which such link circuit shall include a buffer (46) for passing data from the processor to such field constructor circuit. Such processor passes data to such buffer at a constant constant data rate and such buffer passes data to such field constructor circuit at an irregular data rate. 3. A system under claim 1 where the data field constructor circuit retrieves data from the link circuit at a non-uniform data rate, and the link circuit retrieves data from the sender processor at a constant, uniform data rate. 4. The system under claim 2, whereby the data field structure circuit responds to the system clock signal; the processor sends data in response to a clock signal that is an integer multiple of the SC 3/8 clock signal, where SC is the system clock signal; and the buffer writes data in response to an even multiple of the SC 3/8 clock signal. 5. A system under claim 2 where the buffer size is significantly smaller than the data field and the integer is an even number. 6. The system under Claim 1 shall have input data that is compatible with the MPEG standard, the header segment shall include FEC error-corrected information, the field header segment shall contain synchronized field information, and the data segment shall contain 188 bytes of data. 7. A system under claim 1 where the output data from the processor is in the form of bytes and the system clock signal of the SC is a symbolic clock signal. 8. The system under claim 1 also includes a video recording/playback device (15) which is set up in the path of the data stream with a constant data rate between the said transmitting processor and the said link circuit. 9. A system for processing a digital stream of visual information to produce an output stream representing a sequence of data fields, each containing a number of data segments, each segment including a data range and a header range, and a header field with different header ranges preceding those data segments, consists of a transmit processor (14) that responds to input data to produce a data stream of a specified length; a link circuit (16) to receive output data from the transmit processor; a field constructor circuit (17) that operates at an irregular data rate and responds to data from the link circuit to produce an output stream representing the sequence of such data fields, which then represents the data ranges and header ranges with different time intervals; and an output processor (18) where the transmit processor passes the output data stream to the link circuit at a constant, uniform data rate in response to a clock signal which is an integer multiple of SC 3/8, where SC is the system clock signal. 10. The system pursuant to claim 9, where each data segment range includes a component data segment D, which is an integer, and the output processor includes an 8-VSB modulator, is transmitted in response to the SC 3/8 clock signal and data segments, and between data segments, the data transmitted from the transmitter processor corresponds to the SC 3/8 clock signal range. D and E are integers, with D being greater than E. 11. The system pursuant to claim 10, where D is 188 and E is 125. 12. The system under claim 9, where each range of data segments shall include a complementary data segment D, which shall be an integer, shall include an 8-VSB modulator. The data shall be passed in response to the SC 3/4 clock signal, and the ranges of data passed from the transmitting processor shall correspond to ranges D and E, respectively of the SC 3/4 clock signal, where D and E shall be integers, with D being less than E. 13. The system pursuant to claim 12, where D is 188 and E is 438. 14. The system pursuant to claim 9, where each such data segment range includes a component data segment D, which is an integer, and such output processor includes a 16-VSB modulator, is transmitted in response to the SC 3/4 clock signal, and the data segments and between data segments transmitted from such transmitting processor correspond to the SC 3/4 clock signal ranges, respectively, where D and E are integers, with D being less than E. 15. The system pursuant to claim 14, where D is 188 and E is 125. 16. The system under claim 9, and also includes the recording/playback device (15), which is placed in the path of the data stream with a constant data rate between the said transmitting processor and the said link circuit. 17. A receiver system for processing a demodulated and modulated digital stream of data containing visual signal information representing a sequence of data fields, each field consisting of M parts composed of (a) N data fields, each containing a range of data and a range of headers, and (b) header field fields with different header ranges preceding such data fields, where M and N are integers and M is greater than N, responds to the system clock signal (SC) and consists of an input processor (72) to provide a demodulated stream of data representing the sequence of data fields and displaying an uneven data rate; and a field processor (75) to extract the header information from the demodulated stream to produce the stream displaying the uneven data rate. The link circuit (84) receives the output data from the field processor, and the transmit decoder (86) decodes the data received from the link circuit to produce the output data, where the transmit decoder receives the data from the link circuit at a constant constant data rate, and the field processor operates at this constant constant data rate without interrupting the data stream. 18. A system pursuant to claim 17 whereby such link circuit shall include a buffer for the transmission of data from such field processor to such transmit decoder. Such field processor shall transmit data to such buffer at a non-uniform data rate, and such buffer shall transmit data to such transmit decoder at a constant, uniform data rate. 19. A system pursuant to claim 18 where such field processor responds to such system clock signal; such transmit decoder operates in response to a clock signal which is an integer multiple of SC 3/8, where SC is the system clock signal; and such buffer reads data in response to such a multiple of the SC 3/8 clock signal. 20. A system under claim 18 where the size of such buffer is significantly less than the data field and such integer is an even integer. 21. The system pursuant to claim 17, where such output data shall be MPEG compliant, the header section shall include FEC error-corrected information, and the header field shall contain sync field information, and 22. A system pursuant to claim 17 where the output data from such decoder is in the form of byte data and the clock signal of such SC system is a symbolic clock signal. 23. The system under claim 17 and also includes a video recording/playback device (85) which is set up in the path of a constant data stream at a constant data rate between such link circuit and such transmit decoder. 24. In a receiver, a modulated digital stream containing visual information represents a sequence of data fields, each containing M segments composed of (a) N data segments, each containing a data range and a header range, and (b) header field segments with different header ranges preceding such data segments, where M and N are integers and M is greater than N. The processing method consists of the steps of (a) demodulating (72) such data stream to produce a demodulated stream with an uniform data rate; (b) extracting (75) the header information from the demodulated stream without interrupting the stream to produce a stream with an uniform data rate; (c) decoding (86) the information from the stream produced in step (b) at a constant uniform data rate; and (d) carrying (84) the information from step (b) to step (c) at a constant uniform data rate. 25. A receiver system for processing a modulated digital stream of data containing visual signal information representing a sequence of data fields, each field consisting of a number of data segments, each segment including the data segment and the header segment, and a header field segment with different header segments preceding those data segments, shall consist of an input processor (72) for providing the demodulated stream of data representing the sequence of data fields and displaying it at an uneven data rate; a field processor (75) for separating the header information from the demodulated stream to produce a data stream displaying it at an uneven data rate; a link circuit (84) for receiving the output data from the field processor; and a transmit decoder (86) for decoding the data stream received from the link circuit to produce the output data, where the transmit decoder rushes the data stream from the link circuit at a constant, steady data rate in response to a clock signal which is an integer multiple of SC 3/8, where SC is the system clock. 26. A system pursuant to claim 25 where each such data segment range includes a component data segment D, which is an integer; such input processor includes an 8-VSB demodulator; such transmit decoder receives the data stream from the link circuit in response to the SC 3/8 clock signal; and the data- and data-less segments of the data stream received by the transmit decoder from the link circuit correspond to the segments of the SC 3/8 clock signal, respectively, where D and E are integers, with D being greater than E. 27. The system pursuant to claim 26, where D is 188 and F is 125. 28. A system pursuant to claim 25 where each data segment includes a component data segment D, which is an integer; such output processor includes an 8-VSB demodulator; such transmit decoder receives the data stream from the link circuit in response to the SC 3/4 clock signal; and the data- and data-less segments of the data stream received by the transmit decoder from the link circuit correspond to the channels of the SC 3/4 clock signal, respectively, where D and E are integers, with D being less than E. 29. The system pursuant to claim 28, where D is 188 and F is 438. 30. A system pursuant to claim 25 where each data segment includes a component data segment D, which is an integer; such output processor includes a 16-VSB demodulator; such transmit decoder receives the data stream from the link circuit in response to the SC 3/4 clock signal; and the data- and data-non-data segments of the data stream received by the transmit decoder from the link circuit correspond to the channels of the SC 3/4 clock signal, respectively, where D and E are integers, with D being less than E. 31. The system according to claim 30 where D is 188 and F is 125. 32. The system under claim 25, and also includes the recording/playback device (85) which is provided in the path of the data stream with a constant data rate between such link circuit and such transmitting decoder. 33. In a receiver for processing a modulated digital stream containing visual information representing a sequence of data fields, each consisting of a number of data segments, each containing a data segment and a header segment, and a header field with different header segments preceding those data segments, the processing method consists of the following steps: (a) demodulating (72) such stream to produce a demodulated stream with an uniform data rate; (b) separating (75) the header information from the demodulated stream without interrupting the stream to produce a uniform data rate stream; (c) decoding (86) the data from the stream produced in step (b); and (d) carrying (84) the data from step (b) to step (c) at a constant uniform data rate in response to a clock signal which is an integer multiple of SC 3/8, where SC is the system clock.