TW200418143A - Method to increase coupling ratio of source to floating gate in split-gate flash and the structure thereof - Google Patents

Abstract

A method to increase coupling ratio of source to floating gate in split-gate flash and the structure thereof are provided. The present method is characterized in that part of the insulating spacer is isotropica11y etched to expose part of the floating gate. Then, a conformal dielectric layer is formed over the exposed floating gate and a gate oxide layer. According to the present invention, the conformal dielectric layer is extended on part of the floating gate. Thus, the coupling ratio of source to floating gate is increased, thereby improving write and erase efficiency of the flash memory.

Description

200418143 Invention description The present invention relates to a semiconductor memory structure and a method for manufacturing the same, and more particularly to a memory cell (memory ceu) related to a split gate flash memory (spUt gate flash memory). The structure and its manufacturing method are more particularly related to a method for increasing the coupling ratio of the source to the floating gate. Prior art

Complementary metal-oxide-semiconductor (CM0S) memory can be divided into two categories: random access memory (RAM) and read-only memory (R0M). The RAM is a volatile memory limb. The data stored in the RAM will disappear after the power is turned off. However, ROM is very different. Turning off the power does not affect the data stored in it. In the past few years, the market share of 'ROM is gradually expanding, and among them, Flash Memory is even more remarkable. Because flash memory can be written to a single memory cell in an electrically programmable manner at the same time, it can be electrically modified for most of the memory cell blocks ^ "以 ^ ㈡ 丨 ^" "仏丨 ^ ways to modify its content 'The flexibility and convenience of its use has exceeded the erasable and programmable read-only memory (EPR0M) and the erasable and programmable read-only memory (EEPR0M)' And more importantly, the manufacturing cost of flash memory is lower. Because of the above advantages, flash memory is now widely used in many consumer electronics products, such as laptops, smart cards, digital Cameras and communication applications ... etc. These

0503-9498TWF (Nl); TSMC2002-0915; jacky.ptd

200418143 V. Description of the invention (2) Since the consumer electronics products have to meet the needs of consumers, the amount of data to be processed or stored is also increasing, so the memory capacity of the flash memory responsible for accessing data has also changed Four million bits has increased rapidly to 256 million bytes (256M bytes). In the near future, flash memory with a memory capacity of one billion bytes (1G bytes) will also be on the market. Since the flash memory data write and erase efficiency / programming speed is proportional to the degree of capacitive coupling between the source and the floating gate, how to increase the source to the floating gate Coupling ratio (hereinafter referred to as source coupling ratio, SCR) has become one of the research focuses of flash memory. One known technique is to increase the lateral diffusion of source doping (source implant lateral diffusion) to increase the source coupling rate, however, this will shorten the length of the channel (cha η ne 1 1 ength) between the source and the non-electrode, and there will be punch-through and junction breakdown or failure. The problem of junction breakdown / leakage occurs. The following figure 1 is used to explain the memory cell structure of the conventional flash memory. As shown in FIG. 1, two MOS transistors formed on the semiconductor substrate 10 active region (active reg 100n) share a source electrode 25. Each transistor system has a first doped region 20 (ie, the drain), a second doped region 25 (ie, the source), a channel 23, a gate oxide layer 30, and a floating electrode. The gate 40 is set, an intergate dielectric layer 50 and a control gate 60. " Still referring to FIG. 1, the first doped region 20 and the second doped region 25 are connected to

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The channels 23 are all located in the substrate 10, and the channels 23 are located between the first doped region 20 and the second doped region 25. The gate oxide layer 30 is located on the substrate 10, and the floating gate 40 is insulated from the substrate 10 by the gate oxide layer 30. At the same time, 'floating ^ idle 40' is insulated from the control gate 60 through the inter-gate dielectric layer 50. The control gate 60 is located on the upper side of the channel 23, and the control gate 60 is insulated from the substrate 10 by a gate oxide layer 30. In addition, the first insulating spacer (0) is located on the side wall of the floating gate 40, and the second insulating spacer (8) is located on the side wall of the control gate 60. Furthermore, the floating gate The top 40 is oxidized to form a polycrystalline oxide cap 45 (poly oxide cap). In US Patent No. 6 3 0 5 8 3 and US Patent Early Publication No. · 2 0 0 2/0 1 In No. 0 9 1 8 there is a method for increasing the source coupling rate of the flash memory. This method uses the upper surrounding space in an insulation slot (sn) separating the active area to extend the floating gate. In the upper surrounding space in the above-mentioned insulation trench (ST I), the coupling area between the source and the floating idler in the substrate is increased, thereby increasing the source coupling rate. However, 'in the actual process' When this method is used to define the upper surrounding space of the floating gate formed in the insulation trench (ST I), there may be a process problem of misal ign, which makes the profile of the floating gate difficult to grasp. In U.S. Patent No. 6 3 5 5 5 2 7 there is provided a method for adding flash memory Method for source coupling rate. This method forms a polycrystalline stone wall (ρ ο 1 ywa 1 1) along the middle of two floating gates, and the polycrystalline stone wall is located above the source electrode, so that the source electrode can be improved. Face-to-face ratio. In US Patent Early Publication No. 2002/0142545, it is mentioned

200418143 V. Description of the invention (4) A method for manufacturing a memory cell of a split flash memory. This method provides a flash memory cell process that can reduce the use of photomasks. However, this method does not reveal how to increase the source coupling rate. SUMMARY OF THE INVENTION In view of this, an object of the present invention is to provide a method for manufacturing a memory cell of a flash memory, so as to increase the coupling ratio of the source to the floating gate. Another object of the present invention is to provide a memory cell structure of a flash memory for increasing the coupling rate from the source to the floating gate. To achieve the above object, the present invention provides a method for manufacturing a memory cell of a flash memory, which includes at least the following steps: providing a substrate; defining an active area on the substrate; sequentially forming a first gate insulating layer and a A first conductor layer on the substrate in the active area; forming a buffer layer with a first opening on part of the first conductor layer, wherein the first opening exposes part of the first conductor layer; remove Part of the first conductor layer, so that both sides of the first conductor layer located in the first opening are inclined; forming an insulating gap on a side wall of the first opening, and covering part of the first A conductor layer; removing the first conductor layer located under the first opening by using the insulating gap wall as a shielding cover;

0503-9498TWF (Nl); TSMC2002-0915; jacky.ptd Page 8 V. Description of the invention (5) The first conductor layer \ a part of the first conductive layer \ knife of the insulation gap is removed in a straightforward manner and a length of A compliant belt is formed on the first gate insulating layer; the first conductor layer on the exit and a part of the first conductive layer should form a compliant capacity process-anisotropic: Γ layer on the dielectric layer; layer, A part of the dielectric layer is etched back to make the private part, and the part of the polycrystalline silicon layer and the S-gate insulation layer of the polycrystalline silicon are removed. The dielectric layer is square on the side wall of the insulating gap, and the first opening layer and a part of the first gate insulating layer are partially exposed with a pound of 1 part of the substrate; one doped region is in place In the first opening, a contact profile is formed in the 5H substrate, and the first doped region is connected to the soil. In the first opening, the contact plug is electrically connected to 4′-ft. " ih ΐϋ 4: ^ surface;, an oxide layer is formed on the top of the contact plug, with the oxidized layer and the insulation gap as a shield The curtain, the iI layer and part of the f a ^ @ π 勹 I 敝 soap power, remove the 绫 punch; the body layer, thus defining a floating idle and a second gate insulation compliant with a second opening ^ f Layer on the surface of the second opening; a compliant second conductor layer covers the substrate; a trowel etches back the second conductor layer, thus defining a control gate located between the insulation gap and the floating On the second interlayer insulating layer of the wall; and forming a second doped region in the substrate located within the second opening

0503-9498TWF (Nl); TSMC2002-0915; jacky.ptd Page 9 200418143 V. Description of the invention (6) The memory cell structure is also provided by the present invention. The flash memory includes at least: a force-based substrate having A source electrode, a drain electrode, and _ and the drain electrode; the forcing is located on the source electrode and a floating gate formed above part of the channel, and the substrate is insulated; and wherein the floating gate and a control The gate is formed above part of the channel, the base of which is insulated and isolated, and the _ ^, μ-technology gate,-the door gap cadmium η idle system insulation isolation; A floating gate on the side of the control gate; and the 7-knife-compliant dielectric layer of the covering part is formed on part of the first part which is not covered by the insulation gap, Λ but gate μ &amp; The upper layer of the winter layer <4 &gt; 0 and 2 on the pre-set gate and on the part of the insulation gap is explained by this matter, according to the theory that the capacitance is proportional to the area of the dielectric layer (0 ε A / d = ε WL / d) The invention increases the area of the dielectric layer because the compliant dielectric layer is extended to the floating gate, so the source electrode is increased. Floating gate coupling ratio (coupling ratio 〇f source to fi〇ating ga t e) 'thereby raising the write and erase the flash memory of efficiency. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, preferred embodiments are described in detail below in conjunction with the accompanying drawings, which are described in detail as follows: Embodiments: The following uses FIGS. Flash memory cell manufacturing process of the present invention

0503-9498TWF (Nl); TSMC2002-0915; jacky.ptd Page 10 200418143 V. Description of the invention (7) It is especially applicable to embedded flash memory architecture. Referring to FIG. 2, a semiconductor substrate 2 0 0 such as silicon is provided. Then, a shallow trench isolation process (ST I) or a field oxidation process (F 0 X) is performed on the substrate 200 to form an insulation isolation region (not shown), and the insulation isolation region (not shown) is used to form the insulation isolation region (not shown). Insulation isolation and definition of each active region location. Secondly, referring to FIG. 2, a first gate insulating layer 210, a first conductor layer 220, and a buffer layer 230 are sequentially formed on the substrate 2000 in the active region. The first gate insulating layer 2 1 0 is, for example, a Si 02 layer formed by an oxidation method, and the first conductor layer 2 2 0 is, for example, a doped polycrystalline silicon (polysi 1 icon) formed by a deposition method. ) Layer, and the buffer layer 230 is, for example, a S i N or S i 0 N layer formed by a deposition method. Then, by a photolithography step, a part of the buffer layer 230 is removed to form a first opening 240, and a part of the first conductor layer 220 is exposed. Secondly, referring to FIG. 2, the buffer layer 230 is used as a shielding mask, and a slope-shaped etching process (s 1 ope etching) is performed on the first conductive layer 2 2 0, which belongs to an isotropic pattern. Engraving process), and the first conductor layer 2 2 0 is etched by the isotropic part I, so that both sides of the first conductor layer 2 2 0 in the first opening 240 present a slope shape, so that The tip of the floating side will be formed in the future. Here, in order to make the sharp cornering phenomenon more obvious, an oxidation reaction may be performed so that an oxide layer (not shown) is formed on the top surface of the first conductor layer 220 located in the first opening 240. Secondly, referring to FIG. 3, an insulating spacer 310 is formed on a side wall of the first opening 240, and the insulating spacer 310

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V. Description of the invention (8) Cover the first conductor layer 2 2 0. The method for forming the insulating spacer 3 1 0 is, for example, first forming a compliant oxide layer (TE 0 S-S i 〇2 layer, not shown, covering the buffer layer 23 0 and the first conductor layer 2 2 0, and then perform an anisotropic money etch such as a dry / I dryetching method to remove part of the oxide layer (not shown) to form the insulating barrier 3 1 0. Secondly, please refer to the third In the figure, the barrier wall 3 1 0 is used as a shielding cover, and the first conductive layer 22Q located under the first opening 240 is removed, thereby exposing the first gate insulating layer 2 10. Next Please refer to FIG. 4, for example, a wet etching method is used to isotropically remove a part of the insulating spacer 3 1 〇 to expose a part of the first conductive layer 22 0 having a length a. That is to say, after the above-mentioned wet-shaving process, the remaining insulating spacer 3 1 0 is formed to cover a part of the first conductor layer 22 0, and the portion of the first conductor layer that is not covered and exposed by the insulating spacer 3 10 ′ is formed. 410 has a length a. Next, a compliant dielectric layer 420 is formed. The dielectric layer 420 can be further extended to the surface of the buffer layer 230 on the first conductive layer portion 4 10 and a portion of the first gate insulating layer 210. The dielectric layer 420 is, for example, deposited by a deposition method. The formed wo layer may have a thickness of 100 to 300 angstroms. 3 ′ Secondly, referring to FIG. 5, a compliant polycrystalline silicon layer (not shown) is first formed on the dielectric layer 420. Then, for example, a dry layer is used. In the etching method, an anisotropic partial etching back process is performed to remove part of the polycrystalline silicon layer (not shown), part of the dielectric layer 42 and part of the first gate insulating layer. 2 1 0, and the remaining polycrystalline silicon layer 5 (the polycrystalline silicon spacer wall) and the remaining dielectric layer 4 20 are formed in the insulating layer

200418143 V. Description of the invention (9) 310 'side wall, and located above the exposed first conductor layer portion 41o and the first knife gate, the sloping edge layer 2 1〇, and making the first opening A portion of the substrate 200 is exposed underneath 2 4 0. In addition, it should be explained here that after the above-mentioned remnant process, there may be a small amount of the dielectric layer 4 2 0, and the polycrystalline silicon layer 5 2 0 extend to a part of the substrate 2 0. However, for convenience of explanation, here Not shown. Secondly, please refer to FIG. 5 to perform an ion implantation process to form a doped region wo as a source in the first opening 240. The substrate was 2000. Secondly, referring to FIG. 6, a contact plug (contact _ 丨 p 1 ug) 6 1 0 is formed in the first opening 24 0, and the contact plug 6 1 0 is electrically connected to the first doped region. 5 2 0. The method for forming the contact plug 6 丨 0 is, for example, firstly depositing a doped polycrystalline silicon layer (not shown) to fill the first opening 240, and then performing a planarization process (such as CMP and partial etchback). ) To obtain a contact plug 610 with a flat surface. After that, an oxidation process is performed to form an oxide layer 620 on the top surface of the contact plug 610. It should be explained here that, since the material of the contact plug 6o0 and the polycrystalline silicon layer 5o0 in this embodiment are both polycrystalline silicon, they are combined here as the contact plug 6o0. Secondly, 'Please refer to FIG. 7, using the oxide layer 6 2 0 and the insulating spacer · 3 1 0 as a cover screen', first remove the buffer layer 2 with an isotropic cut (such as a wet rice cut) 2 3 0 'Then part of the first conductor layer 2 2 0 is removed with an anisotropic cut (for example, a dry cut), so a floating gate 71 () and a second opening 7 2 0 are defined. . Next ’Please refer to FIG. 8 to form a compliant second gate insulating layer

200418143 Description of the invention (10) 810 (also known as an intergate / interpoly dielectric layer) on the surface of the second opening 7 2 0. The second gate insulating layer 8 1 0 is, for example, a high temperature oxide layer (HT0, Si 02) formed by a deposition method. Here, for convenience of explanation and simplified illustration, the first gate insulating layer 2 1 0 and the second gate insulating layer 8 丨 located in the second opening 7 2 〇 are combined to form the second gate insulating layer 8 丨 〇 Next, referring to FIG. 8 again, a compliant second conductor layer (not shown) is formed to cover the substrate 200. Then, for example, using a dry etching method, the second conductor layer (not shown) is partially etched back anisotropically, so a control gate (c ο ntr ο 1 gate) 8 2 0 is located at The insulating spacer 3 1 0 ′ and the second gate insulating layer 8 1 0 on the side wall of the floating gate 7 10. The material of the control gate 8 2 0 is, for example, a doped polycrystalline silicon layer. Secondly, referring to FIG. 9, the second gate insulating layer 8 1 0 not covered by the control gate 8 2 0 is removed to expose a part of the substrate 2 0 0. Next, an ion implantation process is performed to form a doped region 9 1 0 which is regarded as an electrode (d r a i η) in the substrate 200 located in the second opening 720.

According to the process of this embodiment, the present invention also provides a memory cell structure of a flash memory. See FIG. 9. The memory cell structure includes at least: a substrate 200 having a source electrode 520, a drain electrode 910, and a The channel 920 is located between the source 5 2 0 and the drain 910; a floating gate 7 1 0 is formed above a part of the channel 9 2 0, wherein the floating gate 7 1 0 is related to the substrate 2 0 0 With a first gate insulating layer 2 1 〇

200418143

-Control gate 820, formed in part of the channel 92 ° system 820 and the base 200 by-the second idler insulation ^ 〇 the middle edge is controlled away from the ground and the control gate 8 2 0 and the floating Gate 71 ° system: layer 810 insulation isolation; Nadu ,,, and Ba margin "an insulating gap wall, formed on the side wall of the control gate, 盍 part of the floating gate 71 °; and 1-compliant dielectric A layer 420 'is formed on a part of the first-gate insulating layer 210 and is not covered by the insulating gap 31o, and the insulating gap 31o is covered on the floating gate 71o. Features and advantages of the present invention The manufacturing process is characterized by isotropically removing part of the insulating gap wall to expose part of the floating gate, and forming a compliant dielectric layer on the exposed floating gate and floating gate insulating layer. Structural features of the flash memory cell of the present invention It has a compliant dielectric layer formed on part of the first gate insulating layer, on the floating gate not covered by the insulating gap wall, and on part of the insulating gap wall. The memory cell structure is borrowed A light punch between the source and the floating gate is added by the dielectric layer Rate (coupling ratio of source to floating gate) ° According to the theory that the capacitance is proportional to the area of the dielectric layer (C = eA / d: ε WL / d), the invention extends the compliant dielectric layer to the floating gate. The area of the dielectric layer is increased, so the coupling ratio of source to floating gate is increased, so

0503-9498TWF (Nl); TSMC2002-0915; jacky.ptd page 15 200418143 V. Description of the invention (12) The efficiency of writing and erasing the flash memory has been improved. Although the present invention is disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application.

0503-9498TWF (Nl); TSMC2002-0915; jacky.ptd Page 16 200418143 The diagram briefly illustrates the cross-sectional schematic diagram of the conventional flash memory cell structure in Figure 1; and Figures 2 to 9 are the schematic diagrams of the embodiments of the present invention. Schematic cross-sectional view of the process of flash memory cells. Symbols description of the conventional part (Figure 1) •, wall gap electrical room •, intermediary edge ·, ·, inter-gate absolute pole electrode 0-drain source floating gate 〇〇ο ο ο 4 5 7 10 ~ semiconductor substrate; 23 ~ channel; 30 ~ gate oxide layer; 4 5 ~ polycrystalline silicon oxide cap layer; 60 ~ control gate; part of this case (Fig. 2 ~ 9) 2 0 ~ semiconductor substrate; 210 first conductor layer; 230 An opening; 310 exposed portion of the first conductor layer; 42 0 ′ ~ dielectric layer; source; 220 240 410 420 520 620 720 720 820 920 first gate insulating layer; buffer layer; 3 1 0 '~ insulation gap The second wall oxide layer opens the control gate channel. 5 1 0 to polycrystalline silicon layer; 6 1 0 to contact plug; 7 1 0 to floating gate; 8 1 0 to second gate insulating layer 9 1 0 to drain;

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Claims (1)

1. Step i of the scope of patent application: A method for manufacturing a memory cell of a flash memory, which includes the following steps: providing a substrate; sequentially forming a stack; forming a gate insulating layer and a first conductor layer on the substrate; A buffer layer on the right side of the # 1 opening is part of the first conductor layer 2 + 5H. The first opening exposes part of the first conductor layer; On the side wall of an opening, and the covering part is a "conductor-conductor layer"; the next is: "the insulation gap wall is used as a shielding cover, and the conductor-conductor layer located under the first opening is removed; etc. fh body layer, ; Part of the insulating gap is removed, and part of the first conductive gate insulation is exposed: f Γ a dielectric layer is exposed on the first conductor layer, the first gate layer, the edge layer and part of the On the substrate;-between the ::;: a portion of the dielectric layer and a portion of the first layer and the winter layer, and a portion of the substrate is exposed; a first doped region is formed in the first opening; Xi Ayan forms a contact plug in the first q substrate, and then connects to the first doping ; Electrical connection is formed with the inner V contact plug: an oxide layer is on the top surface of the contact plug; a layer between the oxidized layer and the insulation and a portion of the first conductor layer is removed for reasons; 叩Yi Yi out / pre-set gate and a second open page 18 0503-9498TWF (Nl); TSMC2002-0915; jacky.ptd 200418143 Sixth, the scope of patent application forms a compliant second gate insulation layer in the second opening On the surface; forming a control gate on the second gate insulating layer positioned on the insulating gap wall and the side wall of the floating gate; and forming a second doped region in the substrate positioned within the second opening 2. The method for manufacturing a memory cell of a flash memory as described in item 1 of the scope of the patent application, wherein the step of forming the control gate includes: forming a compliant second conductor layer to cover the substrate; partially etching back the first Two conductor layers, thus defining the control gate on the second gate insulation layer located on the insulation gap wall and the side wall of the floating gate. 3. The flash memory as described in item 1 of the scope of patent application Manufacturing method of memory cell, wherein the base It is a semiconductor substrate. 4. The method for manufacturing a memory cell of a flash memory as described in item 1 of the scope of patent application, wherein the first gate insulating layer is a Si 02 layer. The method for manufacturing a memory cell of a flash memory according to the above item, wherein the first conductor layer is a polycrystalline silicon layer. 6. The method for manufacturing the memory cell of the flash memory according to item 1 of the patent application scope, wherein the The buffer layer is a SiN layer. 7. The method for manufacturing a memory cell of a flash memory as described in item 1 of the scope of the patent application, wherein the insulating spacer is a TEOS oxide layer. 8. As the item 1 of the scope of patent application In the method for manufacturing a memory cell of the flash memory, the dielectric layer is an ON0 layer. 9. The method for manufacturing a memory cell of a flash memory as described in item 1 of the patent application scope, wherein the contact plug is a polycrystalline silicon layer. 10. Flash memory as described in item 1 of the scope of patent application 0503-9498TWF (Nl); TSMC2002-0915; jacky.ptd Page 19 200418143 VI. Scope of Patent Application Manufacturing method, wherein the second interrogation insulating layer is a SiO2 layer. 11. The method for manufacturing a memory cell of a flash memory according to item 2 of the scope of the patent application, wherein the second conductor layer is a polycrystalline silicon layer. 12. · A method for manufacturing a memory cell of a flash memory, including the following steps: providing a substrate; sequentially forming a first gate insulating layer and a first conductor layer on the substrate; and forming a first opening A buffer layer on a portion of the first conductor layer, wherein the first opening exposes a portion of the first conductor layer; a portion of the first conductor layer is removed, and the brother-conductor located within the first opening is removed The two sides of the layer are inclined; an insulating gap is formed on the side wall of the first opening and covers part of the first conductor layer; the insulating gap is used as a shielding cover, and the first opening is removed. The first conductor layer underneath; isotropically removing a part of the insulation gap to expose a portion of the first conductor layer having a length; The -th part of the exposed -conductor layer should form a compliant polycrystalline silicon layer on the dielectric layer; a non-isotropic partial etch-back process is performed to remove part of the polycrystalline silicon layer, An electrical layer and a part of the first-pole insulating layer, so that the remaining Xijingmeng layer and the remaining dielectric layer are formed on the sidewall of the insulating gap wall, and 200418143 6. Scope of Patent Application It is located on the exposed side, and 哕 ί = the conductor layer and part of the first gate insulating layer ^ A part of the substrate is exposed in an opening; forming a H-cohesive region at the first opening Inside the substrate; forming an impurity-receiving region connected to the e-diode; a contact plug in the first opening, the contact plug electrically forming an oxide layer on the top surface of the contact plug; oxygen Layer and the insulation gap wall are shielding veils, removing the buffer layer and part of the first conductor layer, thus defining a floating gate and a second opening; forming a compliant second gate insulating layer on the first Two opening surfaces; forming a control gate on the second gate insulating layer located on the insulating gap wall and the side wall of the floating gate; and forming a doped region in the substrate located in the second opening . 13. The method for manufacturing a memory cell of a flash memory according to item 2 of the patent application scope, wherein the step of forming the control gate includes: forming a compliant second conductor layer to cover the substrate; The second conductor layer thus defines the control gate on the second gate insulation layer located on the insulation gap wall and the floating gate side wall. 14. The flash manufacturing method as described in item 12 of the scope of application for patents, §5, 5th memory cells, wherein the substrate is a "semiconductor substrate." 15. As described in item 12 of the scope of the patent application, the manufacturing method of the 5th and 10th cells is described in detail, wherein the first gate insulating layer is a SiO 2 layer. 16. The method for manufacturing a memory cell of a flash memory as described in the item No. 2 of the patent application scope, wherein the first conductor is a polycrystalline polycrystalline layer 0503-9498TWF (Nl); TSMC2002-0915; jacky.ptd Page 21 200418143 VI. Application for patent scope 17. For example, the method for manufacturing flash memory memory cells described in Item 12 of the patent scope, where the Buffer layer S 丨 N layer ρ # 18 • As described in item 12 of the scope of the patent application, a method for manufacturing a 5-cell body and a s-cell cell, wherein the insulation gap split system TE ° S ff f _ 19, For example, the manufacturing method of item 12 in the scope of patent application, wherein the dielectric layer is 0N0 wide. 2 0. The method for manufacturing a flash memory memory cell as described in Item 12 of the scope of the patent application, wherein the contact plug is a polycrystalline layer ° 21. The method for manufacturing a flash memory § memory cell according to item 12 of the scope of the patent application, wherein the second gate insulating layer is a s0 02 layer. 22. Memory of flash memory as described in item 13 of the scope of patent application A method of manufacturing a cell 'wherein the second conductor layer is a polycrystalline shredded layer. 2 3. The method for manufacturing a memory cell of a flash memory according to item 12 of the scope of the patent application, wherein the method of making the two sides of the first conductor layer located in the first opening have a slope shape, The first tomb body layer is partially etched isotropically. '2 4. A memory cell structure of flash memory, a substrate with a source, an electrode, and a drain; includes: a channel is located at the source and a floating gate is formed in part of the Above the channel, its φ, the base is insulated, · i _ A control gate, which forms the base system insulation isolation, and an insulation gap wall is formed above a part of the channel, and the control gate and the floating are formed on the control gate side, and the control gate is insulated from the gate system; , And covering part of that 0503-9498TWF (N1). TSMC2002-0915; jacky.ptd Page 22 200418143 VI. Scope of patent application Floating gate; and a compliant dielectric layer formed on part of the first gate insulating layer, on the floating gate not covered by the insulating gap wall, and on part of the insulating gap wall. 25. The memory cell structure of a flash memory as described in item 24 of the scope of patent application, wherein the substrate is a semiconductor substrate. 26. The memory cell structure of the flash memory as described in item 24 of the scope of the patent application, wherein the insulating spacer is a TEOS oxide layer. 27. The memory cell structure of the flash memory as described in item 24 of the patent application scope, wherein the dielectric layer is an ON0 layer. 28. The memory cell structure of the flash memory as described in item 24 of the scope of the patent application, wherein the thickness of the dielectric layer ranges from 100 to 300 angstroms. 0503-9498TWF (Nl); TSMC2002-0915; jacky.ptd page 23