TW200419667A - Method to roughen a surface of a body and optoelectronic component - Google Patents

Method to roughen a surface of a body and optoelectronic component Download PDF

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Publication number
TW200419667A
TW200419667A TW092137040A TW92137040A TW200419667A TW 200419667 A TW200419667 A TW 200419667A TW 092137040 A TW092137040 A TW 092137040A TW 92137040 A TW92137040 A TW 92137040A TW 200419667 A TW200419667 A TW 200419667A
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Taiwan
Prior art keywords
etching
mask
patent application
layer
scope
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TW092137040A
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Chinese (zh)
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Reiner Windisch
Heribert Zull
Ralph Wirth
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Osram Opto Semiconductors Gmbh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/81—Bodies
    • H10H20/819—Bodies characterised by their shape, e.g. curved or truncated substrates
    • H10H20/82—Roughened surfaces, e.g. at the interface between epitaxial layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group IV materials or Group III-V materials
    • H10P50/692—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group IV materials or Group III-V materials characterised by their composition, e.g. multilayer masks or materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group IV materials or Group III-V materials
    • H10P50/693—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group IV materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane
    • H10P50/695—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group IV materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4085—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes characterised by the processes involved to create the masks

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  • Drying Of Semiconductors (AREA)
  • Led Devices (AREA)

Abstract

This invention relates to a method to roughen a surface of a body (1), with the following steps: coating the surface with a mask-layer (2), applying preformed mask-bodies (3) on the mask-layer (2), etching-through the mask-layer on the positions uncovered by the mask-bodies (3), etching the body (1) on the positions, which are free from the mask-layer (2), of its surface. In addition, this invention relates to an optoelectronic component. By using the mask-layer (2) as additional auxiliary masks, the methods with lower selectivity against the polystyrole-balls can be used to etching.

Description

200419667 玖、發明說明: 【發明所屬之技術領域】 本發明涉及一種半導體本體之表面粗糙化所用之方法, 其中該粗糙化是藉由蝕刻來達成。 已粗糙化之表面特別是可有利地與發光二極體(LED)相關 聯而被使用著,其原因是形成該LED用之基底所用之半導 體本體所具有之先射出性。此處通常存在一^種較大之折射 率跳躍値,其中該半導體材料之折射率通常是n = 3.5。圍繞 該半導體本體之樹脂所具有之折射率通常是η = 1.5。這樣對 由該半導體本體所發出之輻射而言即造成一種較大之折射 率跳躍値。於是會對周圍之樹脂形成一種小之全反射角, 其大約是26G。該全反射角使半導體本體中所產生之光中只 有一小部份可射出。典型上在製程中所使用之立方體形式 之LED中,未在大約26°範圍之射出錐體中發出之輻射仍 會落在半導體晶體中,此乃因其相對於表面法線之角度亦 不會由於多次反射而改變。光束因此遲早會由於吸收作用 而主要在接觸區,活性區或基板等這些區域中消失。 半導體本體之表面之粗化現在可有利地用來使傳送於該 射出錐體外部之輻射被發散至此種錐體中。這主要是在具 有透明基板-或在活性區下方具備有效反射面之LED-晶片 中(特別是薄膜-LED中)會令人感興趣。此種優點亦適用於 有機LEDs中。 【先前技術】 由文件US 3 7 3 92 1 7中已知光由鎵-磷-晶體發出時之射出 200419667 性可藉由表面之粗糙化來改進。 由 R· Windisch et al 之 ”40 % Efficient Thin-Film Surface-200419667 (1) Description of the invention: [Technical field to which the invention belongs] The present invention relates to a method for roughening the surface of a semiconductor body, wherein the roughening is achieved by etching. The roughened surface can be used in particular in connection with a light emitting diode (LED) advantageously because of the pre-emission property of the semiconductor body used to form the substrate for the LED. There are usually ^ larger refractive index jumps, where the refractive index of the semiconductor material is usually n = 3.5. The refractive index of the resin surrounding the semiconductor body is usually η = 1.5. This causes a large refractive index jump for the radiation emitted by the semiconductor body. Therefore, a small total reflection angle is formed on the surrounding resin, which is about 26G. This total reflection angle allows only a small portion of the light generated in the semiconductor body to be emitted. Typically, in the cube-shaped LED used in the process, the radiation that is not emitted from the emission cone in the range of about 26 ° will still fall in the semiconductor crystal, because its angle with respect to the surface normal will not Changes due to multiple reflections. Sooner or later, the light beam will disappear mainly in these areas such as the contact area, the active area, or the substrate due to absorption. The roughening of the surface of the semiconductor body can now advantageously be used to radiate radiation transmitted outside the exit cone into such cones. This is mainly of interest in LED-wafers (especially thin-film-LEDs) with transparent substrates or effective reflective surfaces under the active area. This advantage also applies to organic LEDs. [Prior Art] It is known from the document US 3 7 3 92 17 that the light emitted when gallium-phosphorus crystal is emitted. 200419667 The property can be improved by roughening the surface. By R. Windisch et al. "40% Efficient Thin-Film Surface-

Textured Light-Emitting Diodes by Optimization of NaturalTextured Light-Emitting Diodes by Optimization of Natural

Lithography55, IEEE Transactions on Electron Device, Vol. 47, No. 7, 2000, p 1492-1498,中已知使以鋁-鎵-砷爲主之半導體 本體粗糙化,以便使光由半導體本體發出時之射出性可獲 得改良。因此使用以下所描述之粗糙化所用方法。在半導 體本體之表面上施加由聚苯乙烯所構成之小球,這例如可 在一種單層中在一種水面上製備完成且然後藉由浸入方式 而轉移至該半導體本體之表面。在水乾燥之後各小球黏合 在該半導體本體之表面上。然後對該表面進行乾燥式蝕 刻,於是在各小球之位置上仍保留著柱狀物且各柱狀物之 間之空間藉由乾燥式蝕刻以便由半導體本體中蝕刻而去 除。 上述半導體本體之表面粗糙化所用之習知方法之缺點 是:其不適合用在一由鋁-鎵-因·磷化物或鋁-鎵·因-氮化物 等材料所構成之半導體本體中。其原因是··所使用之乾燥 式蝕刻方法對該聚苯乙烯-小球而言具有一種太小之選擇 性。這表示:該半導體本體只能以較各小球慢很多之速率 而被蝕刻。這就是爲什麼作爲蝕刻遮罩用之小球在該蝕刻 過程之很早之時點時(此時該半導體本體之表面中只被蝕刻 出一種很小之結構深度)已浪費很多之原因所在。其結果 是:所需之蝕刻深度相對於結構寬度之比(rati〇)不能達到 0.25至5之値。此種比値是需要的,以便可有效地改進該 200419667 光由半導體本體發出時之射出性。 【發明內容】 本發明之目的是提供一種半導體本體之表面粗糙化所用 之方法,其適合用在很多種不同之材料中。 該目的以申請專利範圍第1項之方法來達成。本方法有 利之其它形式描述在申請專利範圍各附屬項中。 本發明之基本觀念是使所使用之蝕刻方法之選擇性問題 可被減輕,此時除了藉由聚苯乙烯小球所達成之遮罩作用 之外亦使用另一輔助遮罩。構成該輔助遮罩所用之材料不 但與待蝕刻之半導體本體之材料不同且亦與各小球之材料 不同。藉助於該另一遮罩,則該蝕刻過程可劃分成二個步 驟,其中在第一步驟中各配置在表面上之小球之結構轉移 至該輔助遮罩中。在第二步驟中該輔助遮罩之結構轉移至 該待蝕刻之半導體本體之表面中。 由於除了各小球之外另一材料亦加入成爲遮罩,則材料 組合可有很大之選擇性,其中各過程可針對該遮罩材料和 待蝕刻之材料之間之已提高之選擇性而被最佳化。例如, 可形成一種蝕刻方法,其不適用於由小球和待蝕刻之半導 體本體所形成之特定之材料組合,但此種方法依據目前二 步驟式之蝕刻方法可用來進行第一蝕刻步驟。此外,現在 亦可藉由一種方法來蝕刻該待粗糙化之本體,該方法未必 選擇性地針對該表面上之各小球來進行。反之,當該第二 蝕刻步驟一方面對該輔助遮罩之材料具有高的選擇性且另 一方面對該待蝕刻之本體亦具有高的選擇性時即已足夠。 200419667 提供一種使本體之表面粗糙化所用之方法,其包含以T 之步驟: 在第一步驟中,該本體之表面塗佈一種遮罩層。 在下一步驟中在該遮罩層上施加已預成形之遮罩體。 在下一步驟中,對該遮罩層進行蝕刻且是在未由各遮章 體所覆蓋之位置上進行。 在下一步驟中,該本體在其表面之由該遮罩層所露出之 位置上被蝕刻。 本方法之優點是:藉由加入另一蝕刻遮罩,則該蝕刻過 程可劃分成二個步驟,其中一種蝕刻過程(其很選擇性地相 對於已預成形之遮罩體而對該本體進行蝕刻)已不需要。反 之,藉由遮罩體-和遮罩層之材料之改變可使一種寬廣之光 譜適用在可能之蝕刻方法中,即,一種較寬之光譜可用在 蝕刻過程之蝕方法中。 在本方法之一種實施形式中,該本體含有鋁-鎵-因-磷化 物(A1 G a I η Ρ)。此種半導體材料可有利地用在紅色光譜區_或 藍色光譜區中發射之發光二極體中。此種半導體材料可選 擇性地沈積在碳化矽上或鎵-砷-基板上。 在本方法之另一有利之實施形式中,該本體含有鋁-鎵_ 因-氮化物(A1 GainΝ)。該材料亦可特別適合地用在紅色光譜 區-或藍色光譜區中之發光二極體中。 在本方法之一種實施形式中施加一種遮罩層,其由介電 質所構成。可考慮SlxNY(例如,Sl3N4, Sl〇N,Sl〇2, Ai2〇3) 和其匕類似之材料作爲介電質。但其它材料亦可適用於遮 200419667 罩層。重要的只是:該遮罩層之材料允許一種蝕刻過程能 選擇性地對該遮罩體進行鈾刻且該本體允許另一不同之蝕 刻過程選擇性地對該遮罩層進行蝕刻。 在本方法之一種實施形式中,可使用由聚苯乙烯所構成 之小球於已成形之遮罩體中。由於其良好之化學穩定性且 由於能以簡易-且便宜之裝置以大件數之方式來製成該聚苯 乙烯-小球,則這些聚苯乙烯-小球特別適用於上述方法中以 作爲遮罩體。 各遮罩體能以隨機之配置形式施加在該.遮罩層之表面上 成爲單層或施加成一種規則之配置形式。 在本方法之一種有利之實施形式中,藉由乾蝕刻方法來 進行蝕刻步驟。例如,可考慮使用反應性離子蝕刻 (RIE = Reactive Ion Etching),離子束蝕刻(IBE = I〇n Beam Etching)和化學促進之離子束蝕刻(CAIBE^Chemical Assisted Ion Beam Etching) 0 例如,亦可考慮使用一種感應性耦合之電漿蝕刻方法 (ICP = Inductive Coupled Plasma)作爲乾鈾刻方法。 本方法中乾蝕刻方法之優點是:不需使用流體,這樣可 提高該遮罩體之局部穩定性,此乃因流體中之流動現象已 不會發生。 在本方法之一種有利之實施形式中,其進行方式是在該 本體之表面上保持著各結構,各結構之寬度b對蝕刻深度t 之比是: 0.1 < t/b < 10. 200419667 本方法較佳是在符合以下之條件下進行: 0.25 < t/b < 5. 此種深度對寬度之比是特別有利的,以便使光學半導體 晶體之表面上之散射性獲得改良,且亦使光由晶體向外之 發射性獲得改良。 上述之蝕刻深度對寬度之比可藉由適當地選取該蝕刻過 程以及該遮罩體之大小和材料來達成。Lithography55, IEEE Transactions on Electron Device, Vol. 47, No. 7, 2000, p 1492-1498, is known to roughen a semiconductor body mainly composed of aluminum-gallium-arsenic so that light can be emitted from the semiconductor body. The injection properties can be improved. Therefore, the method for roughening described below is used. A ball made of polystyrene is applied on the surface of the semiconductor body, which can be prepared, for example, in a single layer on a water surface and then transferred to the surface of the semiconductor body by immersion. After the water is dried, the beads adhere to the surface of the semiconductor body. The surface is then dry-etched, so that pillars remain at the positions of the small balls and the space between the pillars is removed by dry etching in order to be etched from the semiconductor body. A disadvantage of the conventional method for roughening the surface of the semiconductor body described above is that it is not suitable for use in a semiconductor body composed of materials such as aluminum-gallium-in-phosphide or aluminum-gallium-in-nitride. The reason is that the dry etching method used has too little selectivity for the polystyrene-beads. This means that the semiconductor body can only be etched at a much slower rate than the beads. This is why the spheres used as etching masks have been wasted at an early point in the etching process (at this time only a small structural depth is etched into the surface of the semiconductor body). As a result, the ratio of the required etching depth to the structure width (rati0) cannot reach 0.25 to 5. This ratio is needed so that the 200419667 light can be effectively improved when emitted from the semiconductor body. SUMMARY OF THE INVENTION An object of the present invention is to provide a method for roughening the surface of a semiconductor body, which is suitable for use in many different materials. This objective is achieved by the method of the first patent application scope. Other advantageous forms of this method are described in the appended items of the scope of patent application. The basic idea of the present invention is to reduce the selectivity problem of the etching method used. In this case, in addition to the masking effect achieved by the polystyrene beads, another auxiliary mask is used. The material used to form the auxiliary mask is not only different from the material of the semiconductor body to be etched, but also different from the materials of the beads. With the help of the other mask, the etching process can be divided into two steps, in which the structures of the balls arranged on the surface in the first step are transferred to the auxiliary mask. In a second step, the structure of the auxiliary mask is transferred into the surface of the semiconductor body to be etched. Since in addition to each ball another material is also added as a mask, the material combination can be very selective, wherein each process can be targeted at the increased selectivity between the mask material and the material to be etched Be optimized. For example, an etching method may be formed, which is not suitable for a specific material combination formed by a small ball and a semiconductor body to be etched, but this method can be used for the first etching step according to the current two-step etching method. In addition, it is now also possible to etch the body to be roughened by a method which is not necessarily performed selectively on the small balls on the surface. Conversely, it is sufficient when the second etching step has high selectivity for the material of the auxiliary mask on the one hand and high selectivity for the body to be etched on the other hand. 200419667 Provides a method for roughening the surface of a body, which includes a step of T: In a first step, a surface of the body is coated with a masking layer. In the next step, a pre-formed mask body is applied on the mask layer. In the next step, the mask layer is etched and is performed at a position not covered by each mask body. In the next step, the body is etched on its surface at a location exposed by the mask layer. The advantage of this method is that by adding another etching mask, the etching process can be divided into two steps, one of which is an etching process (which is very selectively performed on the body relative to the pre-formed mask body). Etching) is no longer needed. Conversely, by changing the material of the mask body and the masking layer, a broad spectrum can be used in the possible etching methods, that is, a wider spectrum can be used in the etching method in the etching process. In one embodiment of the method, the body contains aluminum-gallium-in-phosphide (A1 G a I η P). Such semiconductor materials can be advantageously used in light emitting diodes emitting in the red spectral region or the blue spectral region. Such a semiconductor material is optionally deposited on silicon carbide or a gallium-arsenic-substrate. In another advantageous embodiment of the method, the body contains aluminum-gallium-in-nitride (A1 GainN). This material is also particularly suitable for use in luminescent diodes in the red spectral region or the blue spectral region. In one embodiment of the method, a masking layer is applied, which consists of a dielectric. Consider SlxNY (for example, Sl3N4, Slon, Sl02, Ai203) and similar materials as the dielectric. But other materials can also be used to cover the 200419667 overlay. What is important is that the material of the masking layer allows an etch process to selectively etch the mask body and the body allows a different etching process to selectively etch the mask layer. In one embodiment of the method, pellets made of polystyrene can be used in a shaped mask body. Due to their good chemical stability and the fact that the polystyrene-beads can be made in large pieces in a simple-and inexpensive device, these polystyrene-beads are particularly suitable for use in the above method as Mask body. Each masking body can be applied to the surface of the masking layer in a random configuration to be a single layer or a regular configuration. In an advantageous embodiment of the method, the etching step is performed by a dry etching method. For example, consider using reactive ion etching (RIE = Reactive Ion Etching), ion beam etching (IBE = Ion Beam Etching), and chemically-assisted ion beam etching (CAIBE ^ Chemical Assisted Ion Beam Etching) 0 For example, Consider using an inductively coupled plasma etching method (ICP = Inductive Coupled Plasma) as the dry uranium etching method. The advantage of the dry etching method in this method is that no fluid is required, which can improve the local stability of the mask body, because the flow phenomenon in the fluid will no longer occur. In an advantageous implementation form of the method, it is carried out in such a manner that the structures are maintained on the surface of the body, and the ratio of the width b of each structure to the etching depth t is: 0.1 < t / b < 10. 200419667 This method is preferably performed under the following conditions: 0.25 < t / b < 5. This ratio of depth to width is particularly advantageous in order to improve the scattering properties on the surface of the optical semiconductor crystal, and It also improves the emission of light from the crystal. The above-mentioned ratio of etching depth to width can be achieved by appropriately selecting the etching process and the size and material of the mask body.

在本方法之另一種形式中,直接在對該遮罩層進行蝕刻 之後去除該遮罩體。在另一種不同形式中,該遮罩體保留 在該遮層之表面上,以便在第二蝕刻過程中在該處可用作 另一蝕刻遮罩。在鈾刻過程結束之後去除該遮罩層,但該 遮罩層亦可保留在該本體之表面上。In another form of the method, the mask body is removed directly after the mask layer is etched. In another different form, the mask body remains on the surface of the mask so that it can be used there as another etching mask during the second etching process. The mask layer is removed after the uranium engraving process is completed, but the mask layer may remain on the surface of the body.

本方法可有利地使該本體中之蝕刻深度介於50和100 nir 之間。此種蝕刻深度可藉由下述方式來達成:使用一種蝕 刻過程,其在該遮罩層和待蝕刻之本體之間具有一種適當 之選擇性。此外,亦須適當地選取該蝕刻期間,以達成所 期望之深度。 上述方法中較佳是施加一種厚度介於1 〇和1 〇〇 nm之間之 遮罩層。此處一種最小厚度對該遮罩層是需要的,否則該 遮罩層即不能可靠地用作該本體之遮罩。但亦不能超過一 種指定之最大厚度,以便使該遮罩層之蝕刻期間所需之時 間保持在一種極限値中。 爲了達成上述之鈾刻深度對結構寬度之比,則有利的方 式是使用一種遮罩體,其在該遮罩層上之橫向尺寸介於150 -10- 200419667 和3 00 nm之間。 此處所述之方法在第一蝕刻步驟中可有利地使用一種過 程’其對該遮罩體和該待粗糙化之本體而言具有一種不良 之選擇性。因此隨後須考慮使用一種過程,其對該遮罩體 之鈾刻強度較對該待粗糙化之本體者還大,但這只限於以 下之情況:該蝕刻過程對該遮罩層又具有一種適當之選擇 性。 例如’該遮罩層之蝕刻可藉由一種反應性離子蝕刻所用 之設備來進行。 此處可有利地使用一種氟化過程,其中使用一由CHF3和 氬所構成之氣體混合物。此處通常使用一種具有平行板反 應器之標準RIE設備。 第二蝕刻步驟例如可藉由ICP-設備來進行,其中使用一 由CH4和H2所構成之混合物作爲蝕刻氣體。 此外,本發明亦提供一種光電組件,其具有半導體本體。 該半導體本體含有鋁-鎵-因-磷化物或鋁-鎵-因-氮化物。此 外,使該本體之表面被結構化,其中該結構之寬度相對於 該結構蝕刻時之各別深度須符合:0.25 < t/b < 5。此外,另 提供相同之組件,但該半導體本體含有鋁-鎵·因-氮化物以 取代鋁-鎵-因-磷化物。此種光電組件(例如,LED)可藉助於 以上所述之方法於第一次中製成。先前技術中已爲人所知 之方法不適合用來達成此處所述之t對b之比。 所謂”結構”之槪念是指:半導體本體蝕刻之後由其表面所 凸出之物。各結構之寬度例如可以是R. Windisch et al.所寫 200419667 文件 “40% Efficient Thin-Film Surface-Textured Light-Emitting Diodes by Optimization of Natural Lithography5,, IEEE Transactions on Electron Devices, Vol. 47, No, 7, 2000, pi 492- 1 498中所描述之圓柱或鐘樓之寬度。 【實施方式】 本發明以下將依據圖式中之實施來描述。This method advantageously enables the etch depth in the body to be between 50 and 100 nir. This etch depth can be achieved by using an etching process that has a suitable selectivity between the mask layer and the body to be etched. In addition, the etching period must be appropriately selected to achieve the desired depth. In the above method, it is preferable to apply a masking layer having a thickness between 10 and 100 nm. Here, a minimum thickness is required for the mask layer, otherwise the mask layer cannot be used reliably as a mask for the body. However, a specified maximum thickness cannot be exceeded in order to keep the time required for the masking layer during etching to a limit. In order to achieve the above-mentioned ratio of the uranium depth to the structure width, it is advantageous to use a mask body whose lateral dimension on the mask layer is between 150-10-200419667 and 300 nm. The method described here can advantageously use a process' in the first etching step, which has a poor selectivity for the mask body and the body to be roughened. Therefore, it is necessary to consider the use of a process whose uranium engraving strength to the mask body is greater than that to the roughened body, but this is limited to the following cases: the etching process has a suitable Of selectivity. For example, the masking layer can be etched by a device used for reactive ion etching. A fluorination process can advantageously be used here, in which a gas mixture of CHF3 and argon is used. A standard RIE device with a parallel plate reactor is usually used here. The second etching step can be performed by, for example, an ICP-equipment in which a mixture of CH4 and H2 is used as an etching gas. In addition, the present invention also provides a photovoltaic module having a semiconductor body. The semiconductor body contains aluminum-gallium-in-phosphide or aluminum-gallium-in-nitride. In addition, the surface of the body is structured, wherein the width of the structure relative to the respective depth of the structure during etching must conform to: 0.25 < t / b < 5. In addition, the same component is provided, but the semiconductor body contains aluminum-gallium-in-nitride instead of aluminum-gallium-in-phosphide. Such a photovoltaic module (e.g., an LED) can be manufactured in the first time by the method described above. Methods known in the prior art are not suitable for achieving the ratio of t to b described herein. The so-called "structure" refers to what protrudes from the surface of a semiconductor body after etching. The width of each structure can be, for example, the 200419667 file "40% Efficient Thin-Film Surface-Textured Light-Emitting Diodes by Optimization of Natural Lithography5, IEEE, on Electron Devices, Vol. 47, No, written by R. Windisch et al. 7, 2000, pi 492-1 1 498 The width of a cylinder or a bell tower. [Embodiment] The present invention will be described below based on the implementation in the drawings.

此處須指出:第1至第4圖都表不一種橫切面。此外’相 同之參考符號表示相同之元件或至少是具有相同-或類似功 能之元件。 第1圖顯示一種本體1,其例如可以是一種半導體本體。 在該本體1之表面上施加一種遮罩層2。該遮罩層2可有利 地具有一種厚度d,其介於10和100 nm之間。 在該遮罩層2上施加一遮罩體3,其在此處所考慮之特殊 情況中一方面形成一種單層且另一方面具有小球之形式。 各小球之橫向尺寸A因此介於150和300 nm之間。但亦可 使用其它形式之具有其它適當材料之遮罩體。It must be pointed out here: Figures 1 to 4 do not represent a cross section. In addition, the same reference symbols indicate the same elements or at least elements having the same-or similar functions. FIG. 1 shows a body 1, which can be, for example, a semiconductor body. A masking layer 2 is applied on the surface of the body 1. The masking layer 2 can advantageously have a thickness d between 10 and 100 nm. A masking body 3 is applied to the masking layer 2, which in the special case considered here forms on the one hand a single layer and on the other hand has the form of small balls. The lateral dimension A of each sphere is therefore between 150 and 300 nm. However, other forms of mask bodies with other suitable materials may be used.

第2圖中顯示:第一蝕刻步驟之後第1圖之配置狀態。該 遮罩層2是處於由該遮罩體3所覆蓋之狀態中時被蝕刻。 因此可形成一種已穿孔之遮罩層2,其中在該遮罩層2之表 面上通常仍配置著該遮罩體3。但該遮罩體3藉由通常不可 避免之蝕刻而使體積較第1圖者還小。這由以下事實所造 成:該遮罩層2蝕刻時所用之幾乎全部之蝕刻方法通常亦 會對該遮罩體3進行蝕刻,即使其只在一種很小之範圍中 時亦然。 -12- 200419667 然後使該遮罩層2表面上之遮罩體3被去除。但此步騾未 必需要’反之’亦可使該遮罩體3保留在該遮罩層2表面 上。 第3圖顯示第1圖之配置狀態,但其中已進行第二鈾刻步 驟。追表示:該本體1之表面已具有結構4。在結構4之表 面上仍保持著該遮罩層2之殘餘部份。Fig. 2 shows the arrangement state of Fig. 1 after the first etching step. The mask layer 2 is etched when it is in a state covered by the mask body 3. Therefore, a perforated masking layer 2 can be formed, wherein the masking body 3 is usually still disposed on the surface of the masking layer 2. However, the volume of the mask body 3 is smaller than that of the first figure by the unavoidable etching. This is caused by the fact that almost all of the etching methods used when the mask layer 2 is etched will usually etch the mask body 3 even if it is only in a small range. -12- 200419667 Then the mask body 3 on the surface of the mask layer 2 is removed. However, this step does not necessarily require 'conversely', so that the mask body 3 remains on the surface of the mask layer 2. Figure 3 shows the configuration of Figure 1, but a second uranium engraving step has been performed. The following indicates that the surface of the body 1 has a structure 4 already. The remainder of the masking layer 2 remains on the surface of the structure 4.

第4圖顯示:第3圖中去除該遮罩層2之後之配置狀態。 所造成之結構4之寬度b對該蝕刻深度t之比須符合以下之 條件= 0.25 < t/b < 5. 各結構4例如可具有圓柱形鐘樓之形式。 各結構4例如可規則性地沿著一種在前沿陣列中由該遮 罩體3之配置所界定之網目來定位。但各結構4亦可隨機 性地分佈在該本體1之表面上。 【圖式簡單說明】 第1圖一種待蝕刻之本體,其上施加一種遮罩層和遮罩FIG. 4 shows the arrangement state after removing the mask layer 2 in FIG. 3. The ratio of the width b of the structure 4 to the etching depth t must meet the following conditions = 0.25 < t / b < 5. Each structure 4 may have the form of a cylindrical bell tower, for example. Each structure 4 can be positioned regularly, for example, along a mesh defined by the configuration of the mask body 3 in the leading edge array. However, the structures 4 can also be randomly distributed on the surface of the body 1. [Schematic description] Figure 1 A body to be etched, with a masking layer and mask applied to it

mm 體。 第2圖第一蝕刻步驟之後第1圖之本體。 第3圖第二蝕刻步驟之後第2圖之本體。 第4圖該遮罩層去除之後第3圖之本體。 主要元件之符號表: 1 本體 2 遮罩層 3 遮罩體 -13- 200419667 4 結 構 A 橫 向尺寸 b 寬 度 d 厚 度 t 深 度mm body. Figure 2 is the body of Figure 1 after the first etching step. Figure 3 is the body of Figure 2 after the second etching step. Fig. 4 The body of Fig. 3 after the mask layer is removed. Symbol table of main components: 1 body 2 mask layer 3 mask body -13- 200419667 4 structure A horizontal dimension b width d thickness t depth

-14--14-

Claims (1)

200419667 拾、申請專利範圍: 1. 一種使半導體本體(1)之表面粗糙化所用之方法,其特徵 爲以下之各步驟: a) 使表面塗佈一種遮罩層(2), b) 施加一種已預成形之遮罩體(3)於該遮罩層(2)上, c) 在未由該遮罩體(3)所覆蓋之位置上對該遮罩層(2)進 行鈾刻,200419667 Patent application scope: 1. A method for roughening the surface of the semiconductor body (1), which is characterized by the following steps: a) coating the surface with a masking layer (2), b) applying a The pre-formed mask body (3) is on the mask layer (2), c) the mask layer (2) is engraved with uranium at a position not covered by the mask body (3), d)在其表面之無該遮罩層(2)之位置上對該本體(1)進行 蝕亥!J。 2.如申請專利範圍第1項之方法,其中該本體(1)含有鋁-鎵_ 因-磷化物。 3.如申請專利範圍第1項之方法,其中該本體(1)含有鋁_鎵_ 因-氦化物。 4.如申g靑專利軔圍弟1至3項中任一項之方法,其中該遮罩 層(2)由介電質所形成。 5 ·如申請專利軔S弟1至4項中任一項之方法,其中使用該d) Etching the body (1) on the surface of the body without the mask layer (2)! J. 2. The method according to item 1 of the patent application scope, wherein the body (1) contains aluminum-gallium-in-phosphide. 3. The method of claim 1, wherein the body (1) contains aluminum_gallium_in-helium. 4. The method according to any one of items 1 to 3 of the patent application, wherein the mask layer (2) is formed of a dielectric. 5 · Method for applying any one of patents 1 to 4 in which 由聚苯乙烯所構成之小球作爲已預成形之遮罩體(3)。 6 ·如申請專利範圍第1至5項中任一項之方法,其中藉由一 乾蝕刻方法來進行該蝕刻步驟。 7 ·如申g靑專利範S弟1至6項中任一項之方法,其中進行本 方法,使各結構(4)保留在該本體(1)之表面中,各結構之 寬度(b)對該蝕刻深度⑴之比須符合: 0.1 < t/b < 10. 8 ·如申請專利範圍第1至7項中任一項之方法,其中進行本 -15- 200419667 方法,使各結構(4 )保留在該本體(1 )之表面中,各結構之 寬度(b )對該蝕刻深度(t)之比須符合: 0.25 < t/b < 5. 9 ·如申請專利範圍第1至8項中任一項之方法,其中直接在 步驟c)之後使該遮罩體(3 )之殘餘部份由該遮罩層(2)中去 除。 1 0 ·如申請專利範圍第1至9項中任一項之方法,其中該本 體(1)中之蝕刻深度⑴介於50和100 nm之間。A small ball made of polystyrene is used as a pre-formed mask body (3). 6. The method according to any one of claims 1 to 5, wherein the etching step is performed by a dry etching method. 7 · The method of any one of items 1 to 6 of the patent application, such as applying the method so that each structure (4) remains in the surface of the body (1), and the width (b) of each structure The ratio of the etching depth ⑴ must conform to: 0.1 < t / b < 10. 8 · If the method of any one of claims 1 to 7 is applied, the method of this -15-200419667 is performed to make each structure (4) Remaining on the surface of the body (1), the ratio of the width of each structure (b) to the depth of etching (t) must conform to: 0.25 < t / b < 5. 9 The method of any one of items 1 to 8, wherein the remaining portion of the mask body (3) is removed from the mask layer (2) directly after step c). 1 0. The method according to any one of claims 1 to 9, wherein the etching depth ⑴ in the body (1) is between 50 and 100 nm. 1 1.如申請專利範圍第1至1 〇項中任一項之方法,其中施加 •—種遮罩層(2),其厚度(d)介於10和100 nm之間。 12.如申請專利範圍第1至11項中任一項之方法,其中該遮 罩層(2)上之遮罩體(3)具有一種橫向尺寸(A),其介於150 和3 0 0 n m之間。 1 3.如申請專利範圍第1至1 2項中任一項之方法,其中第一 蝕刻步驟藉由一種對該遮罩體(3)之鈾刻強度較對該本體 (1)者還大之過程來進行。1 1. The method according to any one of claims 1 to 10 of the scope of patent application, wherein a masking layer (2) is applied, and a thickness (d) thereof is between 10 and 100 nm. 12. The method according to any one of claims 1 to 11, wherein the mask body (3) on the mask layer (2) has a lateral dimension (A) between 150 and 3 0 0 nm. 1 3. The method according to any one of claims 1 to 12 in the scope of patent application, wherein the first etching step uses a uranium engraving strength of the mask body (3) to be greater than that of the body (1). Process. 1 4.如申請專利範圍第1至1 3項中任一項之方法,其中該遮 罩層(2)之蝕刻是藉由一種反應性離子鈾刻用之設備來進 行。 1 5 .如申請專利範圍第1 4項之方法,其中使用一由CHF3和 Ar所構成之混合物作爲蝕刻氣體。 1 6.如申請專利範圍第1至1 5項中任一項之方法,其中該本 體(1)之蝕刻是藉由一種適用於感應性耦合電漿之設備來 進行。 -16 - 200419667 17.如申請專利範圍第16項之方法,其中使用一由CH4和Ή, 所構成之混合物作爲蝕刻氣體。 18·—種光電組件,其包含一種半導體本體,該半導體本濟 含有鋁-鎵-因-磷化物且其表面被結構化,其特徵爲:各結 構(4)之寬度(b)對各結構(4)之鈾刻深度(t)之比須符合: 0.25 < t/b < 5. 19. 一種光電組件,其包含一種半導體本體,該半導體本體 含有銘-鎵-因-氮化物且其表面被結構化,其特徵爲:各結14. The method according to any one of claims 1 to 13 of the scope of patent application, wherein the etching of the masking layer (2) is performed by a reactive ion engraving equipment. 15. The method according to item 14 of the scope of patent application, wherein a mixture of CHF3 and Ar is used as an etching gas. 16. The method according to any one of claims 1 to 15 of the scope of patent application, wherein the etching of the body (1) is performed by a device suitable for inductively coupled plasma. -16-200419667 17. The method according to item 16 of the patent application, wherein a mixture of CH4 and thorium is used as an etching gas. 18 · —A photovoltaic module comprising a semiconductor body containing a semiconductor-aluminum-gallium-caustic-phosphide and a structured surface, characterized in that the width (b) of each structure (4) and each structure (4) The ratio of the uranium engraved depth (t) must meet: 0.25 < t / b < 5. 19. A photovoltaic module comprising a semiconductor body containing an indium-gallium-in-nitride and Its surface is structured and is characterized by: 構(4)之寬度(b)對各結構(4)之蝕刻深度⑴之比須符合: 0.25 < t/b < 5.The ratio of the width (b) of the structures (4) to the etching depth ⑴ of each structure (4) must meet: 0.25 < t / b < 5. -17--17-
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DE102009008223A1 (en) 2009-02-10 2010-08-12 Osram Opto Semiconductors Gmbh Method for structuring a semiconductor surface and semiconductor chip
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US5676853A (en) * 1996-05-21 1997-10-14 Micron Display Technology, Inc. Mask for forming features on a semiconductor substrate and a method for forming the mask
US6074888A (en) * 1998-08-18 2000-06-13 Trw Inc. Method for fabricating semiconductor micro epi-optical components
US6228538B1 (en) * 1998-08-28 2001-05-08 Micron Technology, Inc. Mask forming methods and field emission display emitter mask forming methods
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