TW200423273A - Fixture for die-pull test - Google Patents
Fixture for die-pull test Download PDFInfo
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- TW200423273A TW200423273A TW92109182A TW92109182A TW200423273A TW 200423273 A TW200423273 A TW 200423273A TW 92109182 A TW92109182 A TW 92109182A TW 92109182 A TW92109182 A TW 92109182A TW 200423273 A TW200423273 A TW 200423273A
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- platform
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- bump
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- 238000012360 testing method Methods 0.000 title claims abstract description 77
- 239000000758 substrate Substances 0.000 claims abstract description 56
- 239000004065 semiconductor Substances 0.000 claims description 28
- 238000009864 tensile test Methods 0.000 claims description 21
- 238000000034 method Methods 0.000 claims description 16
- 239000012790 adhesive layer Substances 0.000 claims description 13
- 238000005516 engineering process Methods 0.000 claims description 7
- 238000004154 testing of material Methods 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 4
- 230000003287 optical effect Effects 0.000 claims description 4
- 238000006073 displacement reaction Methods 0.000 claims description 3
- 239000010410 layer Substances 0.000 claims description 3
- 229910000831 Steel Inorganic materials 0.000 claims description 2
- 239000010959 steel Substances 0.000 claims description 2
- 235000012431 wafers Nutrition 0.000 claims 32
- 238000004806 packaging method and process Methods 0.000 claims 1
- 239000013078 crystal Substances 0.000 description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000005272 metallurgy Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- JOCBASBOOFNAJA-UHFFFAOYSA-N N-tris(hydroxymethyl)methyl-2-aminoethanesulfonic acid Chemical compound OCC(CO)(CO)NCCS(O)(=O)=O JOCBASBOOFNAJA-UHFFFAOYSA-N 0.000 description 1
- 241001122767 Theaceae Species 0.000 description 1
- 238000007792 addition Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 230000001050 lubricating effect Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000010008 shearing Methods 0.000 description 1
- 239000002689 soil Substances 0.000 description 1
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- Investigating Strength Of Materials By Application Of Mechanical Stress (AREA)
Abstract
Description
200423273 五、發明說明(1) 【發明所屬之技術領域】 本發明係有關於一種覆晶封裝構造之晶片凸塊拉力、、 試之治具(fixture for die-pull test),更特別係有;則 於一種覆晶封裝構造之面固定(face_fixed)之晶只 f200423273 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a wafer bump pulling force of a flip-chip package structure, and a fixture for die-pull test. Then the surface-fixed crystal of a flip-chip package structure is only f
^ ° % iiL 力測試之治具。 【先前技術】 一般而言’覆晶封裝構造(Flip Chip Package)包含 一基板、一晶片利用覆晶技術安裝於該基板、以及銲錫戈 金凸塊(solder or gold bump)用以將該晶片電性連接至 該基板。一填膠(underf i 1 1 )可另填充於該晶片與基板 間’錯以包封遠基板、該晶片及該凸塊。為了解覆晶接人 之可靠度,故需要進行晶片凸塊拉力測試(die pui i " test ) 〇 參考第1圖,其顯示先前技術之一晶片凸塊拉力測試 之治具1 8,一覆晶封裝構造1 5係穩固的固定於其上。該覆 晶封裝構造15具有一基板14及一晶片12藉由凸塊16配置^ 该基板1 4上。該晶片凸塊拉力測試之治具1 8具有兩凹挿 2 0 ’用以夾住該基板1 4之兩側。一黏著層2 4係塗覆於該雙 曰曰封裝構造1 5之該晶片1 2上’將該晶片1 2黏著至一萬能材 料試驗機(Universal testing machine)(圖中未示)之— 測試頭(T e s t i n g H e a d 〇 r J i g) 2 2 上。 卜、 參考第2圖,於該測試過程中,該測試頭2 2係為該全 月b材料试驗機向上驅動’措以對該晶片1 2向上施加作用 力。隨著該測試頭22向上移動,該晶片及該基板間之結^ °% iiL fixture for force test. [Previous technology] Generally, a Flip Chip Package includes a substrate, a wafer mounted on the substrate using flip-chip technology, and a solder or gold bump to electrically connect the chip. To the substrate. An underfill i 1 1) can be additionally filled between the wafer and the substrate 'to encapsulate the far substrate, the wafer and the bump. In order to understand the reliability of chip-on-chip access, a die bump pull test (die pui i " test) is required. ○ Refer to Figure 1, which shows a jig for a wafer bump pull test, one of the prior art. The flip-chip package structure 15 is firmly fixed on it. The flip-chip package structure 15 has a substrate 14 and a wafer 12 arranged on the substrate 14 through bumps 16. The jig 18 for the wafer bump tensile test has two concave insertions 20 'for clamping both sides of the substrate 14. An adhesive layer 2 4 is coated on the wafer 12 of the double-package structure 15, and the wafer 12 is adhered to a universal testing machine (not shown) — test Head (Testing H ead 〇r J ig) 2 2. B. Referring to FIG. 2, during the test, the test head 22 is driven upwards for the whole month b material testing machine to apply an upward force to the wafer 12. As the test head 22 moves upward, the junction between the wafer and the substrate
200423273 五、發明說明(2) 構,諸如該凸塊16及凸塊下金屬層(Under Bump200423273 V. Description of the invention (2) structure, such as the bump 16 and the metal layer under the bump (Under Bump
Metallurgy ;UBM)(圖中未示)承受拉伸應力(tensUe stress)而變形,且進一步斷裂,使得該晶片12與該基板 1 4分離。 然而,前述之該晶片凸塊拉力測試之治具丨8僅僅固定 該基板1 4的邊緣,因此當該基板丨4係為一撓性基板,諸如 FR-4及BT樹脂基板時,於測試過程中,該基板14會產生彎 曲。於此情^下,該凸塊16將不僅承受正向的拉伸應力, 同時亦承受剪應力(shearing stress)。再者,該基板14 的青曲亦造成應力集中於該凸塊1 6中之外圍凸塊上。因 此,此一測試過程中所獲得的數據,係大幅度的低於該基 板1 4與該晶片1 2實際可承受之正向作用力。 再者,於此一配置下,測試或斷裂後之該基板丨4及該 晶片12係固定於該治具18上,且通常會藉由光學顯微鏡 (optical microscope ;〇M)或電子顯微鏡(scanning electron microscope ;SEM)觀察該凸塊16之破壞模式 (failure mode)。然而,該治具18之可運作之高度往往盔 法與該光學顯微鏡或電子顯微鏡相配合,而無法進行破獲 模式之觀察。 & 有鑑於此,便有需供一種晶片凸塊拉力測試之治具, 用以克服前述的問題。 r'、、- 【發明内容】 本發明之一目的在於提供一種晶片凸塊拉力測試之治 具,以面固定的方式,對半導體封裝構造施力,藉以正確Metallurgy (UBM) (not shown) undergoes tensile stress (tensUe stress) to deform and further break, so that the wafer 12 is separated from the substrate 14. However, the aforementioned jig for testing the tensile strength of the wafer bump 8 only fixes the edge of the substrate 14, so when the substrate 4 is a flexible substrate such as FR-4 and BT resin substrate, the test process In this case, the substrate 14 is bent. In this case, the bump 16 will not only bear the tensile stress in the forward direction, but also the shearing stress. Furthermore, the blue curve of the substrate 14 also causes stress to be concentrated on the peripheral bumps in the bumps 16. Therefore, the data obtained during this test are significantly lower than the actual forward force that the substrate 14 and the wafer 12 can withstand. Moreover, in this configuration, the substrate 4 and the wafer 12 after being tested or broken are fixed on the jig 18, and usually through an optical microscope (OM) or an electron microscope (scanning) electron microscope (SEM) observe the failure mode of the bump 16. However, the operable height of the jig 18 is often matched with the optical microscope or the electron microscope, and observation of the cracking mode cannot be performed. In view of this, there is a need for a jig for a wafer bump tensile test to overcome the foregoing problems. r ',,-[Summary of the invention] An object of the present invention is to provide a jig for testing the tensile strength of a wafer bump, which applies a force to a semiconductor package structure in a surface-fixed manner so as to be correct.
第7頁 200423273 五、發明說明(3) 的量測該半導體覆晶封裝構造之抗拉強度。 為達上述目的,本發明提供一種治具,應用於一覆晶 封裝構造之晶片凸塊拉力測試。該晶片凸塊拉力測試之治 具包含一第一平台及一第二平台。該第一平台係面固定的 支撐該覆晶封裝構造之該基板。該第二平台係面固定的支 樓该覆aa封叙構造之該半導體晶片,並與一外部之萬能材 料试驗機(U n i v e r s a 1 t e s t i n g m a c h i n e )之一測試頭相連 接。 根據本發明之該晶片凸塊拉力測試之治具,其係藉由 兩平台,面固定地支撐該半導體封裝構造之基板及半導體 晶片。該覆晶封裝構造之基板以及半導體晶片係以整個表 面固定於该平台上。因此,於測試過程中,該基板將不致 於產生彎曲或變形,而影響測試的結果。 為了讓本發明之上述和其他目的、特徵、和優點能更 明顯’下文特舉本發明較佳實施例,並配合所附圖示,作 詳細說明如下。 【實施方式】 現w寥考第3圖,其顯示根據本發明之一晶片凸塊拉 力測试之治具5 0 ’用以對一覆晶封裝構造5 5進行晶片凸塊 拉力測f。該覆晶封裝構造55具有一基板54及一半導體晶 片52,藉由覆晶技術連接於該基板54上。 d 4 sa片凸塊拉力測試之治具5 〇包括一托架5 8以及一1〜 定平台6 0。該晶片凸塊拉力測試之治具5 〇另包括一測試平 台64 ’與一萬能材料試驗機之一測試頭(Testing Head orPage 7 200423273 V. Description of the invention (3) Measure the tensile strength of the semiconductor flip-chip package structure. To achieve the above object, the present invention provides a jig, which is applied to a wafer bump tensile test of a flip-chip package structure. The jig for pulling the wafer bump includes a first platform and a second platform. The first platform is fixedly supporting the substrate of the flip-chip package structure. The second platform is connected to the semiconductor wafer of the aa sealed structure of the fixed building, and is connected to a test head of an external universal material testing machine (U n i v e r s a 1 t e s t i n g m a c h i n e). According to the jig for testing the tensile strength of the wafer bump according to the present invention, the semiconductor package structure substrate and the semiconductor wafer are fixedly supported by two platforms. The substrate and semiconductor wafer of the flip-chip package structure are fixed on the platform with the entire surface. Therefore, during the test, the substrate will not be bent or deformed, which will affect the test results. In order to make the above and other objects, features, and advantages of the present invention more obvious, the preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, as follows. [Embodiment] Now referring to Fig. 3, it shows a jig 50 'for a wafer bump tensile test according to the present invention, which is used to perform a wafer bump tensile test f on a flip-chip package structure 55. The flip-chip package structure 55 has a substrate 54 and a semiconductor wafer 52, and is connected to the substrate 54 by a flip-chip technology. The d 4 sa jig tensile test fixture 50 includes a bracket 5 8 and a 1 to 6 fixed platform. The jig for testing the tensile strength of the wafer bump 5 includes a testing platform 64 ′ and a testing head for one of the universal material testing machines.
042.ptd 第8頁042.ptd Page 8
200423273 五、發明說明(4) J i g) 6 2相連接。兩薄板7 〇、7 2係可藉由諸如螺栓之類的固 定件(圖中未示)或諸如滑槽等固定裝置,分別固定於該托 架5 8及该固定平台6 〇上。該薄板7 0、7 2係由剛性的材料所 製造’諸如鋼(steel)。 一黏著層68係塗覆於該薄板72上,用以將該覆晶封裝 構造5 5之該基板5 4黏著於該薄板7 2上,如此使得該基板5 4 能夠加裝於該固定平台6 0上。一黏著層6 6係塗覆於該薄板 7 0上’用以將該覆晶封裝構造5 5之該半導體晶片5 2黏著於 該薄板7 0上,如此使得該半導體晶片5 2能夠加裝於該測試 平台64上。200423273 V. Description of the invention (4) J i g) 6 2 phase connection. The two thin plates 70 and 72 can be fixed to the bracket 5 8 and the fixed platform 60 respectively by a fixing member (not shown) such as a bolt or a fixing device such as a chute. The thin plates 70, 72 are made of a rigid material, such as steel. An adhesive layer 68 is coated on the thin plate 72 to adhere the substrate 5 4 of the flip-chip package structure 5 5 to the thin plate 72, so that the substrate 5 4 can be mounted on the fixed platform 6. 0 on. An adhesive layer 6 6 is coated on the thin plate 70. The semiconductor wafer 5 2 is used to adhere the flip-chip package structure 5 5 to the thin plate 70. In this way, the semiconductor wafer 52 can be mounted on the thin plate 70. The test platform 64.
參考第4圖,於該測試過程中,該測試頭6 2係為該萬 能材料試驗機向上驅動,藉以對該晶片5 2向上施加作用 力。隨著該測試頭62向上移動,該晶片52及該基板54間之 元件’諸如複數個鐸錫或金凸塊(solder bump or gold bump)56 及凸塊下金屬層(Under Bump Metallurgy ;UBM )(圖中未示),承受拉伸應力(tensile stress)而變形, 且進一步斷裂,使得該晶片5 2與該基板5 4分離。於該測試 過程中,該測試頭6 2之位移量及作用力會被記錄,而完成 晶片凸塊拉力測試。 卜. 再者,於此一配置下,分離後之該晶片52與該基板If 仍舊藉由該黏著層6 6及該黏著層6 8,分別黏著於該該薄板 70及該薄板72上。該基板54及該晶片52可與該薄板70及該 薄板7 2 ’ 一併放置於光學顯微鏡(〇 p t i c a 1 microscope ; 0M)或電子顯微鏡(scanning electron microscope ;SEM)Referring to FIG. 4, during the test, the test head 62 is driven upwards by the universal material testing machine, so as to apply upward force to the wafer 52. As the test head 62 moves upward, the components between the wafer 52 and the substrate 54 such as a plurality of solder bumps or gold bumps 56 and an under bump metallurgy (UBM) (Not shown in the figure), undergoes tensile stress and deforms, and further breaks, so that the wafer 52 is separated from the substrate 54. During the test, the displacement and force of the test head 62 will be recorded, and the wafer bump tensile test is completed. In addition, in this configuration, the separated wafer 52 and the substrate If are still adhered to the thin plate 70 and the thin plate 72 through the adhesive layer 66 and the adhesive layer 68 respectively. The substrate 54 and the wafer 52 can be placed together with the thin plate 70 and the thin plate 7 2 ′ in an optical microscope (〇 p t i c a 1 microscope; 0M) or an scanning electron microscope (SEM).
'’齒42.pt d 第9頁 200423273 五、發明說明(5) 中 觀察σ亥復晶封裝構造5 5之破壞模式(f a i 1 u r e m 〇 d e )。 現請茶考第5及6圖,其顯示根據本發明之另一實施例 之一晶片凸塊拉力洌試之治具8 0,用以對一覆晶封裝構造 85進行晶片凸塊拉力測試。該晶片凸塊拉力測試之治具8〇 係與該晶片凸塊拉力測試之治具50相類似,其中類似的元 件標示類似的圖號。 该晶片凸塊拉力測試之治具8 〇包括一固定吸盤9 〇,具 有複數個通道98與一外部真空源(圖中未示)相連接,用以 將該覆晶封裝構造85之該基板84吸著於該固定吸盤9〇其 吕豕日日片凸塊拉 與一萬能材料試驗 J i g ) 9 2相連接。該 真空源(圖中未示) &體晶片82吸著於 綜前所述,於 中’覆晶封装構造 之基板以及半導體 盤上。因此,於測 變形,而影響測試 台及該覆晶封裝構 黏著層及吸盤所限 力測试之治具8 〇另包括一測試吸 機之一測試頭(Testing Head or 測試吸盤94具有複數個通道96與 相連接’用以將覆晶封裝構造85 該測試吸盤9 4上。 本發明之該晶片凸塊拉力測試之 ,面,固定”的。亦即,該覆晶封 ,片係以整個”表面固定’,於該平 戈j程中’該基板將不致於產生 土、、果 才月於本技藝者將可瞭解 仏間之面固定的方式並不以前所 盤94 一外部 之該半 治具 裝構造 台或吸 彎曲或 ’該平 所述之'Tooth 42.pt d p. 9 200423273 V. In the description of the invention (5), observe the failure mode (f a i 1 u r e m 〇 d e) of the σ hai complex structure 5 5. 5 and 6 of the tea test are shown, which show a jig 80 for a wafer bump pull test according to another embodiment of the present invention, which is used to perform a wafer bump pull test on a flip-chip package structure 85. The jig 80 of the wafer bump tensile test is similar to the jig 50 of the wafer bump tensile test, and similar elements are marked with similar drawing numbers. The jig 8 of the wafer bump tensile test includes a fixed suction cup 90, having a plurality of channels 98 connected to an external vacuum source (not shown in the figure) for the substrate 84 of the flip-chip package structure 85. The lubricating lugs of the fixed sucker 90 and the lugs of the sun-chips are pulled and connected to a universal material test J ig) 92. The vacuum source (not shown in the figure) & the body wafer 82 is attracted to the substrate and semiconductor disk of the chip-on-chip package structure as described above. Therefore, the deformation that affects the limit test of the test bench, the bonding layer of the flip chip package, and the suction cup 8 also includes a test head (Testing Head or Test Sucker 94 having a plurality of test heads). The channel 96 is connected to the phase for mounting the flip-chip package structure 85 on the test chuck 94. The pull-test of the wafer bump of the present invention is tested on the surface and fixed. "The surface is fixed", in the course of the Pingge process, "the substrate will not produce soil, and the fruit will be able to be understood by the artist. The method of fixing the surface of the chamber is not the one previously described. Equipped with a construction table or suction bend or 'the flat said
雖然前述的描述及圖示已揭 瞭解到各種增添、修改和取 必須 Γ-Ν 示本發明之較佳實施例 代可能使用於本發明較佳Although the foregoing descriptions and illustrations have been disclosed, various additions, modifications, and selections must be understood. Γ-N shows a preferred embodiment of the present invention, and may be used in the present invention.
200423273 五、發明說明(6) 實施例,而不會脫離如所附申請專利範圍所界定的本發明 原理之精神及範圍。熟悉該技藝者將可體會本發明可能使 用於很多形式、結構、佈置、比例、材料、元件和組件的 修改。因此,本文於此所揭示的實施例於所有觀點,應被 視為用以說明本發明,而非用以限制本發明。本發明的範 圍應由後附申請專利範圍所界定,並涵蓋其合法均等物, 並不限於先前的描述。200423273 V. Description of the invention (6) Examples without departing from the spirit and scope of the principle of the invention as defined by the scope of the attached patent application. Those skilled in the art will appreciate that the present invention may be modified for many forms, structures, arrangements, proportions, materials, elements and components. Therefore, the embodiments disclosed herein should, in all respects, be considered to illustrate the present invention, rather than to limit the present invention. The scope of the present invention should be defined by the scope of the appended patents and the legal equivalents thereof, and is not limited to the previous description.
®2.ptd 第 11 頁 200423273 圖式簡單說明 【圖式簡單說明】 第1圖:係先前技術之晶片凸塊拉力測試之治具之侧面示 意圖。 第2圖:係先前技術之晶片凸塊拉力測試之治具,於測試 過程中之側面示意圖。 第3圖:係為根據本發明之一實施例之一晶片凸塊拉力測 試之治具之側面示意圖。 第4圖:係為第3圖中之該晶片凸塊拉力測試之治具,於測 試過程中之側面示意圖。 圖 力 拉 塊 凸 片 晶 一 之 例 施 實 1 另 之 明 發 本 據 根 為 係 圖 意 示 面 側 之 具 治 之 丨試 第測 第 為 係 圖 測 於 具 治 之 試 測 力 拉 塊 凸 片 晶 該。 之圖 中意 圖示 面 側 之 中 程 ί過 第試 片槽 日Ba凹 2 ο 11 0/W 具 治 之 試 測 力造 拉構 塊裝 凸封 :片晶板塊 明晶覆基凸 說 ^ 8 5 4 6 口 3 1X 11 1X 11 圖®2.ptd Page 11 200423273 Brief description of the drawings [Simplified description of the drawings] Figure 1: The side view of the jig for the wafer bump tensile test of the prior art. Figure 2: This is a side view of the jig for the wafer bump tensile test of the prior art during the test. FIG. 3 is a schematic side view of a jig for a wafer bump tensile test according to an embodiment of the present invention. Fig. 4 is a schematic side view of the jig for the wafer bump tensile test in Fig. 3 during the test. Tuli pull block lug crystal one example of implementation 1 Another Mingfa root is based on the schematic side of the schematic diagram 丨 test the first test is based on the test of the pull pull tab crystal That. In the figure, the middle side of the test piece is shown through the concave groove of the test piece 2 Ba ο 11 0 / W The tensile force of the test piece with convex force is used to build a convex seal: the plate crystal plate is clear and the crystal base is convex ^ 8 5 4 6 port 3 1X 11 1X 11 Figure
0tf642.ptd 第12頁 2004232730tf642.ptd Page 12 200423273
^2.ptd 第 13 頁 圖式簡單說明 24 黏 著 層 22 測 言式 頭 50 晶 片 凸 塊 拉 力 測 試之 治 具 52 半 導 體 晶 片 54 基 板 55 覆 晶 封 裝 構 造 56 凸 塊 58 托 架 60 固 定 平 台 62 測 試 頭 64 測 試 平 台 66 黏 著 層 68 黏 著 層 70 薄 板 72 薄 板 80 晶 片 凸 塊 拉 力 測 試之 治 具 82 半 導 體 晶 片 84 基 板 85 覆 晶 封 裝 構 造 86 凸 塊 88 托 架 90 固 定 吸 盤 92 測 試 頭 94 測 試 吸 盤 96 通 道 98 通 道^ 2.ptd Page 13 Brief description of drawings 24 Adhesive layer 22 Test head 50 Jig for wafer bump tensile test 52 Semiconductor wafer 54 Substrate 55 Flip-chip package structure 56 Bump 58 Bracket 60 Fixed platform 62 Test head 64 Test platform 66 Adhesive layer 68 Adhesive layer 70 Thin plate 72 Thin plate 80 Jig for wafer bump tensile test 82 Semiconductor wafer 84 Substrate 85 Chip-on-chip package structure 86 Bump 88 Bracket 90 Fixed suction cup 92 Test head 94 Test suction cup 96 Channel 98 aisle
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW92109182A TW582083B (en) | 2003-04-17 | 2003-04-17 | Fixture for die-pull test |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW92109182A TW582083B (en) | 2003-04-17 | 2003-04-17 | Fixture for die-pull test |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW582083B TW582083B (en) | 2004-04-01 |
| TW200423273A true TW200423273A (en) | 2004-11-01 |
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| TW92109182A TW582083B (en) | 2003-04-17 | 2003-04-17 | Fixture for die-pull test |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108666298A (en) * | 2017-03-27 | 2018-10-16 | 中芯国际集成电路制造(北京)有限公司 | Die stress test suite and preparation method thereof |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI447376B (en) * | 2011-05-10 | 2014-08-01 | Au Optronics Corp | Method for measuring sealant strength of lcd panel and measuring apparatus thereof |
| TWI642133B (en) * | 2016-10-20 | 2018-11-21 | Siliconware Precision Industries Co., Ltd. | Mounting process for electronic component placement and its application |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108666298A (en) * | 2017-03-27 | 2018-10-16 | 中芯国际集成电路制造(北京)有限公司 | Die stress test suite and preparation method thereof |
| CN108666298B (en) * | 2017-03-27 | 2019-12-10 | 中芯国际集成电路制造(北京)有限公司 | Chip stress testing assembly and preparation method thereof |
Also Published As
| Publication number | Publication date |
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| TW582083B (en) | 2004-04-01 |
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