TW200424930A - Secure mode indicator for smart phone or PDA - Google Patents

Abstract

A digital system is provided with a secure mode (3rd level of privilege) built in a non-invasive way on a processor system (10) that includes a processor core, instruction and data caches, a write buffer and a memory management unit. A secure execution mode is thus provided on a platform where the only trusted software is the code stored in ROM. In particular the OS is not trusted, all native applications (14a, 14b, 14c) are not trusted. The secure mode is entered through a unique entry point. The secure execution mode can be dynamically entered and exited with full hardware assessment of the entry/exit conditions. A secure mode indicator (30) is provided to tell a user of the digital system that the device is in secure mode. This indicator may be a small LED, for example. The user should not enter any secret information (password) or should not sign anything displayed on the screen if the secure mode indicator is not active.

Description

200424930 A7 ____B7 V. Description of the invention (1) The technical field to which the invention belongs This application claims to be the security mode of the processor supporting MMU and interrupts, which is the European Patent Application No. 02290115.1 dated January 16, 2002 ,, (authorization memo number 33762.1 EU), and European Patent Application Serial No. 02100727.3 on June 30, 2002, entitled “Security Mode Supporting MMU and Interrupt Processors” (authorization memo number 33762.2EU) .

ο IX Printed by Employees' Intellectual Property Bureau, Ministry of Economic Affairs, Consumer Consumption 20 The present invention relates to microprocessors, and more specifically, to the improvement of security mechanisms to support women's software services. Prior art microprocessors are general-purpose processors that provide a high amount of instruction to execute the software on them, and have extensive processing requirements depending on the specific software applications they contain. Many different types of processors are known, and microprocessors are just one of them. For example, the Digital # 5 Tiger Processor (DSP) is widely used, and it is most targeted at specific applications such as motion processing applications. DSP-Optimize the performance of the related GPs. To achieve this, they use a more specific execution unit and instruction set. Want to provide continuously rising Dsp performance, while expecting low power consumption = especially, but not limited to mobile telecommunications applications. To further improve the performance of the digital system, two or more processors can be interconnected. For example, a DSP can be interconnected with a general purpose processor in a digital system. The number of algorithms implemented depends on the processing algorithm, and the general-purpose processor takes care of all control processes. The two processors transmit and transfer data via co-limb memory for number processing. Direct memory access (DMA) control • Frequent and processing ° = This paper size applies to China National Standard (CNS) A4 specification (2 丨 〇x 297 public love) 200424930 A7 B7 V. Description of the invention (2) I 'to The burden of transferring data blocks between official memory or peripheral resources to improve processor performance. , / And have operating money (0S), through the control of resources and various = audit team or task execution touch-position Wei. In a system with several processing behaviors, it is more convenient for each processor to have an individual 0s. In a nutshell, 0s sulfur is under the control of all system resources. Many are not designed to share memory and resources with other OSs. So when two or more 0s are combined in a single-system, resource allocation problems may occur. In memory

ο 1X 5 11 Conflicts in the consumption of employees of the Intellectual Property Bureau of the Ministry of Economic Affairs ii Printed 20 conflicts in the use of external devices or peripheral devices may cause adverse consequences to system operation. The construction of the big #knife processing state has 2 privilege levels: one is for 0s use, and the other is for user tasks. A third privilege level has been proposed, but it has never been implemented in current CPUs. For specific financial or safety-critical applications, some operating systems have been identified as safe. Some are commonly used as Lions's claim to yell security, but its unbeatable system is well known. Hardware mechanisms can be used to improve security. For example, U.S. Patent No. 4,905,552, with the name "Heart-marked Security Preservation Status of Information Memory in Retransmitting Memory Towels", discloses a method of providing off-chip resources that can be permanently set to prevent access to the chip. One or more security bits in the memory (0r > chjp), thus protecting the data storage mechanism, thereby protecting the code or data stored in the memory on the chip. However, the misjudgment of the operating system can crack such a security method. For applications that can implement security categories such as commerce (mobile commerce) or ^ bank-4- This paper size applies the Chinese National Standard (CNS) A4 specification (2 丨 〇χ 297 mm) 200424930 A7 V. Description of invention 10 15 Ministry of Economy The Consumer Affairs Bureau of the Intellectual Property Industry Bureau printed a 20 (, sub-bank) Zhixian County and asked users to use the keyboard to rotate private information such as code grabbing, or the information displayed on the screen. There is no other option but to rely on the soundness of their device in performing this campaign. But use: to detect whether a hacker or virus has invaded the security structure of its device. -Summary of the Invention Due to the need to improve pure security. In summary, in a form of the present invention, a digital frame having a security module (privileged level 3) built in a processor system in a non-intrusive manner is provided. The security execution module is located on the platform, the only trusted software system of the platform is stored in the ROM code on the chip. It also provides the indicator means visible to the users of the digital system. The instruction crying method can only be activated by the trusted code under the operation of the safe mode. In one embodiment, the safe mode is entered via a unique entry point. Full hardware evaluation of entry / exit conditions and dynamic entry and exit of safe execution mode. Implementation Ί Exchanging confidential information with the user, such as passwords or messages displayed on the screen, should only be performed when the processing device is in secure mode. —A kind of security mode, device and method are described in 6G, 20G2, 6Θ, 3G date, and filed with the relevant patent application No. 02100727.3. "Security mode for supporting MM (j and interrupted processors)." Include security here A full description of the mode, so that those skilled in the art understand its operation. In the women's full mode, access to the physical user interface (such as a keyboard or display) is limited to secure applications via a trusted driver. The safe mode is used to enter the keyboard and The display control is not enough to fully guarantee the exchange of information with the user. Now the inventor has found that it is necessary to instruct the user by one means, and the 0s call should be appropriately adjusted. (%) 200424930 Description of the invention (〇 Trusted keyboard or display driver, that is, the driver stored in secure memory, and enter safe mode for execution. Otherwise, if a virus / hacker desires; a fake driver on a smart device H ′ Then the user cannot know that he cannot rely on his device. According to the aspect of the present invention, the smart device for performing security applications has a display and a pocket. Outside the keyboard-there is a safe mode indicator. This indicator will inform the user that the device is in safe mode. This indicator can be, for example, small 13 If the safe mode indicator is not activated, the user should not enter any private money 1 ( Password) or should not be signed on anything displayed on the camp screen. If you want to enter your PIN when the indicator is not activated, the user will know that their device ^ has been cracked and the device cannot provide secure operation. 4 is To achieve this' is provided on the digital system of ® 1-input / output (GP 丨 0) _ bit 154 that can only be entered in safe mode. This is a safe GPK) Γ4 lock drive security indicator LED 155. engraved The trusted keyboard and display H driver, which are subscribed to the security mode from the secure ROM / SRAM (Weiyin memory / static random access memory), are responsible for managing the security, ie flash lock. The security mode indicator must be independent Outside the keyboard and display, non-secure application software will enter these devices in non-secure mode. In particular, the messages displayed on Firefly such as, now enter the password, are generally not reliable. In addition, The symbol or message (such as a lock symbol) displayed on the camp screen to indicate safe operation is unreliable. The safe mode indicator must reliably indicate the date «M on Anyu Light Operation, and only "No" when the device is in the safe U temple. Unless the safe mode indicator is activated, the user should not pass any private information such as passwords or sign on the labor curtain 200424930 Α7 Β7 V. Description of the invention (5) 10 15 Consumer cooperation of the Intellectual Property Bureau of the Ministry of Economic Affairs prints anything 20. Figure 1 shows an embodiment of the present invention in a mega cell 100 having a plurality of processors 102 and 104. Block diagram of the digital system. For the sake of clarity, Fig. 1 only shows the part of the megabit unit 1QQ related to the understanding of one embodiment of the present invention. The general architectural details of digital signal processors (DSPs) are well known and readily available elsewhere. For example, Frederick Boutaud et al. Detail a DSP in US Patent No. 5,072,418. Gary Swoboda et al., In US Patent No. 5,329,471, detail how to test and simulate a DSP. The following will fully describe the part of the megabit unit 100 related to one embodiment of the present invention, so that those skilled in the microprocessor technology can implement and utilize the present invention. Although the present invention finds special applications for implementing digital systems such as those on special application integrated circuits (ASICs), it also finds applications for other forms of systems. The ASIC may include one or more megabit units, each of which includes a functional circuit designed for a customer and a pre-designed functional circuit from a design library. There is a distributed security system in the megabit unit 100, which uses a combination of selected hardware blocks and fork protection software execution environments. The distributed security system is a method to solve e-commerce (e, business) and mobile commerce (m-commerce) security issues in the mobile phone environment. The security issues include the following: Density: ensure that only the communicator understands the content of the transmitted information;-integrity: ensure that the information does not change during transmission; 'verification: ensure that the other-the correspondent is what he claims -No negativity: ensure that the sender cannot deny sending the message;

200424930 V. Description of Invention

A7 B7-user protection: pseudonymity and anonymity;-protection against copying. The current operating system (0s) cannot be considered safe. Some 〇s claim security, but its complexity makes it difficult to achieve or guarantee security. For e-commerce and other secure transactions, there is a need for a secure software layer. This must be easy to implement on existing os, but also support the use of memory management unit (MMU) and cache memory, while supporting timely interruption and QS support. In many applications, it has been proven that software-only solutions are not sound enough, and these issues can only be properly addressed through the hard and soft age structure. The development of the security model used in this embodiment is to introduce hardware integrity into the overall security mechanism, which is based on the following premise:-the operating system (0s) is unreliable;-all executed on the platform The essential software is not trusted; _ The only trusted software is the code stored in the security program ROM / SRAM;-the fast buffer storage area can be started for performance reasons;-the interrupt can be started for real-time reasons;-the flexibility can be Start the MMU. The above mentioned Liti drives the following results. First, OSS memory management is untrustworthy. In other words, the translation table defined by MMU operation and OS is not reliable. The security model should be able to resist any misuse of the MMU and the fact that the translation table defined by 0s may be erroneous. Secondly, the Qs definition vector table and interrupt service routines are not credible. The specific management of interrupts needs to be performed in safe mode, so that safe mode can resist any misuse of interrupts and the fact that the interrupt vector table and SR may be erroneous. Third, the completeness of the basic operation of 0s This paper standard is applicable to 1f7 national standard (CNS) A4 specification (2 丨 〇χ 297)

200424930 A7

(Such as background save, fast buffer storage area cache, DLB cache, write buffer; and fetch, etc.) are not sure, so the security mode should not be relied on. Last but not least, in safe mode, all testing, error removal, and verification capabilities need to be removed. 5 ο 1 · — * Printed by the staff of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed by the cooperative. 20 In this embodiment, a split “security mode” is generated for the processor 102, so that it can operate as an individual virtual security processor, and simultaneously Perform security operations. The security mode can be regarded as the third privilege level of the processor 102. Its activation end depends on the existence of specific purpose hardware, which can generate an environment through untrusted software to Protect confidential information from being accessed. The security mode is set by announcing an exclusive security signal 152, and the security signal 彳 52 is transmitted through the system and establishes a boundary between resources accessible by trusted software and resources accessible by any software. The activation of the security mode also depends on the proper control of the security software. The security software system is stored in the security program ROM / SRAM and executed there. There can be no access to the security mode or deception by deceiving the hardware. Trust the flow of tasks that it should not perform. If the boundary is properly established, there should be no use of the processor's normal operations, except through controlled operations. It is used as a pipeline that moves outward from the boundary. Note that the normal operation of the processor includes the execution of "user code" with potential flaws. The security software layer is trusted and stored in the secure memory. It is accessed through a single security gateway to Safe mode, while protecting from MMU modification, and enters a software sequence to the hardware security state engine (SSM) 150 does not really reward the execution of the female full code. When the female full software is executing the safe mode, it will be interrupted Vector reorientation, so that the security control software can use the Chinese paper standard (CNS) A4 specification (2 丨 0x297 mm) as required. 200424930 A7 B7 V. Description of the invention (8) Leave the security mode appropriately. Reorientation process It is transparent to 0S and can prevent the emergence of security information after the transition. 5 15 Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs. 20 GPIO latch 154 is a memory mapped interlock that operates in a known manner. The exception is its Can only be accessed and activated by security software. The indicator 155 is lightly closed to GPIO 154 and lights up in response to the GPIO. By writing logic like logic 1 The indicator 155 is turned on by the latch 154; and the latch 154 is turned off by writing a complementary logic value such as logic 0 to the latch 154. The core 103 accesses the latch 154 via the peripheral bus signal 156. The GPI is limited by the security signal 152 controlled by the SSM 150. The operation of the latch 154 is limited to the GPIO 154 only when the security signal 152 is in the startup state indicating that the processor 102 is executing a security software routine. Write. In this embodiment, the indicator 155 is a light-emitting diode (LED), but in other embodiments, any type of indicator that can show two different kinds of money: on and off. For example, it can be used Various lights, such as neon, money, etc. Various mechanical devices can be made, such as turning a disc that displays different colors to indicate the on / off state, or an actuator that moves the indicator to represent the on / off state. In other embodiments, the two states can be represented by surface changes in structure, height, temperature, etc., so that a person with visual impairment or other limb impairment can read and test the two states. For example, the contact f indicator can be placed in a scroll display device. In another implementation, it means that no audio instructions can be provided, for example, a tone can be played to indicate that the safe mode is on ', but since the turnable safety tone can imitate the tone, a certain degree of attention is required. Repeat reference level 1. The test unit contains a 32-bit core microprocessor (MPU) 102, 1, ncD, and a digital signal with DSP core 105. -10- This paper is based on the national standard (CNS) A4. Specifications (21—297 mm) 200424930 A7 B7 V. Description of the invention (9)

The processor (DSP) 104 shares a memory block 113 called a second-level (L2) memory subsystem. The flow control block 11 receives a transfer request from the main processing node connected to the main interface 120b, a request from the control processing state 102, and a 5 transfer request from a memory access node in the DSP 104. The flow control block inserts these requests and presents them in shared memory and fast buffer memory. The shared periphery 116 is also accessed via a flow control block. The direct memory access controller 106 can transfer data from external sources such as off-chip memory 132 or on-chip memory 134 and shared memory. It can also be seen that each application needs to include various application-specific processors or hardware accelerators 10 108 into the megabit unit, and interact with the DSP and MPU through the flow control block. · In addition to the megabit unit, the third level (L3) control block 130 responds to the explicit request from the DSP or MPU, and links to receive the §memory request from the internal flow control block 110. The external memory 132 and / 15 outside the chip or the on-chip memory 134 are connected to the system flow controller 130; these are called the L3 memory subsystem printed by the consumer cooperation of the Intellectual Property Bureau of the Ministry of Economic Affairs. Both the time frame buffer 136 and the display device 138 are connected to the system flow controller to receive data for displaying images. The main processing β 120a interacts with external resources via the system flow controller 130. The main interface connected to the flow controller 130 can access the main processor i20a to 20 external memories and other devices connected to the flow controller 130. Therefore, in each embodiment, the main processor may be connected at the third level or the second level. — A group of private peripherals 140 is connected to the DSP, while another group of private peripherals 142 is connected to the MPU. Fig. 2 is a block diagram of the MPU 102 in the system of Fig. 1 and its explanation. The eleven-square scale uses the Chinese National Standard (CNS) A4 specification (210 x 297 mm) 200424930 A7. 5. Description of the invention ( 10 10 15 Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs for consumer cooperation. 20 Decentralized security using a combination of selected hardware blocks and a protected software execution environment executed by a security state bow engine. In another embodiment of the digital system, For example, the processor 1 (32 may be a single-processor, or may be combined with one or more processors for cooperative operation. The security mode is the processor 102. Among them, the third privilege level, The security mode provides hardware means to prevent access to the security subsystem of the processor subsystem (CPU) 20Ό set under the appropriate execution environment. The security mode is built around the CPU 2Q0. The CPU 200 contains the processor core, The data and instruction cache areas 204, 206 and MMU 210 are fast. The advantage is that the security features of this embodiment are not invasive to the CPU 200. Therefore, in another embodiment, another processor may be used instead of the processor. Security Hardware Yes Category: logic to control the security signal, and hardware resources restricted by the security mode. The former is mainly composed of the security state engine (SSM) 300. SSM 300 is responsible for monitoring the conditions for entering the security mode; declare / cancel security 302; and the security mode violation on the side. Indication of a violation by declaring a violation signal 304 connected to the reset circuit system 306, even if the system is reset when a security violation is detected. The security status engine monitors from the external interface of the processor 200 Each of the signals 330, especially the address obtained for the processing source on the instruction bus. The state-preserving engine is tightly coupled to the low-order combination code from the incoming sequence. It makes events on the events generated by the incoming sequence on the monitored signal Response. The security mode is entered when the security signal is announced 302. When the security signal is announced, it passes through the entire system and opens access to secure resources. In secure mode, only the processor 200 can access secure resources. In this example -12- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 200424930 A7

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Explanation of the invention (12) There are a few variables that can be reset in the safe mode, so it is advantageous to have the initial value that is known and can only be changed in the safe mode. For example, this feature can be used to: detect the first entry in safe mode; set the proper leave. Mode values (normal, exception, violation); detect power on, etc. In another embodiment, these resettable values can be implemented in other ways, such as by placing a register in an address space that does not overlap the SRAM; by linking the reset signal to the selected memory in the SRam Unit, etc. There is no software way to declare the security signal 302 or improve the behavior of the state engine. SSM is tightly integrated into the startup sequence detailed in Part 5. The SSM monitors the physical instruction address bus 330 from the processor 200 and the entry condition signals 321-327 received from each resource. The instruction interface signal 331 and the data interface signal 333 from the processor 200 are also monitored. It also defines what kind of bus processing is performed on the instruction bus 330 and the data bus 332. A secure fork is an entry by branching to a specific address in a common ROM. It is called a single entry point and is a hard-coded address in the SSM. The entry point is the start address of the "startup sequence". The startup sequence is stored in the -ROM of the public ROM coupled to the security status engine, and it is ensured that the red part of the security model is the entry condition. Other entry conditions are monitored by the supervisor The county determines the condition signal and directly evaluates it. The startup sequence generates defined events on a portion of the money monitored by the security status engine. The sequences ensure that the conditions required to enter the security mode have been met. The security status engine recognizes this model and declares Security signal. In the safe mode, the “preservation status bow | engine continuously monitors some signals to detect violations of the security mode. 200424930 V. Description of invention (13) 105 0 112 Employees of the Intellectual Property Bureau of the Ministry of Economic Affairs printed A7 B7 and Ensure that the safe mode exit procedure is met. Whenever a violation occurs, SSM will release a security signal and declare a security violation signal 304. A typical violation is to try to take out instructions outside the range of rOM / sram. The startup sequence is stored in Public ROM. It ensures that the safe mode entry conditions have been met. The environment setting sequence is stored in the secure ROM. Set the appropriate execution environment in the safe mode that can activate the fast buffer storage area 'interrupt and MMU. The exit sequence is stored in the secure ROM. It enforces the safe mode exit procedure. It is executed by a branch or interrupt. The following provides a way for a woman to leave the security mode. It also protects the "private" content of the security ROM and RAM when leaving. Still referring to Figure 2, the security control register 319 can act as a delta memory only in the security mode. The mapping memory can be accessed and used to actuate / shut down. It can be used by hackers to break the security, but the system hardware and software certification and debugging are still needed for testing, debugging and simulation. Facility. For example, signal 32 indicates that one bit activates / deactivates the operation of embedded tracking macro unit (ETM) 350 for program development. Signal 322 activates / deactivates the JTAG interface on the processor 2000. The signal 323 activates / deactivates the operation of the debug interface (dbg I / F) on the processor 200. In the non-secure mode, the security condition register 32 can be used as a memory mapping temporarily. Registers and are accessed by control Partial entry conditions set in safe mode for hackers to destroy the operation mode of the resources protected. The signals provided by the self-protection condition register are also monitored by the state engine. For example, direct memory access (DMA) actuation Signal 324 is used to actuate a DMA controller (not shown) that can access the secure memory 312. -15- This paper size applies to China National Standard (CNS) A4 specification (2 丨 0 x297 public love)

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5 ο 1 × 5 1 × Printed by the staff of the Intellectual Property Bureau of the Ministry of Economic Affairs, sold by the cooperative. 20 In this embodiment, a scan string interface (scanning | / f) is provided for testing, and a security damage point can be provided. However, the office did not provide a means for outputting the scan string. In order to avoid modifying and processing the internal signal of H, from the outside = for scan gate 342, it is out of the scan wheel that covers processor 200, and its clock length is equal to the number of the longest scan string in processor 200. This masking mechanism (counter reset) is personalized at the time of reset, and the device is switched from the function mode to the test mode each time by a scan actuation under the control of an external test device (not shown). An external interrupt operator 360 is provided to receive a set of interrupt signals, and retransmit them as two interrupt signals 362, 363, which are then received by the processor 2000. The interrupt processor 360 has an overall masking bit 364 that can be set by software and enables the software to turn off all interrupts to the processor as a whole. Whenever the overall mask bit is set, the interrupt controller announces the mask signal 325 and turns off the interrupt signals 362, 363. After announcing the masking signal 325, until the overall masking bit is cleared by the software, the interruption signals 362 and 363 output by the interrupt controller can no longer be announced. The SSM 300 monitors the masking signal 325 to decide whether to activate or mask the interrupt. Booting from external memory is a common way for hackers to compromise system security. In this embodiment, external booting is avoided. In addition, the SSM 300 monitors a power-on signal 327 that is announced when an external power-on is attempted. However, during program development, it is better to allow external boot to facilitate software debugging. A fuse circuit 328 is provided to distinguish a development device from a production device. The device-type signal 326 is monitored by the SSM 300, so it can provide a release security mode on the development device. For development devices, the SSM 300 ignores the power-on signal 327. -16- This paper size is in accordance with the Chinese National Standard (CNS) A4 specification (210x297 public love) 200424930 A7 V. Description of the invention (5 10 15 20 Figure 3 illustrates the ROM content of Figure 2 and is used to divide the ROM It is a block diagram of the circuit system of the public ministry and the security ministry. In this embodiment, the common ROM 311 and the secure ROM 310 are implemented by a single ROM. In another embodiment, 'can not affect the inventiveness here. It is divided in an aspect. The address decoding state circuit 370a is a part of the inversion circuit 370 for accessing the ROM of the ROM. Similar circuits are provided for devices connected to the SRAM and other instructions or data buses. At any time, in response to the address decoding signal 406 or 407 corresponding to the public ROM address or the secure ROM address, respectively, the declaration of the address corresponding to the ROM 310 and 311 on the instruction address bus 330a results in The driver circuit 400 is driven to provide the required instruction data on the instruction bus 33ob. "As disclosed above, if the secure resource is not accessed in the safe mode, false data is provided. The gate circuit 404 monitors the security signal 302 and the safety R 〇M solution signal 407, and if access If the safety ROM is not announced, the driver circuit 400 will pass the invalid data. The safety mode is shown in Figure 4_Lai 2 on the safe mode operation flow chart, which will now be described in more detail. Steps_5Q2 5Q4 stands for-normal unprivileged execution of t 'applications executed on processor 2 (χ) ^ sometimes services in privileged operation, as shown in steps 510, 512, 514 and 516 to the operating system ( os) generation—call 5Q2. As long as _call, Lang 2 saves the state and switches to privileged mode; knows the subscription operation in step 514; restores the state in step 516; and returns the non-privileged application in the coffee 。 These two scales are important. ° 4 Order -17- This paper size is suitable for wealth @ ϋ 家 标准 (cns) A4⑽⑽ X 297mm) 200424930 A7 V. Description of the invention (l6 In step 512, Test to determine whether the required service is safe operation; if so, the system will enter a third level of security called a security mode. At step 520 + 'OS driver performs housekeeping work, puts the system in an appropriate state to enter security Mode. This includes masking Set the security condition register 320 to shut down various resources with security risks; and confirm whether to activate the memory management unit 210, which causes the page table entry corresponding to the startup sequence to be marked as a non-quick storage buffer ''. This will be further detailed later. In step 522, referring back to FIG. 3, skip to an entry point 410 in an entry sequence 412 located in the public ROM 311. The entry sequence is a set of 10 yards, each time Before any type of security code is executed on the platform, it is executed when the "security service" is called by the application. This sequence is also executed when the exception is resumed from the execution of the interrupted security code. The entry sequence starts at the address defined in ROM, which is hard-coded and is called the "entry point". The entry sequence is composed of two parts: a security signal activation sequence 413 and a safe mode environment setting sequence 414. The purpose of starting the sequence is to replace the execution flow of processing H, and to ensure that any other non-random code rogue first occupies some point during this part of the gangster's announcement of the security signal 302 to enter the safe mode and release Access to secure resources (ROM 'SRAM' peripherals, etc.). The purpose of the sequence 414 is to set the environment in which the whole mother executes. The advantage is that by setting the safety switch, you can safely store miscellaneous and miscellaneous caches, and make exceptions to operation interruptions. The security signal activation sequence 413 is located in the public ROM, and the safe mode environment setting sequence 414 is located in the safe ROM. The total code of the entering sequence is large-18- This paper size is applicable to the national standard (CNS) A4 specification (2 | 〇χ 297mm) 200424930 A7 B7 V. Description of the invention (Γ 5 10 15 Employees ’consumption of Intellectual Property Bureau of the Ministry of Economic Affairs Cooperate to print 20 small (Part 1 + Part 2) less than 1 kilobyte, so that it can be mapped to a 1-byte page. For this embodiment, it is the smallest memory paragraph in the MMU translation table. In this way, the virtual address of the entry sequence cannot be mapped to two paragraphs, so that during the execution of the entry sequence, the processor is preferentially occupied at some breakpoints. The memory page of the entry sequence is non-fast bufferable storage It is also important to close the instruction fast buffer when executing the entry sequence. The security translation table (STT) 420 and the security interrupt vector table (SIVT) 430 will be described later. If you see that the size of the 1-byte code is given to Considered as too restrictive in the embodiment, the MMU can be turned off at the startup sequence 413 and re-activated at the end of the environmental sequence 414. In this case, the 1-kbyte limit will only affect the startup sequence. See FIG. 4 at step 524 For the sake of correction, check the startup sequence with SSM 300. As described in detail in Part 5. If the startup sequence is not implemented properly, then the violation signal is announced by SSM in step 54Q and the system is reset. The security environment is set by executing the environment setting sequence 414, which will be described in detail later. To create a female-wide environment, that is, to perform the required security operation in steps from the security code 416, as if it was requested at the beginning with a Fina system. According to one aspect of the present invention, the security code 416 & includes a command to write GPIO_318 in the step ”, which only turns on the security mode indicator 319 in the security mode. The security code can then be requested in step 5282 The user provides confidential information, and then in step 528.3, the security mode is closed again by writing to the GPIO latch again. ", The full-length pull-down style is not forbidden. In step 5284, the attached paper is executed in accordance with Chinese national standards. 200424930 A7

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Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs

, ’Need to be cleared in Guan'an New Yuan money line. To allow interrupts in safe mode, security is required. & FIG. 5 is a detailed state diagram of the security state operation. The security status engine executes the startup phase in ROM and announces a security signal at some points to enter the safe mode. The purpose of this part of the sequence is to generate a defined event phase on the signal on the side of the preservation state. These events ensure that the conditions required to set the security signal are met and can be searched by SSM2. "Condition" signals are monitored throughout the startup sequence. If at the end of the start sequence, any entry conditions are not valid, the protection state engine will transition to the violation state 630 and declare a security violation signal 304. There are two key purposes behind monitoring the entry conditions with SSM: (i) the processor 200 is drawing and executing the boot sequence code; (2) the trusted code has completely replaced the cpu execution process, except after controlled operations, regardless of whether Before and after the security signal is set, no one can take priority without being detected. The startup process is constructed in such a way that a unique prototype is generated on the instruction address bus. The prototype is made up of the (actual) address values of the boot sequence and the relative timing in time. These addresses should appear on the bus. However, the prototype is not related to the memory system access latency. The exact startup sequence bus prototype k is derived from simulation and hard coding in SSM. SSM thus ensures full compliance with the start-up sequence bus prototype. Typically, the final instruction of the startup sequence is a branch instruction, and is different from the fast cache clear instruction or fast cache close instruction. All other instructions in the startup sequence are NOP instructions. 0 In safe mode and have been declared safe After the signal, the entry conditions do not need to be -21- This paper size applies to China National Standard (CNS) A4 (210 x 297 mm)

200424930 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Invention Description (20), and SSM does not continuously test it. However, the SSM continuously detects each signal to detect the reversal of the female full mode, which will be described below. The test of the safe mode exit condition is not performed until after the safe memory is effectively entered. Referring again to FIG. 5, state 600 is an idle state. During this period, 5 SSM monitors address bus 330 to find the entry point address (ESA [EP]) of the incoming sequence. As soon as an entry point address is detected, SSM transitions to state 601 if all entry conditions are met; otherwise, transitions to state 630 where the violation signal 304 is declared. 10 must pass through the states 601-615 in sequence by detecting the correct entry sequence address and the corresponding entry condition signal, otherwise the SSM transitions to the violation state 630. If these sequences pass without error, the safe mode state 620 is entered and a security signal 302 is announced. For example, to transition from state 600 to state 601, the address of the entry point instruction must appear with all the correct condition signals. The next occurrence address must be the address of the next 15 sequence instruction to transition to state 602, otherwise SSM transitions to violation state 630. In a similar approach, all addresses in the startup sequence must appear to transition to states 602-615, and finally to safe mode state 620. The error address 'address timing or error change in a condition signal will cause a transition to the reverse state 630', such as shown by the line 601a. Similarly, if the 20 status signal indicates that any boot sequence access is cacheable, the boot sequence will fail. In safe mode state 620, and after effectively detecting the address of the security routine (ESA [SR]) that indicates that it has entered secure memory, if an address is detected by the SSM located in the public ROM , Then SSM transitions back to -22- This paper size applies + National National Standard (CNS) A4 specification (210 x 297 mm)

V. Description of Invention (Μ) 200424930 Α7 ___ Β7

Go to idle mode 600, as shown by arc 621. If an address is detected with Sm outside of rom or SRAM, or if a security violation is indicated by an error change in the monitored signal, the SSM transitions to a violation state of 63, as shown by arc 622. There is no need to close the instruction cache during the startup sequence; the non-cacheable nature of instructions is sufficient to ensure the soundness of the incoming sequence. However, turning the cache off will eliminate attempts to invade it by improper use of the cache clearing mechanism. Safe Mode Environment Setting Sequence

Referring again to FIG. 4, in step 526, a secure environment is set by executing an environment setting sequence 414 from the secure ROM. The purpose of this sequence is to set a proper view of the execution status of the security code. Security Wei allows programs and data to quickly buffer storage areas, immediate interruptions, and potential MMUs. Some of these steps are specific to safe mode operation, and some are normal operations that should have been performed for QS during the call start sequence. As mentioned before, the safe mode cannot rely on basic 0s operation. Therefore, the environment setting sequence needs to perform some background switching operations, such as clearing the cache area and clearing the TLB, which are essential to the security mode integrity. System Embodiment FIG. 6 illustrates an exemplary implementation of an integrated circuit implemented in a mobile telecommunication device, such as a mobile personal digital assistant (PDA) 10, having a display 14 and an integrated input sensor 12a located on the display 14. , 12b. The digital system 10 includes a test unit as shown in the figure, which is connected to the input sensors 12a and 12b via an adapter (not shown) as an Mpu -23-

1520 Consumption co-operation by employees of the Intellectual Property Bureau of the Ministry of Economic Affairs V. Description of invention (22) 142 for peripheral use. You can use Yan Pen or your finger to input information to the PDA via the sensor. The display 14 is connected to the inspection unit via a local buffer similar to the time frame buffer 136. The display ^ provides the images in the superimposed windows such as the MPEG image window 14a, a total of 5 10 15 and the 3D game window 14c. Image output. ⑽ 电路; circuit system, make up "is carried to antenna 18, the driver for the inspection unit crane is used as a DSP private peripheral, and provides a wireless network chain. The connector 20 is connected to an electrical coupler (not shown), and from there it is connected to the device as a Dsp private perimeter, providing a wired network key for, for example, the office to emit static smoke. The pure surplus chain 23 is also connected to the earphone 22 and is driven by a low-power transmitter (not shown) as a private peripheral 140 of the coffee unit. The microphone μ is also connected to the megabit unit in a similar manner, so that the microphone% and the wireless headset 22 can be used to exchange two-way sound information with its side users on the wireless or wired link. Λ Megabit π 1⑷ provides all encoding and decoding for the sound and video / pictures that are transmitted via wireless network keys and / or wired-based network keys. The advantage is that the survey also provides a safe operating mode. As described herein, the 'safe mode indicator light 30' is controlled by a question lock, which can only be turned on by the execution code when the megabit 270 is executed in the safe mode. The safety mode indicator lamp 30 indicates to the user of ρ〇Α〇 at

Provide confidential information for execution on the PDA. In this method t, PDA Γ provides solutions to the issues of electronic listening (e.com.) And mobile commerce (m-commerce) preservation in mobile electronic series. -24- 200424930 A7

I I I 200424930 A7 B7 24 V. INTRODUCTION OF THE INVENTION Xuan, Xing and data fast buffer storage area, write buffer and memory management sheet 7C. The safe execution mode is located on the platform, where the only trusted software is the exhaustion stored in ROM. In particular, 0S is unreliable and all essential applications are unreliable. The safe mode indicator is used to inform the user that the device is in safe mode. 105 ο 1 1 2 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Although the present invention has been described with reference to the illustrated embodiments, this description is not intended to be limiting thereby. Those skilled in the art can refer to this description to understand various other embodiments of the present invention. For example, the security mode patterns described here can be used to improve all types of processing, such as precision instruction set operations (RISC), complex instruction / operations (CISC), wide blocks, DSP, and so on. In another embodiment, the security environment may be extended to share security resources among several initiator resources such as DSPs. In this embodiment, the preservation status engine can monitor each indicator resource to enforce the above-mentioned preservation principle. In various embodiments, there may be different supplements of security hardware, including various peripherals such as watchdog timers, encryption / decryption hardware accelerators, random number generators (RNG), etc .; and various | / 〇 devices such as keyboards, [ CD, touch screen, etc. Referring again to FIG. 1, in another embodiment, the second SSM may be located in the DSP 104 ′ to generate a security signal in a similar manner to the processing 102 for the security software layer executing on the DSP 104. In this embodiment, the security signal of the bus version can be incorporated into the flow control bus 110, so that the processing initiated by the processor 102 or the DSP 104 can access the security resources, such as the security signal generated by each SSM Of specific shared perimeter 116. Referring again to FIG. 1, in another embodiment, the security signal may extend beyond -26- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 200424930 A7 B7 V. Description of the invention (25 5 ο 11

5 IX Consumption cooperation with employees of the Intellectual Property Bureau of the Ministry of Economic Affairs printed 20 trillion yuan of 100 yuan, allowing third-level resources to operate in a secure manner. The M startup sequence, the environment setting sequence, and the leaving sequence may be changed according to the requirements of the embodiments. For example, different instruction pipeline lengths and different cache line lengths need to be changed during the startup sequence. In another embodiment, the housekeeping work performed in step 520 can be included in the startup sequence. In another embodiment, the means of entering the safe mode may be different from the SSM described herein. As long as the safe mode operation is obtained by any means, a safe mode indicator, which is available only when in the safe mode, can be used to indicate that the user system is operating in the safe mode. In another embodiment, a means other than GPI may be provided to activate the safe mode indicator. For example, bits from the security control register 319 can be used. Similarly, bits from one of the security devices 316a or 316b may be used. The main requirement is that the means can be accessed only in safe mode. In another embodiment, the safe mode indicator may be directly responsive to the safe signal such that the safe mode indicator is activated full time when the processor is in the safe mode. However, in this embodiment, the user can know that the indicator is in the on mode, and therefore wants to omit it, so this is not a preferred embodiment. Referring again to FIG. 2, the security device 316a may be an input device for receiving confidential information from the user. In this way, the input device can be activated to receive the confidential information only when the system is operating in the safe mode. Figure 2 shows the security device attached to the wafer. This is not necessary for all embodiments. It can also be an off-chip device such as an independent fingerprint identification device. Access to external devices -27-

200424930 A7 V. Description of invention 26 5 10 15 20 May be restricted in women's full-core model. The code exchanged with security external devices does not need to be confidential except for the encryptor. When operating the device, the user can see the external safety device. If Lai Zhi is unable to operate outside the safe mode, it is more difficult for hackers to deceive users. Refer to ® 2 for optional tamper detection device 38. Output 380.1 from the tamper detection device 380 provides an indication that the access cover on the sleeve containing CRJ 2000 has been tampered with. Then use SSM 3GQ monitoring signal _ · 1 ′ 俾 When tampering is detected, it will not enter safe mode. The money-like right is in safe mode when tampering occurs, then the SSM detects this passing signal 38Q_1 and leaves the safe mode to indicate violation, as mentioned above. The tamper detection device may also be an external off-chip device. The output of the button detection device can be monitored by SSM or the safety GPI0 can be registered. Since Gp | 〇's access is restricted by the security mode, the client cannot clear it. In this way, the security software will see the next time it enters safe mode. The scope of the accompanying patent application is therefore to be regarded as any such improvement of the embodiments encompassed within the true spirit and spirit of the invention. Brief Description of the Drawings With reference to the accompanying drawings, the special embodiments according to the present invention are described by way of example only. Similar codes used are similar parts of the table, and unless otherwise described, the drawings are related to the digital system of Figure 1. Among them, FIG. 1 is a block diagram of a digital system including an embodiment of the present invention in a megabit unit with multiple processor cores; FIG. 2 is a block diagram of the system block of FIG. 1, which is explained by selecting The hardware block is also protected by the Security State Engine (SSM). Tt -28- This paper size is applicable to the Chinese National Standard (CNS) A4 specification (2 丨 〇χ 297 公 爱 200424930)

5

ο The decentralized security of the 1X software execution environment combination; Figure 3 is a block diagram illustrating the ROM contents of View 2 and the circuit that separates the ROM into the Ministry of Public Security and the Ministry of Security; Figure 4 illustrates the system entering Figure 2 Flow chart of the operation of the security mode; FIG. 5 is an operation state diagram illustrating the security state engine in the system of FIG. 2; and FIG. 6 illustrates a wireless personal digital assistant including an embodiment of the present invention. Unless otherwise indicated, the corresponding numbers and symbols in different diagrams refer to the corresponding parts. 10144h Consumption cooperation by employees of the Intellectual Property Bureau of the Ministry of Economic Affairs 8 2 4 0 3 5 8333 1222410101010112030343850 U1 * HI T— 1. Schematic code description Personal digital assistant 12a, 12b Integrated input sensor display 14a Image window shared text file Windows 14c 3D gaming window antenna 20 connector headset 23 wireless link microphone 30 safety mode indicator light megabit unit 102 microprocessor core 104 digital signal processor (DSP) digital signal processor 106 direct memory access control core controller Hardware accelerator 110 Flow control block Memory block 116 Shared peripheral main processor 120b Main interface flow controller 132 Off-chip memory On-chip memory 136 Frame buffer display device 140, 142 Private peripheral security status engine (SSM) 152 Security signal -29- This paper size is in accordance with Chinese National Standard (CNS) A4 (210x297 mm) 200424930 A7 B7 V. Description of Invention (28) Consumer Co-operation of Intellectual Property Bureau of the Ministry of Economic Affairs 钍 Printed 154 Universal Input / Output (GPIO) latch Lock bit 155 security indicator around LED 156 Bus signal 200 Central Processing Unit (CPU) / Processor Subsystem 204 Data cache. Memory 206 Instruction cache memory 210 Memory management unit 300 Security state engine (MMU) (SSM) 302 Security signal 304 Violation signal 306 Reset circuit system 310 Secure read-only memory (ROM) 311 Public read-only memory (ROM) 312 Secure static random access memory (SRAM) 316a, 316b Safety peripherals 318 General-purpose input / output (GPIO) latch 319 Security control register / safe mode indicator fuse circuit 321 ~ 327 Entry condition signal 328 330 Command bus 330a Command address bus 330b Command bus 324 Actuation signal 326 Device type signal 327 Start-up signal 331 Command interface signal 332 data bus 333 data interface signal 342 scanning gate 350 embedded tracking macro unit 360 interrupt operator 362, 363 interrupt signal 364 overall mask bit 370 decoding circuit 370a address decoder circuit 380 tamper detection device 380.1 signal 400 driver circuit 404 gate circuit 406 public read-only memory (ROM) encoding signal 407 Security read-only memory (ROM) decoded signal 410 Entry point -30- This paper size applies Chinese National Standard (CNS) A4 (210 x 297 mm) 200424930 A7 V. Description of the invention (29) 413 416 420 Idle state security mode State (I), the designated representative of this case: Figure 4: The sequence of the security signal activation sequence Safety Translator Table (STT) 500,502,504, steps 510,512,514, 516,520,522, 524,526,528, 528.1,528.2, 528.3,528.4, 530,540 600 620 414 Safety mode environment settings Sequence 418 Safety read-only memory (ROM) leaving sequence 430 Safety interrupt vector table (SIVT) 542,601 a, trip line 621,622 601 ~ 605 status 630 Violation of the state representative diagram of the component representative symbol Brief description:

Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper is sized for China National Standard (CNS) A4 (210x297 mm)

Claims (1)

200424930 Patent Application Scope 1. A method for operating a digital system, comprising the steps of: providing a safe mode operation that can only execute trusted code; and ^ providing a visible safe mode indicator hand & for the digital system, where The indicator means can only be activated with the _ code in the safe mode operation. 2. The method according to the first patent application scope, further comprising the steps of: executing an application program; entering the safe mode operation to execute a secure portion of the application program; 10 15 20 in response to the secure portion of the application program, activating the Means of safe mode indicator; and • while activating the means of displaying the information, a user is required to provide confidential information to the secure part of the application. , = The method of item 2 of the patent scope, further comprising the step of turning off the safe mode indicator means after receiving the confidential information and when the safe part of the application is continuously executed in the safe mode. If the method of the second or third item of the patent scope is applied, the step of activating the safe mode indication H means includes the execution of the “write_memory mapping to flash lock order” where only when operating in the safe mode When this instruction is executed, the memory map latch can be written. 5. The method as claimed in any one of items 彳 to 4 of the scope of patent application, wherein the step of providing a safe mode operation further comprises the steps of: jumping to an entry address located at a specific address in an instruction memory; A start-up sequence instruction is executed from the entry address; and only when fully executed by the central processing unit (CPU) in a predetermined sequence 32-This paper size is applicable to National Standard (CNS) A4 (7 ^ 297 public love) 200424930 AS B8 C8 VI. When applying for the start-up sequence instruction of the patent application range ~ -----, enter the safe mode operation. 6. If the method of any of the items j to 5_ in the scope of the patent application, further comprising the step of providing tamper detection means to detect whether the digital system has been tampered with; and 5 of which, if the new detection means indicates The digital system has been tampered with, and it is forbidden to provide a step of safe mode operation. 7. — A digital system, including: a central processing unit (CPU) for executing instructions; a public 5th memory for storing non-secure instructions connected to an instruction bus of the CPU, the CPU at any time Access to the public memory body · A secure memory for storing safety instructions connected to the instruction bus of the CPU, the safety memory can only be accessed when a security signal is announced; the security circuit, which Has an output for declaring the security signal when a security mode operation is established 15; and a security mode indicator in response to the security signal, a user of the digital system can see the security mode indicator, where The safe mode indicator can only be placed in a start-up mode by executing an instruction when announcing the consumer cooperation of the employee of the Intellectual Property Bureau of the Ministry of Economic Affairs to print the k number. 2. The digital system according to item 7 of the patent application scope, wherein the safe mode indicator includes: A linked memory mapping latch to receive a data bit from the CPU in response to a write instruction Meta signal, the operation of the memory mapping latch is controlled by the security signal, so that only when the security signal is announced, the record -33-This paper size applies the Chinese National Standard (CNS) aT ^ 格 ⑵0 ? (297 公 ») '—-200424930 VI. Patent application scope Memory map pair, which has a-output key to indicate the status of the latch; and-safe mode indicator device, its connection To the record, the output signal of the interlock is reflected, and the safe mode indicator device is in response to the state of the interlock 5 ', wherein the safe mode indicator device is -light, or -can indicate the open state or The mechanical device of the closing device 'or-a sound device which can indicate the opening state of the shed closing device. 9. If the digital system of the 7th or 8th in the scope of patent application, further includes a button to detect, it is operable to indicate whether the recording system 10 has been buttoned, and its full circuit monitoring and inspection The method of calling for change is operable to avoid establishing a safe operation mode in response to the method of detecting the button. 10 · If the digital system of any one of claims 7-9 is a wireless device, further comprising: · 15 an integrated keyboard connected to the CPU via a keyboard adapter; and a display adapter connected to A display of the CPU; consumer cooperation of the Intellectual Property Bureau of the Ministry of Economic Affairs; printed radio frequency (rf) circuit system connected to the CPU; and an antenna connected to the RF circuit system; and the safe mode indicator includes a The display is a light emitting diode (LED) arranged in the line of sight. -34-This paper is suitable for National Standards (CNS) A4 specifications