TW200426845A - The weak programming method of a non-volatile memory - Google Patents
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- 230000015654 memory Effects 0.000 title claims abstract description 112
- 238000000034 method Methods 0.000 title claims abstract description 37
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- 102000004129 N-Type Calcium Channels Human genes 0.000 claims description 3
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- 238000009826 distribution Methods 0.000 abstract description 10
- 230000005641 tunneling Effects 0.000 description 21
- 108091006146 Channels Proteins 0.000 description 20
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 239000002784 hot electron Substances 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- 238000011084 recovery Methods 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 230000002776 aggregation Effects 0.000 description 1
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Abstract
Description
200426845 五、發明說明（1) 發明所屬之技術領域 本發明是有關於一種弱程式化方法，且特別是有關於 一種非揮發性記憶體（Ν ο η - V ο 1 a t i 1 e M e m 〇 r y )之弱程式化 方法。 先前技術 快閃記憶體（F 1 a s h M e m 〇 r y )為一種電氣抹除式可程式 唯讀記憶體（EEPROM)，其具有可寫入、可抹除、以及斷電 後仍可保存數據的優點，是個人電腦和電子設備所廣泛採 用的一種記憶體元件。此外，快閃記憶體為非揮發性記憶 體（Non-Volatile Memory ;NVM)的一種，其具有揮發十生 記憶體體積小、存取速度快、耗電量低的優點。快閃記憶1 體在資料抹除（Erasing)時係採用「一塊一塊」（Block by Block)抹除的方式，但是在常用的FN通道 (Fowler — Nordheim channel)抹除方法中，常會因過抹 除，而造成抹除臨界電壓分佈很廣以及產生更多的快閃記 憶體之位元線的漏電流。 在習知的快閃記憶體中，基底上以隧穿氧化層 (Tunneling Oxide)與浮置閘極（Floating Gate)相隔， 且浮置閘極之上配置有控制閘極（C ο n t r ο 1 G a t e )，此二閘 極之間以閘極介電層（Inter — Gate Dielectric Layer)相 隔，其中，此快閃記憶體為堆疊閘極快閃記憶體，且浮置 閘極與控制閘極係由摻雜的多晶矽製作而成，而源極區與 汲極區則配置於基底之兩側。 當快閃記憶體在進行資料寫入的操作時，係將源極與200426845 V. Description of the invention (1) The technical field to which the invention belongs The present invention relates to a weakly stylized method, and in particular to a non-volatile memory (N ο η-V ο 1 ati 1 e M em 〇ry ) 'S weakly stylized approach. The prior art flash memory (F 1 ash M em ry) is an electrically erasable programmable read-only memory (EEPROM), which has write, erasable, and data that can be saved after power off. The advantage is a memory element widely used in personal computers and electronic devices. In addition, flash memory is a type of non-volatile memory (NVM), which has the advantages of small volatile memory, fast access speed, and low power consumption. The flash memory 1 uses the "Block by Block" erasing method when erasing data, but in the commonly used FN channel (Fowler — Nordheim channel) erasing method, it is often erased This results in a wide range of erased threshold voltage distributions and more leakage current from the bit lines of the flash memory. In the conventional flash memory, a tunneling oxide is used to separate the floating gate from the floating gate, and a control gate (C ο ntr ο 1) is arranged above the floating gate. Gate), the two gates are separated by a gate dielectric layer (Inter — Gate Dielectric Layer), wherein the flash memory is a stacked gate flash memory, and the floating gate and the control gate It is made of doped polycrystalline silicon, and the source region and the drain region are disposed on both sides of the substrate. When the flash memory is performing a data write operation, the source and the
10175twf.ptd 第8頁 200426845 五、發明說明（2) 基底接地，且在控制閘極與汲極上施以適當電壓，用以將 電子注入浮置閘極中。而在讀取快閃記憶體中的資料時， 係於控制閘極上施以適當的工作電壓，此時浮置閘極的帶 電狀態會影響其下通道（C h a η n e 1 )的開/關，而此通道之開 /關即為判讀資料值「〇」或「1」之依據。另外，在快閃 記憶體進行抹除資料的操作時，係將基底、汲（源）極區或 控制閘極的相對電位提高，並利用穿隧效應使電子由浮置 閘極穿過穿隧氧化層而排至基底（亦即Substrate Erase) 或汲（源）極中（Drain (Source) Side Erase)，或是穿過 閘極介電層而排至控制閘極中。 在對快閃記憶體進行寫入的操作時，通常是以通道熱Φ 電子注入（Channel Hot Electron Injection ，簡稱CHEI) 模式對快閃記憶體進行程式化操作，以將資料寫入至快閃 記憶體内；在進行快閃記憶體内之資料抹除時，則以F N穿 隧（Fowler Nordheim t u η n e 1 i n g )模式將電子自浮置閘極 中經由穿隧氧化層拉出至通道中。 其中’在以F N穿隧模式進行抹除資料的動作時，因從 浮置閘極拉出的電子數目不容易控制，所以容易產生從浮 置閘極拉出的電子數目太多’而使得浮置閘極帶正電荷， 造成了過抹除（Over-Erase)的現象，並使得快閃記憶體的 抹除臨界電壓分佈變廣以及位元綠產生漏電流的情況。而 若，抹除太嚴重時，會使得通道不用經由控制間極的電壓 而f通’以致產生錯誤的資料。因此，習知利用額外的軟 程式化（Soft Program)以及過抹除確認（〇ver_Erase10175twf.ptd Page 8 200426845 V. Description of the Invention (2) The substrate is grounded, and an appropriate voltage is applied to the control gate and the drain to inject electrons into the floating gate. When reading the data in the flash memory, an appropriate operating voltage is applied to the control gate. At this time, the charged state of the floating gate will affect the on / off of its lower channel (C ha η ne 1). , And the opening / closing of this channel is the basis for judging the data value "0" or "1". In addition, in the flash memory erasing data operation, the relative potential of the substrate, the drain (source) region or the control gate is increased, and the tunneling effect is used to make the electrons pass through the tunnel from the floating gate. The oxide layer is discharged into the substrate (ie, Substrate Erase) or drain (Source) Side Erase, or through the gate dielectric layer and discharged into the control gate. When writing to the flash memory, usually the channel hot Φ electron injection (Channel Hot Electron Injection (CHEI) mode) is used to program the flash memory to write data to the flash memory. In the body; when erasing the data in the flash memory, the electrons are pulled out of the floating gate through the tunneling oxide layer into the channel in the FN tunneling (Fowler Nordheim tu η ne 1 ing) mode. Among them, when erasing data in the FN tunneling mode, the number of electrons drawn from the floating gate is not easy to control, so it is easy to generate too many electrons drawn from the floating gate, which makes the floating The gate electrode is positively charged, which causes the phenomenon of over-erase, and makes the erased threshold voltage of the flash memory wider and the bit green generates leakage current. However, if the erasing is too serious, the channel will not pass through the control pole voltage and f will be passed, so that erroneous data will be generated. Therefore, it is customary to use additional Soft Program and over erase confirmation (〇ver_Erase
10175twf.ptd 第9頁 200426845 五、發明說明（3) V e r i f y )來補救快閃記憶體的過抹除問題，但這樣卻會發 生抹除時間之增加與硬體電路區域變大的問題。 發明内容 有鑑於此，本發明提出一種非揮發性記憶體之弱程式 (Weak P r 〇 g r a m )化方法，可修正非揮發性記憶體的過抹除 現象，並減少抹除時間，以提高非揮發性記憶體之可靠 度。 為達上述與其他之目的，本發明提出一種非揮發性記 憶體之弱程式化方法，此非揮發性記憶體至少包括有控制 閘極與基底，此弱程式化方法為在第一區間，於基底施加 第一電壓，且控制閘極施加第四電壓；其次，在第二區 間，於基底上施加第二電壓，且於控制閘極上施加第三電 壓。其中，第一電壓與第二電壓之極性相同，第三電壓與 第一電壓之極性相反。 上述第一區間，於基底施加之第一電壓為負電壓，用 以減少非揮發性記憶體之位元線的漏電流，避免因位元線 的漏電流而造成弱程式化之效率變低，並且在第一區間 中，於非揮性記憶體的汲極區接合處之接合電場處會產生 電子-電洞對。 上述第二區間，於基底施加該第二電壓以及在控制閘 極施加第三電壓，以使控制閘極與基底間之垂直電場增 加，以增加注入此非揮發性記憶體之浮置閘極之電子的數 目° 本發明在當非揮發性記憶體發生過抹除現象時，首10175twf.ptd Page 9 200426845 V. Description of the Invention (3) V r r f y) to remedy the flash memory over-erase problem, but this will increase the erase time and increase the hardware circuit area. SUMMARY OF THE INVENTION In view of this, the present invention proposes a weak program (Weak Program) method for non-volatile memory, which can correct the over-erase phenomenon of non-volatile memory and reduce the erasure time to improve non-volatile memory. Reliability of volatile memory. In order to achieve the above and other objectives, the present invention proposes a weakly-programmed method of non-volatile memory. The non-volatile memory includes at least a control gate and a substrate. The weakly-programmed method is in the first interval. A first voltage is applied to the substrate and a fourth voltage is applied to the control gate. Second, a second voltage is applied to the substrate and a third voltage is applied to the control gate in the second interval. The first voltage has the same polarity as the second voltage, and the third voltage has the opposite polarity. In the first interval, the first voltage applied to the substrate is a negative voltage, which is used to reduce the leakage current of the bit line of the non-volatile memory, and to avoid the low programming efficiency due to the leakage current of the bit line. And in the first interval, an electron-hole pair is generated at a bonding electric field at a junction of the drain region of the non-volatile memory. In the second interval, the second voltage is applied to the substrate and the third voltage is applied to the control gate, so that the vertical electric field between the control gate and the substrate is increased, so that the floating gate injected into the non-volatile memory is increased. Number of electrons ° When the erasing phenomenon occurs in the non-volatile memory, the first
10175twf.ptd 第10頁 200426845 五、發明說明（4) 先，在基底（P型井區）上施加負電壓，且控制閘極上施加 第四電壓，其次，保持先前在基底（P型井區）上所施加負 電壓，並於控制閘極上施加一正電壓。以上步驟，會於非 揮發性記憶體内的與汲極區接合處之接合電場，產生電子 -電洞對，接著在控制閘極上施加正電壓時，會增加非揮 性記憶體内垂直電場的強度，而使得電子有足夠之能量穿 過穿隧氧化層而注入到浮置閘極中。 為讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 實施方式： 第1圖繪示為一種非揮發性記憶體中快閃記憶體之剖 面示意圖。在第1圖中快閃記憶體包括基底1 0 0、隧穿氧化 層1 0 2、浮置閘極層1 0 4、閘極間介電層1 0 6、控制閘極層 1 0 8、源極區1 1 0以及汲極區1 1 2。 基底1 0 0，如熟悉此技藝者可知，基底1 0 0可為矽材 質，在基底1 0 0中設置有一井區。控制閘極1 0 8設置於基底 1 0 0上。浮置閘極1 0 4設置於控制閘極1 0 2與基底1 0 0之間， 其中，如熟悉此技藝者可知，控制閘極1 0 8與浮置閘極1 0 4 之材質可為摻雜多晶矽。閘極介電層1 〇 6設置於控制閘極 1 0 8與浮置閘極1 0 4之間，閘極介電層1 0 6之材質，如熟悉 此技藝者可知，可以是氧化矽/氮化矽/氧化矽層等，當然 此閘極介電層1 0 6之材質也可以是氧化矽層、氧化矽/氮化 矽層等。穿隧氧化層1 〇 8設置於浮置閘極1 0 4與基底1 0 0之10175twf.ptd Page 10 200426845 V. Description of the invention (4) First, a negative voltage is applied to the substrate (P-type well area), and a fourth voltage is applied to the control gate, and secondly, it is maintained on the substrate (P-type well area). A negative voltage is applied to the gate and a positive voltage is applied to the control gate. The above steps will generate the electric field at the junction between the non-volatile memory and the drain region, and then generate an electron-hole pair. When a positive voltage is applied to the control gate, the vertical electric field in the non-volatile memory will increase. Strength, so that the electrons have enough energy to pass through the tunneling oxide layer and be injected into the floating gate. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings to make a detailed description as follows: Implementation: FIG. 1 is shown as A schematic cross-sectional view of a flash memory in a non-volatile memory. In Figure 1, the flash memory includes a substrate 100, a tunneling oxide layer 10, a floating gate layer 104, an inter-gate dielectric layer 106, a control gate layer 108, The source region 1 1 0 and the drain region 1 1 2. The substrate 100 is known to those skilled in the art. The substrate 100 can be made of silicon. A well area is provided in the substrate 100. The control gate electrode 108 is disposed on the substrate 100. The floating gate 10 is located between the control gate 102 and the substrate 100. Among them, if the person skilled in the art knows, the material of the control gate 108 and the floating gate 104 may be Doped polycrystalline silicon. The gate dielectric layer 1 06 is located between the control gate 108 and the floating gate 104, and the material of the gate dielectric layer 106 can be silicon oxide / Silicon nitride / silicon oxide layers, etc. Of course, the material of the gate dielectric layer 106 can also be silicon oxide layers, silicon oxide / silicon nitride layers, and the like. The tunneling oxide layer 108 is disposed between the floating gate electrode 104 and the substrate 100.
10175twf.ptd 第11頁 200426845 五、發明說明（5) 間，穿隧氧化層1 0 8之材質，如熟悉此技藝者可知，可以 是氧化矽。源極區1 1 0與汲極區1 1 2設置於浮置閘極1 0 4兩 側的基底1 0 0中。 其中，如熟悉此技藝者可知，快閃記憶體可為η -型通 道快閃記憶體與Ρ -型通道快閃記憶體。在η -型通道快閃記 憶體中，寫入資料與抹除資料的模式包括有： (1)利用通道熱電子注入（CHEI)模式在汲極區112將電 子注入浮置閘極1 0 4中（寫入資料），並自源極區1 1 0以F Ν穿 隧模式將電子拉出（抹除資料）。 (2 )利用F Ν穿隧模式在通道區將電子注入浮置閘極1 0 4 中（寫入資料），並自汲極區以F Ν穿隧模式將電子拉出（抹 4 除資料）。 (3 )利用F Ν穿隧模式在通道區將電子注入浮置閘極1 0 4 中（寫入資料），並自通道區以FN穿隧模式將電子拉出（抹 除資料）。 (4)利用通道熱電子注入（CHEI)模式在汲極區1 12將電 子注入浮置閘極1 0 4中（寫入資料），並自通道區以F Ν穿隧 模式將電子拉出（抹除資料）。 而在ρ -型通道快閃記憶體中，寫入資料與抹除資料的 模式包括有： (1 )利用通道熱電子注入（CHEI)模式在汲極區1 12將電 子注入浮置閘極1 0 4中（寫入資料），並自通道區以F N穿隧 模式將電子拉出（抹除資料）。 (2 )利用價帶-導帶間穿隧效應引致之通道熱電子注入10175twf.ptd Page 11 200426845 5. In the description of the invention (5), the material of the tunnel oxide layer 108 is silicon oxide, as known to those skilled in the art. The source region 1 10 and the drain region 1 12 are disposed in a substrate 100 on both sides of the floating gate 10 4. Among them, as those skilled in the art know, the flash memory may be an η-channel flash memory and a P-channel flash memory. In the n-type channel flash memory, the modes for writing data and erasing data include: (1) Channel electron injection (CHEI) mode is used to inject electrons into the floating gate electrode 112 in the drain region 112. (Write data), and pull the electrons from the source region 110 in the F N tunneling mode (erasing data). (2) Use F Ν tunneling mode to inject electrons into floating gate 1 104 in the channel area (write data), and pull electrons out of drain region in F Ν tunneling mode (erasing data) . (3) Fn tunneling mode is used to inject electrons into the floating gate 104 (writing data) in the channel region, and to pull out electrons (erasing data) in the FN tunneling mode from the channel region. (4) The channel hot electron injection (CHEI) mode is used to inject electrons into the floating gate 104 (write data) in the drain region 112, and pull the electrons out of the channel region in the F N tunneling mode ( Erase data). In the ρ-type channel flash memory, the modes of writing data and erasing data include: (1) the channel hot electron injection (CHEI) mode is used to inject electrons into the floating gate 1 in the drain region 1 12 0 4 (write data), and pull out the electrons from the channel area in FN tunneling mode (erase data). (2) Channel hot electron injection caused by tunneling effect between valence band and conduction band
10175twf.ptd 第12頁 200426845 五、發明說明（6) (Band-t〇-Band tunneling induced Hot Electron in ject ion，簡稱BB HE)模式在汲極區1 10將電子注入浮置 閘極1 0 4中（寫入資料），並自通道區以F N穿隧模式將電子 拉出（抹除資料）。 接著請合併參照第2 A圖、第2 B圖以及第2 C圖，其分別 繪示本發明之較佳實施例之非揮發性記憶體中快閃記憶體 之弱程式化方法操作圖，其中包括程式化此快閃記憶體， 以及以弱程式化方法修正快閃記憶體過抹除現象之操作。 當程式化快閃記憶體時，於控制閘極1 0 8上施加例如 是9伏特至1 2伏特左右的電壓V c g，汲極1 1 2上施加例如是5 伏特至7伏特左右的電壓V d，使源極1 1 0之電壓例如是0伏 特，並使基底100(P型井區）電壓為0伏特。在此種電壓情 況下，即會產生大的通道電流（(K 2 5毫安培/記憶胞至1毫 安培/記憶胞），其中電子係由源極1 1 0端向汲極1 1 2端移 動，且在汲極112端被高通道電場所加速而產生熱電子， 其動能足以克服穿隧氧化層1 0 2之能量阻障，再加上控制 閘極1 0 8上施加有高正電壓，使得熱電子從汲極1 1 2端注入 浮置閘極1 0 4中，如第2 A圖所示。在程式化之後，由於浮 置閘極1 0 4上帶有淨負電荷，所以會令非揮性記憶體之臨 界電壓（V T )上升。而這些電子會在浮置閘極1 0 4中停留一 段很長的時間（例如在室溫中，停留時間為十年左右），除 非故意的將其抹除。 在第2 B圖中，我們利用F N抹除操作方式，在控制閘極 1 0 8上施加例如是0伏特之第四電壓，在基底1 0 0施加例如10175twf.ptd Page 12 200426845 V. Description of the invention (6) (Band-t〇-Band tunneling induced Hot Electron in ject ion, BB HE for short) mode injects electrons into the floating gate 1 10 4 (Write data), and pull out electrons from the channel area in FN tunneling mode (erase data). Next, please refer to FIG. 2A, FIG. 2B, and FIG. 2C in combination, which respectively illustrate operation diagrams of the weakly-programmed method of the flash memory in the non-volatile memory of the preferred embodiment of the present invention. This includes programming the flash memory, and correcting flash memory over-erase in a weakly programmatic manner. When the flash memory is programmed, a voltage V cg of, for example, about 9 to 12 volts is applied to the control gate 108, and a voltage V of, for example, about 5 to 7 volts is applied to the drain 1 1 2 d. Let the voltage of the source 110 be, for example, 0 volts, and make the voltage of the substrate 100 (P-well region) 0 volts. Under this voltage condition, a large channel current will be generated ((K 2 5 mA / memory cell to 1 mA / memory cell), in which the electron system is from the source 1 1 0 terminal to the drain 1 1 2 terminal It moves and is accelerated by a high-channel electric field at the end of the drain electrode 112 to generate hot electrons. Its kinetic energy is sufficient to overcome the energy barrier of the tunneling oxide layer 102, plus a high positive voltage is applied to the control gate 108. , So that hot electrons are injected into the floating gate 1 104 from the drain 1 12 terminal, as shown in Figure 2 A. After stylization, because the floating gate 1 104 has a net negative charge, so Will increase the critical voltage (VT) of the non-volatile memory, and these electrons will stay in the floating gate 104 for a long time (for example, at room temperature, the residence time is about ten years), unless Intentionally erase it. In Figure 2B, we use the FN erase operation method to apply a fourth voltage, such as 0 volts, to the control gate 108, and apply, for example, the substrate 100
10175twf.ptd 第13頁 200426845 五、發明說明（7) 是2 0伏特的正電壓，且源極區1 1 0與汲極區1 1 2為浮置的情 況下，將電子自浮置閘極1 0 4中拉出至通道中，且因我們 無法控制拉出之電子數目而造成了過抹除現象，以致浮置 閘極1 0 4中帶正電荷。 接著在第2 C圖中，為了補救過抹除之現象，我們首先 在基底1 0 0上施加例如是負2伏特左右之電壓，控制閘極 1 0 8施加第四電壓，此第四電壓例如是0伏特，而源極區 1 1 0接地，汲極區1 1 2施加例如是4至5伏特左右之電壓，此 時將會在汲極區1 1 2接合處產生電子-電洞對，且可減少位 元線之漏電流，接著，在控制閘極1 0 8上施加例如是0. 5伏 特至1 . 5伏特左右之電壓，而基底1 0 0依然施加負2伏特之 f 電壓，源極區1 1 0接地，汲極區1 1 2為4至5伏特左右之電 壓，此時因為控制閘極1 0 8所施加之正電壓，使得非揮性 記憶體之垂直電場強度增加，並使得在汲極區1 1 2接合處 產生之電子有足夠之能量穿過穿隧氧化層102進入到浮置 閘極1 0 4中。 在本發明之較佳實施例中，快閃記憶體為η -型通道快 閃記憶體。 請繼續合併參考第3圖、第4Α圖、第4Β圖以及第4 C 圖，其分別繪示本發明之較佳實施例之非揮發性記憶體中 快閃記憶體之弱程式化操作電壓時序圖與本發明之較佳實 Β 施例之非揮發性記憶體中快閃記憶體之臨界電壓分佈圖，| 其中，分別包括過抹除時之臨界電壓分佈圖與本發明之弱 程式化後臨界電壓之分佈圖，在時間t 0至t 1的範圍為外線10175twf.ptd Page 13 200426845 V. Description of the invention (7) is a positive voltage of 20 volts and the source region 1 1 0 and the drain region 1 1 2 are floating, the electrons are self-floating gates 1 0 4 was pulled out into the channel, and because we could not control the number of pulled out electrons, the over-erasing phenomenon was caused, so that the floating gate 1 0 4 had a positive charge. Then in Fig. 2C, in order to remedy the erasure phenomenon, we first apply a voltage of about 2 volts to the substrate 100, and control the gate 108 to apply a fourth voltage, such as It is 0 volts, and the source region 1 10 is grounded, and the drain region 1 12 is applied with a voltage of about 4 to 5 volts, for example, an electron-hole pair will be generated at the junction of the drain region 1 12. The bit line leakage current can be reduced. Then, a voltage of, for example, 0.5 volts to 1.5 volts is applied to the control gate 108, and the substrate 100 still applies an f voltage of negative 2 volts. The source region 1 10 is grounded, and the drain region 1 12 is a voltage of about 4 to 5 volts. At this time, because the positive voltage applied by the gate 10 8 is controlled, the vertical electric field strength of the non-volatile memory is increased. The electrons generated at the junction of the drain region 1 12 have sufficient energy to pass through the tunneling oxide layer 102 and enter the floating gate 104. In a preferred embodiment of the present invention, the flash memory is an n-type channel flash memory. Please continue to refer to FIG. 3, FIG. 4A, FIG. 4B, and FIG. 4C, which respectively illustrate the weakly stylized operating voltage timing of the flash memory in the non-volatile memory of the preferred embodiment of the present invention. Figure and critical voltage distribution diagram of flash memory in non-volatile memory of the preferred embodiment B of the present invention, | which respectively include the critical voltage distribution diagram after over-erasing and the weakly stylized invention Distribution diagram of critical voltage, outside the range from time t 0 to t 1
10175twf.ptd 第14頁 200426845 五、發明說明（8) 補救區，t 1至t 2的範圍為跟隨補救區。 第4 A圖所繪為非揮發性記憶體中快閃記憶體發生過抹 除現象時之臨界電壓分佈圖，其中臨界電壓分佈包括有外 線補救區與跟隨補救區。因此在第3圖中之t 0至11的外線 補救區中，我們在基底上施加負2伏特左右之電壓，控制 閘極施加0伏特電壓，而源極區接地，汲極區施加4至5伏 特左右之電壓後之結果，不但減少了位元線之漏電流而且 使得臨界電壓之聚合點3 0 0往右移（如第4 B圖所繪）。接 著，在第3圖中11至t 2的跟隨補償區中，我們在控制閘極 上施加0 . 5伏特至1 . 5伏特左右之電壓，而基底依然施加負 2伏特之電壓，源極區接地，汲極區為4至5伏特左右之電 壓，增強了電子注入浮置閘極中之數量，且臨界電壓之聚 合點3 0 0又繼續往右移（如第4 C圖所繪）。因此，由第4 A 圖、第4 B圖與第4 C圖可知，經過弱程式化快閃記憶體之後 可使得臨界電壓之分佈更為緊密。 綜合以上所述，本發明之非揮發性記憶體中快閃記憶 體之弱程式化方法具有下列優點： (1 )本發明之非揮發性記憶體中快閃記憶體之弱程式 化方法，可以很簡單由控制閘極之電壓來控制，以得到較 窄的抹除臨界電壓分佈。 (2 )本發明之非揮發性記憶體中快閃記憶體之弱程式 化方法，因於基底上施加負電壓，可減少熱電洞注入 S i 0 2 / S i介面的程度，且可改善非揮發性記憶體胞的可靠 度。10175twf.ptd Page 14 200426845 V. Description of the invention (8) The recovery area, the range from t 1 to t 2 is the following recovery area. Figure 4A is a diagram of the critical voltage distribution when flash memory has been erased in the non-volatile memory. The critical voltage distribution includes the external recovery area and the following recovery area. Therefore, in the outer line remedy area from t 0 to 11 in Figure 3, we apply a negative voltage of about 2 volts to the substrate, the control gate applies 0 volts, and the source region is grounded, and the drain region is applied 4 to 5 As a result of a voltage of about volts, not only the bit line leakage current is reduced, but the convergence point of the threshold voltage 300 is shifted to the right (as shown in Figure 4B). Next, in the following compensation area from 11 to t 2 in Figure 3, we apply a voltage of about 0.5 volts to about 1.5 volts on the control gate, while the substrate still applies a voltage of negative 2 volts, and the source region is grounded. The drain region is a voltage of about 4 to 5 volts, which enhances the number of electrons injected into the floating gate, and the convergence point of the threshold voltage 3 0 0 continues to move to the right (as shown in Figure 4C). Therefore, from Figures 4A, 4B, and 4C, it can be seen that after the weakly-programmed flash memory, the distribution of the threshold voltage can be made closer. In summary, the weakly-programmed method of flash memory in the non-volatile memory of the present invention has the following advantages: (1) The weakly-programmed method of the flash memory in the non-volatile memory of the present invention can It is simply controlled by controlling the gate voltage to obtain a narrower erased threshold voltage distribution. (2) The weakly-programmed method of flash memory in the non-volatile memory of the present invention, because a negative voltage is applied to the substrate, the degree of thermal hole injection into the S i 0 2 / S i interface can be reduced, and the non-volatile memory can be improved. Reliability of volatile memory cells.
10175twf.ptd 第15頁 200426845 五、發明說明（9) (3 )本發明之非揮發性記憶體中快閃記憶體之弱程式 化方法，在過抹除之補救與使抹除臨界電壓更緊密的操作 後，可減少電源之消耗。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍内，當可作些許之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者為準。 ❹10175twf.ptd Page 15 200426845 V. Description of the invention (9) (3) The weakly programmed method of flash memory in the non-volatile memory of the present invention, in the erasure of over-erase and the erasure of the threshold voltage more closely After the operation, the power consumption can be reduced. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make some changes and retouch without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. ❹
10175twf.ptd 第16頁 200426845 圖式簡單說明 第1圖繪示為一種非揮發性記憶體中快閃記憶體之剖 面示意圖； 第2 A圖繪示本發明之較佳實施例之非揮發性記憶體中 快閃記憶體之弱程式化方法操作圖； 第2 B圖繪示本發明之較佳實施例之非揮發性記憶體中 快閃記憶體之弱程式化方法操作圖； 第2 C圖繪示本發明之較佳實施例之非揮發性記憶體中 快閃記憶體之弱程式化方法操作圖； 第3圖繪示本發明之較佳實施例之非揮發性記憶體中 快閃記憶體之弱程式化操作電壓時序圖；以及 第4 A圖至第4 C圖繪示本發明之較佳實施例之非揮發性$ 記憶體中快閃記憶體之臨界電壓分佈圖。 圖式標示說明： 1 00 基 底 102 穿 隧 氧 化 層 1 04 浮 置 閘 極 1 06 閘 極 介 電 層 108 控 制 閘 極 110 源 極 區 112 汲 極 區 300 聚 合 點10175twf.ptd Page 16 200426845 Brief Description of Drawings Figure 1 shows a schematic cross-sectional view of a flash memory in a non-volatile memory; Figure 2 A shows a non-volatile memory in a preferred embodiment of the present invention Figure 2B shows the operation method of the weak programming method of the flash memory in the body; Figure 2B shows the operation method of the weak programming method of the flash memory in the non-volatile memory of the preferred embodiment of the present invention; Figure 2C FIG. 3 is a diagram illustrating a weakly-programmed method operation of a flash memory in a non-volatile memory according to a preferred embodiment of the present invention; FIG. 3 illustrates a flash memory in a non-volatile memory according to a preferred embodiment of the present invention Figures 4A to 4C show the critical voltage distributions of the flash memory in the non-volatile $ memory of the preferred embodiment of the present invention. Schematic description: 1 00 base 102 tunneling oxidation layer 1 04 floating gate 1 06 gate dielectric layer 108 control gate 110 source region 112 drain region 300 aggregation point
10175twf.ptd 第17頁10175twf.ptd Page 17
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| CN106326780A (en) * | 2016-08-18 | 2017-01-11 | 佛山中科芯蔚科技有限公司 | Physical chip fingerprint generating method and system |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI397072B (en) * | 2009-01-13 | 2013-05-21 | Winbond Electronics Corp | Method for determining native threshold voltage of nonvolatile memory |
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2003
- 2003-05-16 TW TW92113288A patent/TWI286320B/en not_active IP Right Cessation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106326780A (en) * | 2016-08-18 | 2017-01-11 | 佛山中科芯蔚科技有限公司 | Physical chip fingerprint generating method and system |
| CN106326780B (en) * | 2016-08-18 | 2019-05-17 | 佛山中科芯蔚科技有限公司 | A kind of phy chip fingerprint generation method and system |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI286320B (en) | 2007-09-01 |
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