TW200513902A - Automatic register backup/restore system and method - Google Patents

Automatic register backup/restore system and method

Info

Publication number
TW200513902A
TW200513902A TW092128105A TW92128105A TW200513902A TW 200513902 A TW200513902 A TW 200513902A TW 092128105 A TW092128105 A TW 092128105A TW 92128105 A TW92128105 A TW 92128105A TW 200513902 A TW200513902 A TW 200513902A
Authority
TW
Taiwan
Prior art keywords
backup
registers
register file
general
mode
Prior art date
Application number
TW092128105A
Other languages
English (en)
Other versions
TWI223756B (en
Inventor
Ing-Jer Huang
Yu-Wen Sung
Original Assignee
Ing-Jer Huang
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ing-Jer Huang filed Critical Ing-Jer Huang
Priority to TW092128105A priority Critical patent/TWI223756B/zh
Priority to US10/959,778 priority patent/US7143271B2/en
Application granted granted Critical
Publication of TWI223756B publication Critical patent/TWI223756B/zh
Publication of TW200513902A publication Critical patent/TW200513902A/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G06F9/30123—Organisation of register space, e.g. banked or distributed register file according to context, e.g. thread buffers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30105—Register structure
    • G06F9/30116—Shadow registers, e.g. coupled registers, not forming part of the register space
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30189—Instruction operation extension or modification according to execution mode, e.g. mode flag
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Retry When Errors Occur (AREA)
  • Executing Machine-Instructions (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
TW092128105A 2003-10-09 2003-10-09 Automatic register backup/restore system and method TWI223756B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW092128105A TWI223756B (en) 2003-10-09 2003-10-09 Automatic register backup/restore system and method
US10/959,778 US7143271B2 (en) 2003-10-09 2004-10-06 Automatic register backup/restore system and method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW092128105A TWI223756B (en) 2003-10-09 2003-10-09 Automatic register backup/restore system and method

Publications (2)

Publication Number Publication Date
TWI223756B TWI223756B (en) 2004-11-11
TW200513902A true TW200513902A (en) 2005-04-16

Family

ID=34421016

Family Applications (1)

Application Number Title Priority Date Filing Date
TW092128105A TWI223756B (en) 2003-10-09 2003-10-09 Automatic register backup/restore system and method

Country Status (2)

Country Link
US (1) US7143271B2 (zh)
TW (1) TWI223756B (zh)

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JP4311287B2 (ja) * 2004-06-25 2009-08-12 ソニー株式会社 ブートシステム及びブート方法及びこのブート方法を用いたデータ処理装置
US8321377B2 (en) 2006-04-17 2012-11-27 Microsoft Corporation Creating host-level application-consistent backups of virtual machines
KR101669989B1 (ko) * 2010-05-27 2016-10-28 삼성전자주식회사 파이프라인 프로세서 및 이퀄 모델 보존 방법
US9141389B2 (en) 2011-04-07 2015-09-22 Via Technologies, Inc. Heterogeneous ISA microprocessor with shared hardware ISA registers
US9176733B2 (en) * 2011-04-07 2015-11-03 Via Technologies, Inc. Load multiple and store multiple instructions in a microprocessor that emulates banked registers
US9645822B2 (en) 2011-04-07 2017-05-09 Via Technologies, Inc Conditional store instructions in an out-of-order execution microprocessor
EP2631786B1 (en) * 2011-04-07 2018-06-06 VIA Technologies, Inc. Load multiple and store multiple instructions in a microprocessor that emulates banked registers
US9128701B2 (en) 2011-04-07 2015-09-08 Via Technologies, Inc. Generating constant for microinstructions from modified immediate field during instruction translation
US9043580B2 (en) 2011-04-07 2015-05-26 Via Technologies, Inc. Accessing model specific registers (MSR) with different sets of distinct microinstructions for instructions of different instruction set architecture (ISA)
US9898291B2 (en) 2011-04-07 2018-02-20 Via Technologies, Inc. Microprocessor with arm and X86 instruction length decoders
US9317288B2 (en) 2011-04-07 2016-04-19 Via Technologies, Inc. Multi-core microprocessor that performs x86 ISA and ARM ISA machine language program instructions by hardware translation into microinstructions executed by common execution pipeline
US9274795B2 (en) 2011-04-07 2016-03-01 Via Technologies, Inc. Conditional non-branch instruction prediction
US9146742B2 (en) 2011-04-07 2015-09-29 Via Technologies, Inc. Heterogeneous ISA microprocessor that preserves non-ISA-specific configuration state when reset to different ISA
US9292470B2 (en) 2011-04-07 2016-03-22 Via Technologies, Inc. Microprocessor that enables ARM ISA program to access 64-bit general purpose registers written by x86 ISA program
US9032189B2 (en) 2011-04-07 2015-05-12 Via Technologies, Inc. Efficient conditional ALU instruction in read-port limited register file microprocessor
US9336180B2 (en) 2011-04-07 2016-05-10 Via Technologies, Inc. Microprocessor that makes 64-bit general purpose registers available in MSR address space while operating in non-64-bit mode
US9378019B2 (en) 2011-04-07 2016-06-28 Via Technologies, Inc. Conditional load instructions in an out-of-order execution microprocessor
US8880851B2 (en) 2011-04-07 2014-11-04 Via Technologies, Inc. Microprocessor that performs X86 ISA and arm ISA machine language program instructions by hardware translation into microinstructions executed by common execution pipeline
US20120260073A1 (en) * 2011-04-07 2012-10-11 Via Technologies, Inc. Emulation of execution mode banked registers
US9244686B2 (en) 2011-04-07 2016-01-26 Via Technologies, Inc. Microprocessor that translates conditional load/store instructions into variable number of microinstructions

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5159680A (en) * 1988-07-28 1992-10-27 Sun Microsystems, Inc. Risc processing unit which selectively isolates register windows by indicating usage of adjacent register windows in status register
US5398330A (en) * 1992-03-05 1995-03-14 Seiko Epson Corporation Register file backup queue
US5386563A (en) * 1992-10-13 1995-01-31 Advanced Risc Machines Limited Register substitution during exception processing
JP3281211B2 (ja) * 1995-01-31 2002-05-13 富士通株式会社 同期式メモリを有する情報処理装置および同期式メモリ
US5675759A (en) * 1995-03-03 1997-10-07 Shebanow; Michael C. Method and apparatus for register management using issue sequence prior physical register and register association validity information
US5701493A (en) * 1995-08-03 1997-12-23 Advanced Risc Machines Limited Exception handling method and apparatus in data processing systems
US5793944A (en) * 1996-09-13 1998-08-11 International Business Machines Corporation System for restoring register data in a pipelined data processing system using register file save/restore mechanism
US6243804B1 (en) * 1998-07-22 2001-06-05 Scenix Semiconductor, Inc. Single cycle transition pipeline processing using shadow registers
US6542991B1 (en) * 1999-05-11 2003-04-01 Sun Microsystems, Inc. Multiple-thread processor with single-thread interface shared among threads
TW494644B (en) 2001-07-09 2002-07-11 Faraday Tech Corp Method for selecting access register
GB2411254B (en) * 2002-11-18 2006-06-28 Advanced Risc Mach Ltd Monitoring control for multi-domain processors
US7024544B2 (en) * 2003-06-24 2006-04-04 Via-Cyrix, Inc. Apparatus and method for accessing registers in a processor

Also Published As

Publication number Publication date
TWI223756B (en) 2004-11-11
US7143271B2 (en) 2006-11-28
US20050081021A1 (en) 2005-04-14

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Legal Events

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