TW200519948A - Memory cell unit, nonvolatile semiconductor storage device including memory cell unit, and memory cell array driving method - Google Patents

Memory cell unit, nonvolatile semiconductor storage device including memory cell unit, and memory cell array driving method

Info

Publication number
TW200519948A
TW200519948A TW093127051A TW93127051A TW200519948A TW 200519948 A TW200519948 A TW 200519948A TW 093127051 A TW093127051 A TW 093127051A TW 93127051 A TW93127051 A TW 93127051A TW 200519948 A TW200519948 A TW 200519948A
Authority
TW
Taiwan
Prior art keywords
memory cell
diffusion layer
cell unit
impurity diffusion
semiconductor
Prior art date
Application number
TW093127051A
Other languages
English (en)
Other versions
TWI258144B (en
Inventor
Fujio Masuoka
Hiroshi Sakuraba
Fumiyoshi Matsuoka
Syounosuke Ueno
Ryusuke Matsuyama
Shinji Horii
Takuji Tanigami
Original Assignee
Fujio Masuoka
Sharp Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujio Masuoka, Sharp Kk filed Critical Fujio Masuoka
Publication of TW200519948A publication Critical patent/TW200519948A/zh
Application granted granted Critical
Publication of TWI258144B publication Critical patent/TWI258144B/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
    • H10D30/693—Vertical IGFETs having charge trapping gate insulators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/681—Floating-gate IGFETs having only two programming levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Read Only Memory (AREA)
TW093127051A 2003-09-18 2004-09-07 Memory cell unit, nonvolatile semiconductor storage device including memory cell unit, and memory cell array driving method TWI258144B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003326466A JP2005093808A (ja) 2003-09-18 2003-09-18 メモリセルユニット、それを備えてなる不揮発性半導体記憶装置及びメモリセルアレイの駆動方法

Publications (2)

Publication Number Publication Date
TW200519948A true TW200519948A (en) 2005-06-16
TWI258144B TWI258144B (en) 2006-07-11

Family

ID=34308742

Family Applications (1)

Application Number Title Priority Date Filing Date
TW093127051A TWI258144B (en) 2003-09-18 2004-09-07 Memory cell unit, nonvolatile semiconductor storage device including memory cell unit, and memory cell array driving method

Country Status (4)

Country Link
US (1) US7387935B2 (zh)
JP (1) JP2005093808A (zh)
KR (1) KR100665910B1 (zh)
TW (1) TWI258144B (zh)

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JP3679970B2 (ja) * 2000-03-28 2005-08-03 株式会社東芝 不揮発性半導体記憶装置及びその製造方法
US7208373B2 (en) * 2005-05-27 2007-04-24 Infineon Technologies Ag Method of forming a memory cell array and a memory cell array
US7282401B2 (en) 2005-07-08 2007-10-16 Micron Technology, Inc. Method and apparatus for a self-aligned recessed access device (RAD) transistor gate
US7867851B2 (en) 2005-08-30 2011-01-11 Micron Technology, Inc. Methods of forming field effect transistors on substrates
JP4822841B2 (ja) * 2005-12-28 2011-11-24 株式会社東芝 半導体記憶装置及びその製造方法
US7700441B2 (en) 2006-02-02 2010-04-20 Micron Technology, Inc. Methods of forming field effect transistors, methods of forming field effect transistor gates, methods of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, and methods of forming integrated circuitry comprising a transistor gate array including first gates and second grounded isolation gates
JP5016832B2 (ja) * 2006-03-27 2012-09-05 株式会社東芝 不揮発性半導体記憶装置及びその製造方法
US7602001B2 (en) 2006-07-17 2009-10-13 Micron Technology, Inc. Capacitorless one transistor DRAM cell, integrated circuitry comprising an array of capacitorless one transistor DRAM cells, and method of forming lines of capacitorless one transistor DRAM cells
US7772632B2 (en) 2006-08-21 2010-08-10 Micron Technology, Inc. Memory arrays and methods of fabricating memory arrays
US7589995B2 (en) 2006-09-07 2009-09-15 Micron Technology, Inc. One-transistor memory cell with bias gate
JP4768557B2 (ja) * 2006-09-15 2011-09-07 株式会社東芝 不揮発性半導体記憶装置及びその製造方法
JP5100080B2 (ja) * 2006-10-17 2012-12-19 株式会社東芝 不揮発性半導体記憶装置及びその製造方法
JP4772656B2 (ja) * 2006-12-21 2011-09-14 株式会社東芝 不揮発性半導体メモリ
JP5016928B2 (ja) * 2007-01-10 2012-09-05 株式会社東芝 不揮発性半導体記憶装置及びその製造方法
JP2008172164A (ja) * 2007-01-15 2008-07-24 Toshiba Corp 半導体装置
US7923373B2 (en) 2007-06-04 2011-04-12 Micron Technology, Inc. Pitch multiplication using self-assembling materials
JP2009094236A (ja) * 2007-10-05 2009-04-30 Toshiba Corp 不揮発性半導体記憶装置
CN101911287B (zh) * 2007-12-27 2013-05-15 株式会社东芝 半导体存储器件及其制造方法
US7906818B2 (en) * 2008-03-13 2011-03-15 Micron Technology, Inc. Memory array with a pair of memory-cell strings to a single conductive pillar
KR101052921B1 (ko) * 2008-07-07 2011-07-29 주식회사 하이닉스반도체 버티컬 플로팅 게이트를 구비하는 플래시 메모리소자의제조방법
US7910979B2 (en) * 2008-07-08 2011-03-22 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device
JP5288936B2 (ja) * 2008-08-12 2013-09-11 株式会社東芝 不揮発性半導体記憶装置
KR101115473B1 (ko) * 2010-03-02 2012-02-27 주식회사 하이닉스반도체 3차원 구조의 비휘발성 메모리 소자 및 그 제조 방법
KR101692389B1 (ko) 2010-06-15 2017-01-04 삼성전자주식회사 수직형 반도체 소자 및 그 제조 방법
KR101682666B1 (ko) 2010-08-11 2016-12-07 삼성전자주식회사 비휘발성 메모리 장치, 그것의 채널 부스팅 방법, 그것의 프로그램 방법 및 그것을 포함하는 메모리 시스템
US8681555B2 (en) 2011-01-14 2014-03-25 Micron Technology, Inc. Strings of memory cells having string select gates, memory devices incorporating such strings, and methods of accessing and forming the same
US8441855B2 (en) 2011-01-14 2013-05-14 Micron Technology, Inc. Strings of memory cells having string select gates, memory devices incorporating such strings, and methods of accessing and forming the same
JP2013058276A (ja) 2011-09-07 2013-03-28 Toshiba Corp 半導体記憶装置
US8946808B2 (en) * 2012-02-09 2015-02-03 SK Hynix Inc. Semiconductor device and method of manufacturing the same
US20150070999A1 (en) * 2013-09-11 2015-03-12 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device
US9530781B2 (en) * 2014-12-22 2016-12-27 Sandisk Technologies Llc Three dimensional NAND memory having improved connection between source line and in-hole channel material as well as reduced damage to in-hole layers
US9812462B1 (en) * 2016-06-07 2017-11-07 Sandisk Technologies Llc Memory hole size variation in a 3D stacked memory
CN111223868A (zh) * 2018-11-27 2020-06-02 钰成投资股份有限公司 半导体非挥发性存储元件结构
JP6723402B1 (ja) 2019-02-28 2020-07-15 ウィンボンド エレクトロニクス コーポレーション 抵抗変化型ランダムアクセスメモリ

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2877462B2 (ja) 1990-07-23 1999-03-31 株式会社東芝 不揮発性半導体記憶装置
US5877054A (en) * 1995-06-29 1999-03-02 Sharp Kabushiki Kaisha Method of making nonvolatile semiconductor memory
JP4226205B2 (ja) 2000-08-11 2009-02-18 富士雄 舛岡 半導体記憶装置の製造方法
JP4329919B2 (ja) * 2001-03-13 2009-09-09 Ｏｋｉセミコンダクタ株式会社 半導体メモリおよび半導体メモリの駆動方法
KR100483035B1 (ko) 2001-03-30 2005-04-15 샤프 가부시키가이샤 반도체 기억장치 및 그 제조방법
US7221586B2 (en) * 2002-07-08 2007-05-22 Micron Technology, Inc. Memory utilizing oxide nanolaminates

Also Published As

Publication number Publication date
US20050063237A1 (en) 2005-03-24
US7387935B2 (en) 2008-06-17
TWI258144B (en) 2006-07-11
KR20050028886A (ko) 2005-03-23
JP2005093808A (ja) 2005-04-07
KR100665910B1 (ko) 2007-01-09

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