TW200525849A - Snubber circuit - Google Patents

Abstract

An apparatus comprising a switching circuit and a control circuit coupled to the switching circuit. The apparatus further comprises a biasing snubber circuit coupled to the switching circuit and the control circuit to capture energy from a circuit switched by the switching circuit and to provide at least a portion of the captured energy to bias the control circuit.

Description

200525849 IX. Description of the invention: [Yun ^ Ming belongs ^ Ji Xuan Xing collar] Cross-reference of related applications This application claims priority of common pending applications, which has serial number 5 xx / xxx, xxx (lawyer memo number 200300840-1, titled "AC Current Switching Circuit") and serial numbers χχ / χχχ, χχχ (lawyer's memorandum number 200031455 1, only called "power converter"), each of which is tied to 2004 Filed January 23, 2014 and each of them is incorporated herein by reference. The present invention relates to a moderator circuit. 10 [Standard] Background of the Invention An alternating current (AC) circuit containing an inductive load contains stored energy that needs to be dissipated when the circuit is closed. If this stored energy is not taken into account when designing the circuit, the result may be many unwanted effects on the circuit and / or the environment surrounding the circuit. A significant effect on the circuit would be the increase in heat in the circuit. For example, a circuit used in a -switching device may heat up. This may result in the need for a designer to include a heat sink for a switching device. Addition—The hot slot may add to the cost of a design. 20 纟 The unsatisfactory effect of circuits with stored inductive energy is that the closing of the circuit may cause a large instantaneous discharge current, which dissipates through the rest of the circuit. These large transient currents may cause damage to other circuit components that receive the energy of the transient currents. Furthermore, his unsatisfactory effect may be a radio frequency (RF) emission exceeding the desired size 200525849. Other ranges classify devices and restrict the types of devices that can be sold. For example, in the United States, the FCC verifies a device as "Class A," or "Class B," depending on the amount of energy emitted by the device. "Class B," the device is authorized for home use, and "Class A ,," The device is limited to use in the office. [Summary of the Invention] The present invention is a device that includes: a switching circuit; a control circuit coupled to the switching circuit; and a bias voltage to the switching circuit and the control circuit. The moderator circuit biases the control circuit by capturing energy from a circuit switched by a switching circuit and providing at least a portion of the captured energy. 10 Brief description of the drawing will be due to the exemplary embodiment illustrated in the drawings Embodiments of the present invention are described in a non-limiting manner. Similar elements are referenced in the drawings with reference numerals, and in which: FIG. 1 illustrates an AC MOSFET switch according to an embodiment, including 15 antiparallel diodes. Fig. 2 illustrates a more detailed appearance of an AC MOSFET switch including intrinsic parasitic diodes of MOSFETs according to an embodiment. Fig. 3 illustrates when an embodiment using an AC MOSFET is used to control the current Current delivered to a load. 20 Figures 4A-4C illustrate a power filter and its effect on the current drawn by a load driven by an AC MOSFET switch according to an embodiment. Figure 5 illustrates a method according to an implementation. One example is an AC MOSFET switch design, which includes a mitigation device. 200525849 Figure 6 illustrates a single 1C device according to an embodiment, which includes two NMOS type MOSFET devices of an AC MOSFET switch. Figure 7 illustrates according to an embodiment An imaging device suitable for masking a device using a slow-down circuit. 5 FIG. 8 illustrates a fuse power control circuit according to an embodiment using an AC MOSFET switch including a regenerative slow-down device. The figure illustrates a combined moderator and bias circuit according to one embodiment. Figure 10 illustrates a combined moderator and bias circuit 10 circuits according to other embodiments. Figure 11 illustrates a combination moderator according to other embodiments. And a bias circuit. Fig. 12 illustrates a regenerative moderator according to one of the other embodiments. Fig. 13 illustrates a regenerative moderator according to one of the other embodiments with 15 additional DC Fig. 14 illustrates a regenerative retarder for use with a DC-DC converter according to an embodiment. [Embodiment 3 Detailed Description of Preferred Embodiments 20 Although a specific embodiment will be illustrated and described herein However, those skilled in the art will appreciate that the specific embodiments shown and described may be substituted by various alternatives and / or equivalent implementations without departing from the scope of the invention. This application is intended to cover the embodiments discussed herein Any modification or change. Therefore, it is obviously intended that the present invention is limited only by the scope of patent applications. 200525849 The following discussion is presented in the context of a MOSFET device. It is understood that the principles described herein can also be applied to other transistor devices. Reference is now made to FIG. 1 which illustrates an AC MOSFET switch 110 including an antiparallel diode 112 114 according to an embodiment. For the 5 MOSFETs 142 144, the source of the MOSFET device is coupled on the interface 102. In one embodiment, the MOSFETs 142 144 are power MOSFETs. In addition, the gate is electrically coupled to the junction surface 104. These couplings assist two MOSFETs 142 144 to operate as a single AC MOSFET switch. Thus, by applying a gate-to-source voltage of 10 VGS greater than the threshold voltage VTH to the two MOSFETs 142 144, both MOSFETs conduct current 120. Also illustrated in FIG. 1 are two diodes 112 114. These diodes 112 114, which may be parasitic or obvious, are antiparallel to their individual MOSFETs. As explained in further detail below, these diodes 112 114 can be utilized to bypass the intrinsically antiparallel diodes of the MOSFETs. Thus, as illustrated, the anodes of the diodes 112 to 114 are coupled to the sources of individual MOSFETs of the diodes, and the cathodes are coupled to the individual drains. Figure 1 also illustrates an AC MOSFET used in controlling power to a load. As previously mentioned, the AC MOSFET switch 110 includes two MOSFETs 142 144. The AC MOSFET switch 110 controls the current 120 through the load 130 20. This can be accomplished by the switch control circuit 140, which applies a gate-source voltage to the two MOSFETs 142 144 forming the AC MOSFET switch 110. In the illustrated embodiment, the charging pump bias circuit 150 is connected from the live (L) 172 and neutral (N) 174 lines of the AC power supply to supply current to the switch control circuit 140. 200525849 FIG. 2 illustrates a more detailed appearance of an AC MOSFET switch using one of P-type MOSFETs including intrinsic parasitic diodes 232 234 of MOSFETs 242 244 according to an embodiment. Also illustrated is the antiparallel diode 212 214, which can be used to bypass the intrinsic antiparallel diodes 232 5 234 of the MOSFETs. Note that the sources of the two MOSFETs 242 244 are coupled 204 to each other. In addition, the gates of the two MOSFETs 242 244 are coupled to each other 206. When VSG 280 is applied which is less than a threshold voltage VTH, MOSFETs 242 244 will be "closed" and the internal reverse biased PN junction will substantially prevent current from flowing through the MOSFETs. When a voltage VSG 280 greater than a threshold voltage VTH is applied to the common source 10 poles, and the gates of the MOSFETs 242 244 are turned on to assist the current flow through the AC MOSFET switch. Note that the current will flow in the reverse direction in the MOSFET 242 or 244 depending on the polarity of the AC voltage source. That is, in the reverse direction, as is generally used in a DC circuit, that is, the drain-to-source in an N-type MOSFET, or the source-to-drain in a P-type MOSFET. Reverse current flow does not cause problems because the MOSFET transistor is actually a bidirectional device, that is, once the correct gate voltage is applied and the conduction channel is formed, current can flow from sink to source or source to sink . Generally, during the reverse polarity across the source / drain of a MOSFET, the internal PN junction represented by parasitic diodes 234 and 232 in Figure 2 will eventually open, allowing current to flow 20 271 . Note that the parasitic diodes 234 and 232 are not separated from the MOSFETs 244 and 242; for example, the parasitic diode 234 is a PN junction, which is part of the structure of the transistor 244. Once the gate voltage is removed, the parasitic diode is turned on during the reverse current flow, which makes a single MOSFET unsuitable for controlling the AC current 271 273. The common source of MOSFETs 242 and 244 shown in Figure 2 200525849 configuration results in one of the parasitic diodes in a reverse biased state, which substantially prevents current from flowing through the parasitic when the MOSFETs are in one of the conducting or non-conducting states Diodes 232 234. Referring again to Figure 1, the switch control circuit 14o and the charging pump circuit 1505 are used to provide control of the application of the voltage applied to the gates of the MOSFETs 142 144. In the illustrated embodiment, the switch control circuit 14o may be an externally controlled pulse width modulation circuit. In the illustrated embodiment, the charging pump 150 uses an AC line to supply the power of the pulse width modulation circuit. In addition, the frequency of the modulated control signal may be fixed, and at the same time, the duty cycle 10 of the modulation is used to determine the power to be transmitted to the load 130 as described below. In one other example, the gate and source of the AC MOSFET can be driven by a circuit that has a small on-time and is combined with a variable frequency to determine the power to be transmitted to the load 130. Figure 3 illustrates the current delivered to a load when one embodiment of an AC MOSFET is used to control the current. For example, as discussed above in relation to FIG. 丨, the switch control circuit 1405 may be a pulse width modulation circuit. In such a case, the power delivered to the load 130 can be controlled by changing the duty cycle of the pulse control signal. Figure 3 illustrates an exemplary input voltage 310 from the live and neutral lines. Also indicated in the dark shaded area 32 is the period during which the AC MOSFET switch 110 is turned on to allow current to flow through the load 30. The voltage 310 and the current 320 are normalized so that they share a common wave packet. Thus, in the illustrated embodiment, a 50% duty cycle signal driving the gate-to-source voltage will result in an effective power of one half of the total power available to the load. By using a pulse width modulation technology 200525849, the magnitude of the power delivered to the load can be adjusted by controlling the width of the pulses generated by the pulse width modulation of the switch control circuit. The equation for the power transfer from management to the load is: 5 where Vrm ^ AC rms voltage of the power source, R is the resistance of the load, and d is the duty ratio of the pulse width modulator that drives the AC MOSFET. By checking this equation 'the power transferred to the load is a linear function of the duty ratio of the pulse width modulator. When the duty ratio is zero, the load is zero power, and when the duty ratio is 1, it is at the maximum power. 0 In another embodiment, the gate and source of the AC MOSFET switch are driven by a circuit that has a minimum on-time and combines a variable frequency oscillator (VFO) to transmit power to the load 130. P = V2 ^ -RxfxTmin 15 determined by the following formula, where V is the rms voltage of the AC power supply, R is the resistance of the load, f is the frequency of the VFO driving the AC MOSFET, and Tmin is the minimum allowable on-time. By inspection, this equation shows that the power transferred to the load is a linear function of the frequency of VF0. When the VFO frequency is 0, the load is at zero power. When the frequency of VFO is equal to or less than the minimum allowable on-time Tmin, 20 is at the maximum power. The above example operation is to assist the switching of AC current at a relatively high frequency. Good for switching currents at relatively high frequencies. Outside the audio range (eg greater than 20KΗζ) the switching frequency can be used to reduce human factors issues related to auditory switching 200525849 noise. Other advantages of operation at higher frequencies may be reductions in switching and conduction losses. Implementations that operate at relatively low frequencies spend more time in the linear region of operation. It takes a lot of time during the switching to consume a significant amount of extra energy in the linear mode, because the relatively slow conversion is done through this linear region. In addition, because of the relatively low voltage drop associated with revealing switching of the AC current, the product of the current flowing from the voltage drop across the device consumes less energy. In addition, the above ACMOSFET switching circuit does not introduce significant harmonic terms into the AC current. This reduces the costs associated with filtering these harmonics to meet international regulatory requirements. FIG. 4A illustrates an input circuit to an AC MOSFET switch according to an embodiment. Illustrated is a filter stage 410 to provide a high frequency connection to ground for any transient or conducted emissions that occur across the input. Also explained is a filter stage 420 to provide smoothing of the AC current 15 drawn by the load 43. The effect of this filter is to smooth the multi-harmonic current drawn by the pulse width modulated or VFO driven load, so that the power source experiences a continuous current flow without actually having a harmonic current content. In the Bayesian example, the switch control circuit 430 switches the current 472 to the load, as illustrated in Figure 4B. During the switching time, assuming a purely resistive 20-resistance load, the current 472 passing the load 430 will follow the supplied hot-line voltage, that is, it will be in phase. When the switch is closed, the current delivered to the load will drop to zero 474. Thus, as can be seen, when the switch is turned on and off, there will be a dramatic shift or step-down in the current drawn by the load. Step changes in these currents represent unwanted currents on AC power sources. 12 200525849 Harmonics, which may exceed regulatory limits. To solve this problem, a filter stage 420 is added to the circuit. Figure 4 (: The diagram illustrates the current drawn by the switching load on the live and neutral connection from the AC% source as a result of the filter 42 °. When the switch is off, the filter stage 420 makes the current drawn by the load 43 ° Current 476 is flat / nephrized. In the case where the switch is driven by a pulse width modulator, the total instantaneous current drawn by the circuit can be the sum of the instantaneous values of the basic current and the ripple current.

Vs) Ra and middle fc are; the wave considered is the resonance frequency of stage 420, fs is the blade switching frequency of the pulse width modulator, f0 is the frequency of the AC power supply, and d is the duty cycle of the pulse width modulator, V Is the peak source voltage, and R is the load resistance 43. With the direct verification of this equation, it is noted that as the switching frequency of the pulse width modulator increases, the resulting AC current waveform on the connection of the live and neutral wires is dramatically smoothed. FIG. 5 illustrates an AC MOSFET switch design including a mitigation device 580 according to one embodiment. Mitigation device 58 is used to consume the moon dagger stored in the circuit. The stored energy in the f; path exists because of different factors related to the circuit ... the parasitic electrical inductance associated with the wiring that provides AC current, the parasitic inductance in the component wires, and the parasitic inductance in the load itself inductance. The 'moderator' design is designed to capture a portion of the stored energy in a circuit when the circuit is closed. These retarders are designed to reduce circuit resonance in particular. However, these retarders are not designed to consume all energy; they are only designed to consume enough energy to reduce resonance and resonance "over" voltages that may otherwise occur. In order to dissipate all the energy in the circuit,

This capacitor size is expected to avoid the resonance of the circuit only ^ However, the remaining energy is dissipated through the heat in the switching element or as a RF chirp emission. In order to avoid this heat or RF emission, a _larger_ retarder circuit can be used. In order to make the moderator consume almost all the stored energy of the circuit, the energy mixed by the moderator should be equal to the energy stored in the circuit's inductance.

1/2 LI = 1/2 CV

1 = 1 / 2CV, where I = V / R 1/2 L (V / R) 2 =: i / 2 CV2 Solving C we find that: In this way, the capacitor used is directly related to the value of parasitic inductance. Dissipating heat can be unsatisfactory because it can cause damage to the circuit. However, adding a heat sink may increase the cost of the design. In addition, the generation of RF emissions may be unsatisfactory because it may cause an unfavorable level during the rF inspection procedure for devices containing AC MOSFET switches. To protect against RF emissions, a mask for RF emissions can be provided. However, adding a mask to the ground 200525849 may increase the design cost. Thus, in one embodiment, the capacitor, which is part of the moderator illustrated in Figure 5, is designed to capture the stored energy that is generally associated with the AC MOSFET switch in the circuit. In this way, the design of the rF mask and the design of any heat-consuming device can be reduced. FIG. 6 illustrates a single integrated circuit (IC) device 600, which includes two NMOS-type MOSFET devices of an AC MOSFET switch according to an embodiment. In another embodiment, two PMOS-type MOSFET devices can be used in the construction of an ac MOSFET. In retrospect, two of the 10-source MOSFETs are logically coupled to each other in the AC MOSFET switch. By fabricating two MOSFETs in a single package on a 1C, a MOSFET can share a common source region 61 on a 1C. In the embodiment illustrated in FIG. 6, a common source region 61 is implanted into a wafer containing an AX MOSFET switch. The sharing of the common source region 61 allows 15 to use a single source wire from a package containing two MOSFETs of an AC MOSFET switch. This, in turn, can result in reduced conduction resistance, since a source wire and the connection parasitics associated with the source wire are eliminated, such as the ohmic resistance from the wafer to a packaged wire. For example, in one embodiment, eliminating a source lead can reduce the impedance by one thousandth of an ohm, corresponding to the impedance associated with one of the leads to a 20 AC MOSFET switch. 70 thousandths of an ohm can be a significant portion of the total resistance associated with an AC MOSFET switch. For example, assume that for each MOSFET in an AC MOSFET switch, 100 ohms 2 Rdson. Thus, with a resistance of 70 thousandths of an ohm for each wire of the source and the drain, the total path impedance across the source and the drain 15 200525849 is 240 thousandths of an ohm. The two separate series devices have an effective resistance of 480 parts per million ohms through the aC MOSFET switch. Recall that during the switch off time, the external source wire in the AC MOSFET is used to apply the gate bias and as a conduction path for a particular type of retarder application. By design, the external source connection 61 has a very low current flow and does not introduce a series resistance to the AC MOSFET switch during the switch on-time. This fact allows the on-resistance of the AC MOSFET switch to be reduced by 14 thousand ohms, or to reduce the effective resistance by 30% by using a common source region on the wafer of the AC MOSFET and eliminating a wire. Because the power consumed is directly related to electrical resistance, this results in a 15% reduction in power loss for the described embodiment. Manufacturing the AC MOSFET switch on a single wafer also allows the separation of one of the existing gate extremes to be eliminated. The result of the common source region and the eliminated gate extremes is a four-pin device with two high current drain connections and two lower current gate and source connections. One pin of the four-pin device is coupled to 15: each of M0SFETs2 gates. The other pins are coupled to a common source region, and each of the two remaining pins is coupled to a different one of the drains. As such, an embodiment of an AC MOSFET switch design has been disclosed. This design generally allows faster operation of AC MOSFET switches, especially operations above the audio frequency spectrum (for example, greater than 20kHz). AC MOSFET switching operation generally uses higher frequencies, which subsequently allows the device to be used in a wide range of AC power control, thus reducing the use of rectification and the resulting induction of harmonics to the power line. These advantages reduce the use of expensive filtering and allow better operation in a human environment, such as a home or office environment. The design can also allow a single IC for many AC MOSFET switches in later use. This can reduce the number of endpoints, thus reducing losses due to lead resistance. While describing different circuit elements, those skilled in the art will recognize that equivalent circuit elements can be utilized without altering the spirit of the disclosed embodiments. For example, where a single bias capacitor is used, multiple parallel 5 capacitors can be used to obtain a desired effective capacitance. "Capacitor, when used herein (in the description and in the scope of the patent application) includes the general meaning understood by those skilled in the art, that is, an electronic device that has the ability to store charges, and is configured to provide the ability Other devices or combinations of devices that store charge 0 1 10 The bias circuit of the control circuit used to drive the AC MOSFET switch can be combined with the moderator circuit. By combining the bias circuit and the moderator circuit, it can be further slowed down The wasted power in the suppressor circuit can be used to drive the control circuit. Figure 7 illustrates an imaging system 700 according to an embodiment, which is adapted to mask a device using a moderator circuit. As explained, for the embodiment The imaging system 700 includes a processor / controller 702, a memory 704, an imaging engine 706, and a communication interface 708, which are coupled to each other through a bus 71. The imaging engine 706 includes a printer for heating and printing toner to In addition to the heating subsystem 720, the imaging subsystem may include other induction heating elements or induction motors. The imaging engine 706 is similar to many imaging systems 2〇 to those, such as available from HP Hewlett Packard Corp. of Palo

Alto, CA winner. The heating subsystem 72 is connected to an AC power source through an interface 73. The heating subsystem 72 may utilize a moderator circuit, as described in this description. The processing state 702, combined with other parts of the imaging system 700, can perform a variety of different control functions of the heating system 720. For example, in one embodiment, the processor controls the power management of the heating subsystem 720 to intelligently turn off the heating subsystem when the heater is not in use. In addition, the processor 702, the memory 704, the imaging engine 706, the communication interface 708, and the bus 710 represent these components in a wide range. FIG. 8 illustrates a heater power control circuit according to an embodiment using an AC MOSFET switch 840 including a regenerative retarder “ο. Control circuit 82 such as a linear analog pulse width modulator (PWM) 〇 An AC MOSFET switch 840 is used to control the rate of work transmitted to a heating element 83. When the control circuit 820 turns off the ACMOSFET switch 840, the current is diverted through the regenerative retarder 810. The regenerative retarder 810 includes generating a bias voltage A circuit with a voltage of 825. Thus, in this embodiment, the control circuit §20 is biased by a regenerative retarder 810. Thus, it will be additionally used as a lossy retarder, such as a resistor and 15 electrical valleys for retardation. A significant portion of the energy consumed by the heat in the device can be "recaptured" and utilized. As illustrated in Figure 8, the energy can be used to bias the control circuit 820. In other words, the moderator and bias The circuits can be combined into a single circuit. In addition, depending on the design of the moderator and the bias voltage available from the moderator, 'other items in the system' are powered by the moderator circuit. For example, 'in a device that consumes a large amount of heat that requires a cooling fan, the cooling fan can be powered by a regenerative retarder in addition to or in the control circuit. Figure 9 illustrates a regenerative retarder according to an embodiment. M0SFETs Ql 942 and Q2 940 and their corresponding apparently antiparallel transistor diodes 928,918 18 200525849 form an AC MOSFET switch, as previously described. When the current 1 99 ° flows as illustrated, and 仏 942 and Q2 940 When the circuit is closed, for example, when the circuit enters a closed state, the current is diverted through the energy storage device Q 91〇 and the capture circuit R 912 and 4 914. This rotation causes the charge to be established in an energy storage device 5 and the bias capacitor C3 916 The bias capacitor c3916 provides a bias voltage between a bias node 905 of a bias circuit and a ground terminal 950. Then the current continues to pass through the apparent transistor diode 918 of Q2 940. When 仏 942 and When the q2 940 is opened again, the q 910 is reset. That is, by flowing through the 仏 942, the mountain 970 to discharge the 10 charges stored on the Ci 91〇, and then consumed in the heart 912. The retarder / bias circuit Symmetrical allowance The charge follows the two directions of AC flow. When the current 990 is reversed and 942 and (^ 2 940 are closed), the flow passes through the devices C2 920, R2 922, d3 924, charge C3 916, and then passes through Transistor diode 928. When 仏 942 and Q2 940 are turned on by 15 again, C2 920 is reset and the charge stored in capacitor C2 920 flows through

MOSFET Q2 940, d4 972 and consumed in ruler 2 922. As such, during the off period of the AC MOSFET switch, charge is supplied to the bias capacitor C3 916, resulting in a bias voltage at the bias node 905. The voltage between the ground terminal 950 and the bias node 905 provides a bias to the control circuit. 20 Figure 1 illustrates a regenerative moderator according to an embodiment. Capacitor C3 1016 stores the charge that can be used to bias a control circuit. When the MOSFETs Q1042 and ^ 2 1104 are turned off, a current I 1090 flows through C! 1010 and Tun 1014 and charges c3 1016. The current continues to pass through the apparent transistor diode 1018 of Q2 1040. Implementation here In the example, there is no electricity 19 200525849 resistor in the shutdown circuit to dissipate energy. In this way, more energy can be transferred to charge C3 1016 during the shutdown. When the MOSFETs Q〗 1042 and Q2 1040 are turned on, Q 1010 passes through 1042, Mt. 1070 * 1 ^ 1012 to reset. When the current i flows 1090 in the reverse direction, 5 similar results occur through the slowing / biasing devices C2 1020, R2 1022, d4 1072, apparent transistor diodes 1028 and d3 1024. Figure 11 illustrates a regenerative retarder according to one of the other embodiments. By modifying the embodiment of Figure 10 and replacing the resistors with inductors b 1113 and L2 1123, energy losses can also be greatly reduced during reset Allows a considerable 10 mitigating energy to be captured and charged to C3 1116. When 1142 and (^ 2 1140 are turned off, the capacitor c3 1116 is charged through C2 n2〇 and Shan n24 or Ci m (^ d2 1114, as previously discussed , Depending on the direction of the current through the MOSFETs during the off time Assume that when 仏 Π42 and Q21140 are turned on, the current flows I 1190. The charge stored on q 1110 causes the current to flow through ^ 15 1113. The Li Ci circuit will resonate at a frequency that can be expressed by liC1 In order to provide adequate retarder reset, the resonance frequency of LI c1 * L2 C2 can be selected so that the frequency is at least as high as the minimum period expected for conducting Q1 1142 and Q2 114. 20 When Ql 1142 and Q2 114 〇 When turned on, the resonance result of LI C1 caused an attempt to reverse the voltage on C 1110. When the voltage on the anode to d21114 reached a potential energy just above the bias node H05, d2 1114 Open, allowing extra energy to hit C3 1116. This embodiment advantageously reduces the amount of energy loss by 20 200525849 by removing the resistor from the moderator / bias circuit shutdown and reset operations. Again in The illustration in Figure 11 is the retarder of the active device of the retarder / bias circuit. The circuit contains many diodes which can themselves be sources of conduction and radiation to the circuit. To help reduce these conduction and 5 shots to slow RC The circuit 1180 is placed across the diode. In one embodiment, a fast switching diode is used in the retarder / bias circuit. For example, 'with a switching time of 10ns or faster A polar body can be used in one embodiment. When the AC MOSFET is switching, the magnitude of the bias current 10 provided by the circuit will be relatively high compared to when the AC MOSFET is not switching. For example, suppose an AC MOSFET switch is operating at 28.5kHz and a live-wire voltage of 120 \ ^] ^ and (1: 1 and (1; 2 are 0.01 Buffaradi capacitors. Each of the retarder capacitors effectively "sees" The RMS voltage across it, and Ci 1110 sees the first half cycle and C21120 sees the second half cycle. The retarder 15 capacitor is being charged and discharged at the switching frequency. The current available to charge c3 can be calculated as follows: Q = ixt = cxv i = cx ^ / = cx vxf

i = (0.01xl06) (120) (28500) i = 34.2 mA 2 0 This value can be doubled in an embodiment using an inductor to invert the voltage of the retarder capacitor during the retarder reset. However, when the AC MOSFET switch is idle, the switching of the retarder circuit occurs with, for example, a 50-60 Hz line frequency. In this case, the capacitor C3 1116 that sees the peak of v will have a much smaller current to charge it: 21 200525849

i = (0.01x106) (120x V2) (60) i = 0.10mA 笫 12 illustrates a regenerative retarder according to one embodiment. In this embodiment, two series resistors r3 5 1282 and R4 1284 are added along a full wave rectifier 1280. These components can be used to help provide additional DC bias. When the circuit is idle, this additional DC bias may be useful in supplying additional charge to bias the piezoelectric valley to C3 1216. For example, as mentioned previously, false

With a 120 VACRMS power source, resistors r3 1282 and R4 1284 at 60kQ provide an additional:

10 (120) / (60k) = 2.0mA So, by putting the full-wave rectifier 1280 and the series resistor r3 1282 and R4 1284 into the circuit as explained, when the AC MOSFET switch is idle, the valley is C3 1216 is available to provide a bias current to the control circuit from 0.1 mA booster to 2.1 mA. 15 Figure 13 illustrates a regenerative retarder with additional DC bias according to an embodiment. In the circuit, except that C3 1316 is charged by capacitor core 131 (^ nC: 2 132〇), the currents of resistors R! 1388 and R2 1386 are used to provide increased current to charge C3 1316. Similar to the calculation above, For R! 1388 and R2 1386, a 60 kQ resistor result was used to obtain an additional current of 2.0 mA of 20 mA. This increases the bias current to 2.imA. Also illustrated in Figure 13 t is the use of a Zener 2 The polar body 1384 straddles C3 1316. The energy stored on C3 1316 can cause the voltage at Vbias node 1305 to increase beyond the size of noon allowed by one of the control circuits of a regenerative retarder bias. In this case, by placing a Zener diode 1384 with a correct breakdown voltage of 22 200525849 across the capacitor device ㈡ 1316, a correct voltage value can be maintained at the bias node 1305. For example, If the vBIAS value of a 13 volt control circuit is required, a Zener diode with a 15 volt breakdown voltage can be placed on the transcapacitor device q i3i6 5 to ensure that the voltage across the qi316 does not exceed 15 Volts. In another embodiment, one The resistor is placed across A 1316 to help maintain the voltage across C3 1316. In other embodiments, an avalanche-polar body is used to ensure that a correct voltage value can be maintained at the bias node 1305 . While the previous embodiment illustrates a 10 regenerative retarder for use with an AC MOSFET switch, the regenerative retarder can be used in other configurations. Figure 14 illustrates a DC-DC converter according to an embodiment The regenerative retarder used in the above. The one illustrated in Figure 14 is an electrically isolated flyback converter. The power switch 1430 is used to control the power transmission to the load 1425. The power switch 1430 is controlled by the control circuit 1470 The control circuit 15 1470 is biased by the bias node 1405 charged by the regenerative decelerator 1440. While explaining an electrically isolated flyback converter DC switching circuit connected to the regenerative deceleration, such as boost And other DC switching circuit types of the step-up and step-down converter. When the power switch 1430 is turned off, the regenerative retarder 1440 is used to capture 20 times the energy stored in the galvanically isolated converter. When When the rate switch 1430 is turned off, the current ϊ 1490 flows through Q 141〇 and Shan 1414 and charges c3 1416 and the corresponding bias node 1405. When the power switch 1430 is turned on, C〗 1410 passes through the power switches 1430, d2 1419 And L〗 1418 to reset. During low-frequency operation of the DC-DC switching circuit, provide sufficient bias of 23 200525849 sufficient current may not be provided by C〗 1410. As such, resistor Ri 1412 is coupled across Q 1410 to provide additional bias. The appropriate value of & 1412 to provide a sufficient bias current for the bias node 1405 may be application dependent. Thus, a unique method for providing a bias voltage for a control circuit is provided. Although specific embodiments have been illustrated and described herein, those skilled in the art will appreciate that many other and / or equivalent embodiments can be substituted for those disclosed herein without departing from the spirit and scope of the scope of patenting. This application is intended to cover any adaptations or variations of any of the preferred embodiments discussed herein. Therefore, it is intended that the present invention is limited only by the scope of patent application and equivalents10. c Brief Description of Drawings 3 FIG. 1 illustrates an AC MOSFET switch according to an embodiment, which includes an antiparallel diode. FIG. 2 illustrates a more detailed appearance of an AC MOSFET switch including the essential diodes of the MOSFETs according to an embodiment. Figure 3 illustrates the current being delivered to a load when an embodiment using an AC MOSFET is used to control the current. Figures 4A-4C illustrate a power filter and its effect on the current drawn by a load driven by an AC MOSFET switch according to an embodiment. FIG. 5 illustrates an AC MOSFET switch design according to an embodiment, which includes a mitigation device. FIG. 6 illustrates a single 1C device according to an embodiment, which includes two NMOS-type MOSFET devices of an AC MOSFET switch. 24 200525849 FIG. 7 illustrates an imaging device according to an embodiment, which is adapted to cover a device using a slowing circuit. FIG. 8 illustrates a fuse power control circuit according to an embodiment using an ACMOSFET switch including a regenerative retarder. 5 Figure 9 illustrates a combined moderator and bias circuit according to an embodiment. Figure 10 illustrates a moderator and bias circuit according to a combination of other embodiments. Fig. 11 illustrates a moderator and bias circuit according to a combination of other embodiments. Figure 12 illustrates a regenerative moderator according to one of the other embodiments. Figure 13 illustrates a regenerative moderator with additional DC bias according to one of the other embodiments. Fig. 14 illustrates the use of a regenerative retarder with a DC-DC converter according to an embodiment. [Description of symbols of main components] 102, 104 ... Interface 110 ... Switch 112, 114 ... Diode 120 ... Current 130 ... Load 140 ... Switch control circuit 142, 144 ... MOSFETs 150 ... Charging pump bias Voltage circuit 172 ... live line 174 ... neutral line 212, 214 ... diodes 232, 234 ... parasitic diodes 242-244 ... MOSFETs 280 ... Vsg 271, 273 ... AC currents 410, 420 ... filters Class 25 200525849 430, 440 ... Load 472, 476 ... Current 530 ... Load 573 ... Capacitor 577 ... Resistor 580 ... Slowing device 600 ... Single integrated circuit (1C) device 610 ... Common source Pole area 620 ... substrate 700 ... imaging system 702 ... processor 704 ... memory 706 ... imaging engine 708 ... communication interface 710 ... bus 720 ... including AC with regenerative charge pump retarder MOSFET switch heating subsystem 730 ... Interface 810 ... Regenerative retarder 820 ... Control circuit 825 ... Bias voltage 830 ... Resistor 840 ... Switch 905 ... Bias nodes 940, 942 " .MOSFETs 918, 928 ... Diode 950 ... Ground 990 ... Current 910 ... Energy storage device 9 12, 914 ... Capture circuit 916 ... Bias capacitors 970, 972 ... Diodes 1010, 1016, 1020 ... Capacitors 1012, 1022 ... Resistors 1014, 1070, 1072, 1024 1028 ... Diodes 1040, 1042 ... Transistors 1140, 1142 ... Transistors 1110, 1116, 1120 ... Capacitors 1190 ... Currents 1114, 1124, 1172 ... Diodes 1113, 1123 ... Inductors 1105 ... Node 1180 ... RC retarder circuit 1216 ... 1282 ... Resistor 1280 ... Rectifier 26 200525849 1284 ... Resistor 1316, 1320 ... Capacitor 1386 ... Resistor 1384 ... Diode 1410, 1416 ... Capacitor 1414 ... Diode 1412 ... Resistor 1490 ... Current 1430 ... Transistor 1470 ... control circuit 1425 ... load 1405 ... bias voltage 1440 ... regenerative retarder 27

Claims (1)

200525849 X. Patent application scope: 1. A device comprising: a switching circuit; a control circuit coupled to the switching circuit; and 5 a bias moderator circuit coupled to the switching circuit and the control circuit to switch from one to the other Circuit switching circuits capture energy and provide at least a portion of the captured energy to bias the control circuit. 2. The device according to item 1 of the patent application, wherein the switching circuit includes a DC switching circuit. 10 3. The device of claim 1 in which the switching circuit includes an AC switching circuit. 4. The device as claimed in claim 3, wherein the AC switching circuit includes: a first field-effect transistor (FET) having a first source, a first gate, and a first electrode; 15 A second FET having a second drain, a second source coupled to the first source, and a second gate coupled to the first gate; a first diode body having A first anode coupled to a first source and a first cathode coupled to the first drain; and a second diode having a second anode 20 coupled to a second source and a second anode A second cathode coupled to the second drain. 5. The device as claimed in claim 3, wherein the bias moderator circuit comprises: a first and second series resistor / capacitor pair, which are correspondingly coupled to one of the first and second fields of the AC switching circuit One of the first effect transistor (FET) 28 200525849: a first and a second electrode; a first diode coupled between a first source of the first FET and a first series resistor / capacitor pair, One anode of the first diode is coupled to the first source and one cathode of the first diode is coupled to the first 5 series resistor / capacitor; a second diode is coupled to the second FET Between a second source and a second resistor / capacitor pair, one anode of the second diode is coupled to the second source and one cathode of the second diode is coupled to the second series resistor / capacitor pair 10 a third diode, one anode of the third diode is coupled to the cathode of the first diode; a fourth diode, one anode of the fourth diode is coupled to the second anode A cathode of a diode and a cathode of one of the fourth diodes is coupled to a cathode of a third diode; and 15 A capacitor is coupled between the coupling cathodes of the third and fourth diodes and the first and second sources, and the first and second sources are joined together. 6. The device of claim 3, wherein the bias moderator circuit includes: a first terminal of a first capacitor and 20 a first terminal of a second capacitor, which are correspondingly coupled to the AC switch A first and a second field effect transistor (FET) of the circuit, a first and a second drain; a coupling between a second terminal of the first capacitor and a first source of the first FET A first series linear device / diode pair; a second series linear element / diode pair coupled between a second terminal of a second capacitor and one of the second FETs 29 200525849 second source; A first diode in which one anode of the first diode is coupled to the second end of the first capacitor; a second diode in which one of the second diodes is anode coupled to the fifth of the second capacitor Two terminals and one cathode of the second diode is coupled to one cathode of the first diode; and a bias voltage between the coupling cathode coupled to the first and second diodes and the first and second sources A capacitor, the first and second sources are coupled together. 7. For the device in the sixth item of the patent application, wherein the first series linear device / two 10-pole pair includes a first inductor and a third diode, and the second series linear device / diode pair includes A second inductor and a fourth diode. 8. The device of claim 7 in which the anodes of the third and fourth diodes are coupled to a source, and the cathodes of the third and fourth diodes are correspondingly coupled to the first and second diodes. Inductor. 15 9. The device according to item 6 of the patent application, wherein the bias moderator circuit further comprises: a first resistor, wherein a first terminal of the first resistor is coupled to a first terminal of the first capacitor, And a second terminal of a first resistor is coupled to a second terminal of the first capacitor; and 20 a second resistor, wherein a first terminal of a second resistor is coupled to a first terminal of the second capacitor And a second terminal of one of the second resistors is coupled to a second terminal of the second capacitor. 10. The device of claim 3, further comprising a load coupled to the AC switching circuit. 30