TW200537621A - Dielectric layer for semiconductor device and method of manufacturing the same - Google Patents
Dielectric layer for semiconductor device and method of manufacturing the same Download PDFInfo
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- TW200537621A TW200537621A TW094102747A TW94102747A TW200537621A TW 200537621 A TW200537621 A TW 200537621A TW 094102747 A TW094102747 A TW 094102747A TW 94102747 A TW94102747 A TW 94102747A TW 200537621 A TW200537621 A TW 200537621A
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- Prior art keywords
- layer
- oxide
- dielectric
- metal
- dielectric layer
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 41
- 238000004519 manufacturing process Methods 0.000 title description 8
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 claims abstract description 61
- 229910001092 metal group alloy Inorganic materials 0.000 claims abstract description 24
- 229910052751 metal Inorganic materials 0.000 claims description 49
- 239000002184 metal Substances 0.000 claims description 37
- 238000000034 method Methods 0.000 claims description 32
- 239000000758 substrate Substances 0.000 claims description 32
- 238000005516 engineering process Methods 0.000 claims description 18
- 238000000231 atomic layer deposition Methods 0.000 claims description 17
- 239000003990 capacitor Substances 0.000 claims description 15
- 229910044991 metal oxide Inorganic materials 0.000 claims description 15
- 150000004706 metal oxides Chemical class 0.000 claims description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 229910052735 hafnium Inorganic materials 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 11
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 11
- MUBZPKHOEPUJKR-UHFFFAOYSA-N Oxalic acid Chemical compound OC(=O)C(O)=O MUBZPKHOEPUJKR-UHFFFAOYSA-N 0.000 claims description 10
- QVQLCTNNEUAWMS-UHFFFAOYSA-N barium oxide Chemical compound [Ba]=O QVQLCTNNEUAWMS-UHFFFAOYSA-N 0.000 claims description 10
- 238000000137 annealing Methods 0.000 claims description 9
- -1 oxide button Chemical compound 0.000 claims description 9
- 150000003839 salts Chemical class 0.000 claims description 9
- 229910052782 aluminium Inorganic materials 0.000 claims description 8
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 claims description 8
- 229910052914 metal silicate Inorganic materials 0.000 claims description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 7
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 7
- 238000005229 chemical vapour deposition Methods 0.000 claims description 7
- 229910002064 alloy oxide Inorganic materials 0.000 claims description 5
- 230000007423 decrease Effects 0.000 claims description 5
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 5
- 238000005546 reactive sputtering Methods 0.000 claims description 5
- 239000004575 stone Substances 0.000 claims description 5
- 229910052726 zirconium Inorganic materials 0.000 claims description 5
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 239000000203 mixture Substances 0.000 claims description 4
- 229910052702 rhenium Inorganic materials 0.000 claims description 4
- WUAPFZMCVAUBPE-UHFFFAOYSA-N rhenium atom Chemical compound [Re] WUAPFZMCVAUBPE-UHFFFAOYSA-N 0.000 claims description 4
- 239000010936 titanium Substances 0.000 claims description 4
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 239000002253 acid Substances 0.000 claims description 3
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- AZDRQVAHHNSJOQ-UHFFFAOYSA-N alumane Chemical group [AlH3] AZDRQVAHHNSJOQ-UHFFFAOYSA-N 0.000 claims description 2
- JNDMLEXHDPKVFC-UHFFFAOYSA-N aluminum;oxygen(2-);yttrium(3+) Chemical compound [O-2].[O-2].[O-2].[Al+3].[Y+3] JNDMLEXHDPKVFC-UHFFFAOYSA-N 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims 2
- 229910052746 lanthanum Inorganic materials 0.000 claims 2
- 235000014676 Phragmites communis Nutrition 0.000 claims 1
- WIACXAXNTAJXSG-UHFFFAOYSA-N [Re+4].[O-2].[Al+3] Chemical compound [Re+4].[O-2].[Al+3] WIACXAXNTAJXSG-UHFFFAOYSA-N 0.000 claims 1
- 150000001875 compounds Chemical class 0.000 claims 1
- FZLIPJUXYLNCLC-UHFFFAOYSA-N lanthanum atom Chemical compound [La] FZLIPJUXYLNCLC-UHFFFAOYSA-N 0.000 claims 1
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 claims 1
- 230000000737 periodic effect Effects 0.000 claims 1
- 238000007747 plating Methods 0.000 claims 1
- KKCBUQHMOMHUOY-UHFFFAOYSA-N sodium oxide Chemical compound [O-2].[Na+].[Na+] KKCBUQHMOMHUOY-UHFFFAOYSA-N 0.000 claims 1
- 229910001948 sodium oxide Inorganic materials 0.000 claims 1
- ZCUFMDLYAMJYST-UHFFFAOYSA-N thorium dioxide Chemical compound O=[Th]=O ZCUFMDLYAMJYST-UHFFFAOYSA-N 0.000 claims 1
- 229910003452 thorium oxide Inorganic materials 0.000 claims 1
- 229910052727 yttrium Inorganic materials 0.000 claims 1
- 229910001928 zirconium oxide Inorganic materials 0.000 claims 1
- 239000010410 layer Substances 0.000 description 204
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 12
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 8
- 239000003989 dielectric material Substances 0.000 description 7
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 6
- 235000012239 silicon dioxide Nutrition 0.000 description 6
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- 229910021332 silicide Inorganic materials 0.000 description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 4
- 125000006850 spacer group Chemical group 0.000 description 4
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- 229910000838 Al alloy Inorganic materials 0.000 description 2
- ROSDSFDQCJNGOL-UHFFFAOYSA-N Dimethylamine Chemical compound CNC ROSDSFDQCJNGOL-UHFFFAOYSA-N 0.000 description 2
- 229910003865 HfCl4 Inorganic materials 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 229910052769 Ytterbium Inorganic materials 0.000 description 2
- 229910007932 ZrCl4 Inorganic materials 0.000 description 2
- 238000002425 crystallisation Methods 0.000 description 2
- 230000008025 crystallization Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000002243 precursor Substances 0.000 description 2
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 2
- 238000012916 structural analysis Methods 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- NAWDYIZEMPQZHO-UHFFFAOYSA-N ytterbium Chemical compound [Yb] NAWDYIZEMPQZHO-UHFFFAOYSA-N 0.000 description 2
- SDTMFDGELKWGFT-UHFFFAOYSA-N 2-methylpropan-2-olate Chemical compound CC(C)(C)[O-] SDTMFDGELKWGFT-UHFFFAOYSA-N 0.000 description 1
- QGZKDVFQNNGYKY-UHFFFAOYSA-O Ammonium Chemical compound [NH4+] QGZKDVFQNNGYKY-UHFFFAOYSA-O 0.000 description 1
- 229910001029 Hf alloy Inorganic materials 0.000 description 1
- 229910003855 HfAlO Inorganic materials 0.000 description 1
- 229910000914 Mn alloy Inorganic materials 0.000 description 1
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 1
- 241001674048 Phthiraptera Species 0.000 description 1
- 229910007245 Si2Cl6 Inorganic materials 0.000 description 1
- 229910003910 SiCl4 Inorganic materials 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- 150000001298 alcohols Chemical class 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- VYBYZVVRYQDCGQ-UHFFFAOYSA-N alumane;hafnium Chemical compound [AlH3].[Hf] VYBYZVVRYQDCGQ-UHFFFAOYSA-N 0.000 description 1
- 150000004645 aluminates Chemical class 0.000 description 1
- MIQVEZFSDIJTMW-UHFFFAOYSA-N aluminum hafnium(4+) oxygen(2-) Chemical compound [O-2].[Al+3].[Hf+4] MIQVEZFSDIJTMW-UHFFFAOYSA-N 0.000 description 1
- VQYHBXLHGKQYOY-UHFFFAOYSA-N aluminum oxygen(2-) titanium(4+) Chemical compound [O-2].[Al+3].[Ti+4] VQYHBXLHGKQYOY-UHFFFAOYSA-N 0.000 description 1
- DDUQUDHFIZQTCS-UHFFFAOYSA-N aluminum;oxygen(2-);samarium(3+) Chemical compound [O-2].[O-2].[O-2].[Al+3].[Sm+3] DDUQUDHFIZQTCS-UHFFFAOYSA-N 0.000 description 1
- 230000009172 bursting Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000000839 emulsion Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 150000002362 hafnium Chemical class 0.000 description 1
- PDPJQWYGJJBYLF-UHFFFAOYSA-J hafnium tetrachloride Chemical compound Cl[Hf](Cl)(Cl)Cl PDPJQWYGJJBYLF-UHFFFAOYSA-J 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000005527 interface trap Effects 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 125000000956 methoxy group Chemical group [H]C([H])([H])O* 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000010349 pulsation Effects 0.000 description 1
- 238000000746 purification Methods 0.000 description 1
- 229910052704 radon Inorganic materials 0.000 description 1
- SYUHGPGVQRZVTB-UHFFFAOYSA-N radon atom Chemical compound [Rn] SYUHGPGVQRZVTB-UHFFFAOYSA-N 0.000 description 1
- RMAQACBXLXPBSY-UHFFFAOYSA-N silicic acid Chemical compound O[Si](O)(O)O RMAQACBXLXPBSY-UHFFFAOYSA-N 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 235000015096 spirit Nutrition 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- 238000003949 trap density measurement Methods 0.000 description 1
- LXEXBJXDGVGRAR-UHFFFAOYSA-N trichloro(trichlorosilyl)silane Chemical compound Cl[Si](Cl)(Cl)[Si](Cl)(Cl)Cl LXEXBJXDGVGRAR-UHFFFAOYSA-N 0.000 description 1
- DUNKXUFBGCUVQW-UHFFFAOYSA-J zirconium tetrachloride Chemical compound Cl[Zr](Cl)(Cl)Cl DUNKXUFBGCUVQW-UHFFFAOYSA-J 0.000 description 1
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
- Non-Volatile Memory (AREA)
- Thin Film Transistor (AREA)
- Chemical Vapour Deposition (AREA)
- Semiconductor Integrated Circuits (AREA)
- Formation Of Insulating Films (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
200537621 九、發明說明： 【發明所屬之技術領域】 本發明大體而言係關於半導體裝置領域，且更特定言 之’本發明係關於一種多層介電結構及利用該多層介電結 構及其製造方法之半導體裝置。 【先前技術】 隨著每一代金屬氧化物半導體（M〇s)積體電路（1C)，裝置 尺寸已持續縮小以提供高密度與高效能之裝置。特定言 > 之’使閘極介電質之厚度盡可能小，因為M〇s(金屬氧化物 半導體）場效電晶體（FET)中之驅動電流隨閘極介電質厚度 減小而增加。因此，為改良裝置效能而提供極薄、可靠且 低缺陷之閘極介電質變得愈來愈重要。 數十年來，例如二氧化矽（Si〇2)之熱氧化物層已用作閘極 μ電質，因為二氧化矽熱氧化物層與下層矽基板穩定，且 製造製程相對簡單。 一氧化矽具有低介電常數（k)(例如3.9)，進一200537621 IX. Description of the invention: [Technical field to which the invention belongs] The present invention generally relates to the field of semiconductor devices, and more specifically, the present invention relates to a multilayer dielectric structure and the use of the multilayer dielectric structure and a manufacturing method thereof Semiconductor device. [Previous Technology] With each generation of metal oxide semiconductor (MOS) integrated circuit (1C), the device size has been continuously reduced to provide high-density and high-performance devices. In particular, the 'make the gate dielectric thickness as small as possible, because the driving current in the Mos (metal oxide semiconductor) field effect transistor (FET) increases as the gate dielectric thickness decreases. . Therefore, it is becoming increasingly important to provide extremely thin, reliable, and low defect gate dielectrics to improve device performance. For decades, a thermal oxide layer such as silicon dioxide (SiO2) has been used as the gate μ-electrode because the silicon dioxide thermal oxide layer is stable to the underlying silicon substrate and the manufacturing process is relatively simple. Silicon monoxide has a low dielectric constant (k) (for example, 3.9).
然而，因為二 步縮小二氧化石$ /序的層中，但仍產生相同或更好 達為“等效氧化物厚度（E〇T)，，。 料之裝置特性。舉例而 已做過各種¥試來改良介電材料二 98898.doc 200537621However, because of the two-step reduction of the dioxide / order layer, it still yields the same or better up to the "equivalent oxide thickness (EO)". The device characteristics of the material. Examples have been made various Try to improve the dielectric material 98898.doc 200537621
人。、、國專⑺第6，G2G，G24號揭示了-種插人♦基板與高k 電層之間的氮氧化物層。美國專利第6，㈣，…號揭示了 -種作為閘極介電質之氮氧化鍅層或氮氧化铪層。此外， 國際專利中晴公開案第WQ。0/010()8號揭示了 Si02、氮 夕及氮氧化物介面層。美國專利第6,〇2〇,243號亦揭示了 一種高介電常數锆（或铪）氮氧化矽閘極介電質。 s j而此等嘗試並未成功解決與習知介電材料相關之問 ^牛例而σ，同k介電層與矽基板或多晶矽閘電極之間的 虱化矽層或氮氧化物層導致具有高介面狀態密度的電荷陷 阱，進而減低通道遷移率且亦降低裝置效能。此外，氮氧 化石夕層或氮氧化物層之形成需要相對大的熱預算。 相應地，仍需要改良的介電層結構及製造方法來藉由（例 如）減少介電層之等效氧化物厚度及改良介面特性而改良 裝置效能。 【發明内容】 在一實施例中，半導體裝置包括一矽酸鹽介面層及一覆 亥矽駄鹽介面層上的高k介電層。該高k介電層包括金屬 合金氧化物。 【實施方式】 本發明提供_種卓越的介電層結構及其製造方法。在以 述中闌述諸多具體細節來提供對本發明之徹底瞭 =然而，普通熟習此項技術者應瞭解，無需此等具體細 即便可實施本發明。在—些情況下，未詳細展示熟知的處 v驟、裝置結構及技術以避免混淆本發明。 98898.doc 200537621 參看圖卜根據本發明之—實施例，—由㈣鹽材料形成 之石夕酸鹽介面層12可安置於一導電層或諸如石夕基板之半導 體基板10上。石夕酸鹽介面層12之介電常數較佳大於二氧化 石夕、氮化石夕或氮氧化石夕中任一者之介電常數。較佳地，石夕 ‘酸鹽介面層具有約為5埃至50埃之厚度。更佳地，石夕酸鹽 ^面層12具有約為5埃至卿之厚度（2埃至4埃的E叫等效 氧化物厚度））。矽酸鹽介面層12較佳係由式所表 示之金屬矽酸鹽材料形成。此處，金屬“M”可為銓（Hf)、鍅 (Zr)、组（Ta)、鈦（Ti)、航（Sc)、紀⑺、鋼（La)及銘⑽。然 而，並不希望此清單無遺漏或限制本發明。可在本發明的 精神及範轉内使用任何適於本發明之其它金屬。 根據本發明之一態樣，金屬矽酸鹽材料（Mi xSix〇2)展示 了當值”l-x”大於或等於約〇」時介電常數之最佳值。較佳 地，值”l-x”不大於約〇·5。更佳地，值” i_x”為約〇·2至約〇·4。 此外，一高k介電層14安置於矽酸鹽介面層12上，以形成 φ 一多層介電結構15。高k介電層Η之介電常數高於si〇2之介 電常數。高k介電層14之介電常數宜高於矽酸鹽介面層12之 介電常數。高k介電層也宜具有與下層矽酸鹽介面層12之極 好的連貫性（coherency)，且不與諸如閘電極或控制閘極之 上層結構反應。 在本發明中，矽酸鹽介面層12大體上改良了介面特性。 此係因為矽酸鹽介面層12大體上防止了（例如）高k介電層14 與下層半導體基板10之間或高k介電層與用於形成電容器 之下部電極之間的反應。此外，因為該石夕酸鹽介面層12之 98898.doc 200537621 形成能置比二氧务访々jjy > U…I化石夕之形纟能量更為負，I在石夕基板上係 匕^上穩疋的’因此有助於形成可靠之半導體裝置。因此， 咸^本發明與先前技術方法相比減低了介面陷牌密度，且 大體上改良了介面特性。 j外肖此等先前技術方法相比，可保持或減低而（等 效乳化物厚度)’因為金屬矽酸鹽介面層12具有約為】〇至匕 之相對高的介電常數。 此外，咸信金屬料鹽介面層12在隨後之熱處理期間， 即使在9啊高溫下也可保持大體上非晶形之狀態。因此， 在金屬矽酸鹽介面層12中產生更少的晶粒邊界，進而減少 洩漏電流。 現回頭看高k介電層14，其包括金屬合金氧化物。高乂介 曰之孟屬合金氧化物以包含至少兩互相擴散之金屬元 素較佳、。高k介電層14之金屬合金氧化物可為至少兩金屬氧 物之此&物。該等至少兩金屬元素經均勻混合更佳，其 ^並：< 在原子級上均句混合最佳。’然巾，視應用而定，該 等至少兩金屬元素可未經均勻混合，但經充分混合以充當 在本發明之精神及範疇内的介電材料。 根據本發明之一態樣，形成高k介電層14之至少兩金屬氧 化物可經選擇成在高k介電層Η中具有最小淨固《電荷，例 :接近零。就此而論，金屬氧化物可包含但不限於氧化銓、 氧化锆、氧化鈕、氧化鋁、氧化鈦、氧化釔、氧化鳃、氧 化銳、氧化鑭或氧化鋇。 在另一態樣中，金屬氧化物可描述為铪鋁合金氧化物、 98898.doc 200537621 錯铭合金氧化物、鈕鋁合金氧化物、鈦鋁合金氧化物、釔 铭合金氧化物或铪鍅鋁氧化物。然而，並不希望此清單無 遺漏或限制本發明。可在本發明的精神及範疇内使用任何 適於本發明之其它金屬。熟習此項技術者將瞭解，金屬鋁 合金氧化物可表示為金屬鋁酸鹽，例如鋁酸铪（HfAlO)。 包含金屬合金氧化物之高k介電層14之介電常數可大於 石夕酸鹽介面層12之介電常數。 • 此外，金屬合金氧化物可由式AyBi y〇z，（〇<y<1)來表示。 杈佳地’ A與上述Μ相同或來自與μ相同之週期族。換言 之，矽酸鹽介面層12之金屬較佳與金屬合金氧化物之金屬 (高k介電層14)相同。舉例而言，若多層介電結構15包括矽 酸铪介面層丨2，則高k介電層14可包括一铪鋁合金氧化物 層，例如氧化铪與氧化鋁之混合物。同樣，若矽酸鹽介面 層12包括一矽酸錯介面層12，則高k介電層14包括一鍅鋁合 金氧化物層，例如氧化锆與氧化鋁之混合物。結果，裝置 鲁特性可得以改良。舉例而言，介面特性可由於石夕酸鹽介面 層12與上層高k介電層14之間的電連貫性而得以改良。 更佳地，A與乂為…族金屬，且B為χIII族金屬。舉例而 言，A為锆或铪，且B為鋁。 根據-態樣，V可為約0.5至約0.9,以具有高介電常數 及南結晶溫度。 根據另一態樣，A與B之組合比在約！：丨與約5 :丨之間。 此係因為A之含量愈高’介電常數愈高，但結晶溫度愈低， 其導致洩漏電流增加。理想地，高k介電層14具有大體上非 98898.doc •10- 200537621 晶形結晶結構’以減少流經其的茂漏電流。更佳地， 之組合比為約2 :卜因為所得的高k介電層14之淨固定電荷 «接k零纟此狀況下，八較佳為铪或鍅；且B較佳為鋁。 高k介電層14可具有約2埃至6〇埃之厚度。此處，2埃為一原 子層之基本厚度’且60埃表示在隨後之退火製程期間防止 爆裂現象之厚度上限。如此項技術中已知，在形成期間陷 牌於介電層中的經基基團可在隨後退火時自介電層爆裂， 從而毁壞介電層，例如在介電層中留下洞。若發生此種爆 裂現象’隨後的處理步驟（諸如閘極多沉積）可受到顯著抑 制。 圖2說明一種製造用於半導體裝置中的上述多層介電結 構15之方法。為清楚與簡明起見，若製造步驟係為習知或 熟知，則省略其細節。 如上所述，矽酸鹽介面層12可形成於導電層或半導體基 板10上。金屬矽酸鹽介面層12較佳係由參看圖i所述之材料 形成。更佳地，金屬矽酸鹽介面層12可使用ALD(原子層沉 積）技術形成。因此，與需要高熱預算之先前技術方法對 比，低熱預算製程在本發明之情況下係為可能。此外，夢 由使用ALD(原子層沉積）技術，可使用更廣範圍之前軀物， 且可形成一具有受到緊密控制的厚度之膜，傳統化學氣相 沉積（CVD)將不可能形成該膜。 詳言之，如此項技術中已知，可藉由交替且反覆地對金 屬來源、石夕來源及氧來源執行脈動及淨化步驟來執行用於 形成金屬矽酸鹽介面層12之ALD(原子層沉積）技術。在秒酸 98898.doc • 11 - 200537621 鍅介面層12狀況下，ZrCl4可用作金屬來源。類似地，在矽 酸铪介面層之狀況下，HfCl4可用作金屬來源。同樣，矽來 源可包括SiH4或SiCl4H2。氧來源可包括H20、臭氧、氧基、 醇類，諸如IPA、D20或H2〇2。同樣，可在本發明的精神及 範疇内使用其它適用於本發明之前軀物。在表1中說明了此 等例示性前軀物。 表1 給來源 锆來源 矽來源 鹵化物 HfCl4 ZrCl4 SiCl4 烷氧化物 Hf(OtC4H9)4Hf(OC2H5)4 &(OtC4H9)4 Si(OC4H9)4Si- (OCH3)4Si(OC2H5)4 醯胺 Hf(N(C2H5)2)4H- f(N(CH3)2)4， Hf(N(CH3C2H5))4 Zr(N(C2H5)2)4- Zr(N9CH3)2)4? Zr(N(CH3C2H5))4 Si(N(C2H5)2)4_ Si(N(CH3)2)4， Si(N(CH3)2)3H， HfCl2(hmds)2 烷氧胺 (alkoxylamine) Hf(dmae)4 Zr(dmae)4 Si(dmae)4 ETC SiH4, SiCl4H2, Si2Cl6 *dmae(二甲胺)people. No. 6, G2G, and G24 of the National Academy of Sciences revealed a kind of nitrogen oxide layer interposed between the substrate and the high-k electrical layer. U.S. Patent No. 6, ㈣, ... discloses a hafnium oxynitride layer or a hafnium oxynitride layer as a gate dielectric. In addition, the International Patent Zhongqing Publication No. WQ. 0/010 () 8 reveals the interface layer of SiO2, nitrogen oxide and nitrogen oxide. U.S. Patent No. 6,002,243 also discloses a high dielectric constant zirconium (or hafnium) oxynitride silicon gate dielectric. These attempts have not succeeded in solving the problems related to the conventional dielectric materials. However, σ, the lice silicon layer or the nitrogen oxide layer between the k dielectric layer and the silicon substrate or polysilicon gate electrode leads to High interface state density of charge traps reduces channel mobility and also reduces device performance. In addition, the formation of oxynitride layers or oxynitride layers requires a relatively large thermal budget. Accordingly, there is still a need for improved dielectric layer structures and manufacturing methods to improve device performance by, for example, reducing the equivalent oxide thickness of the dielectric layer and improving interface characteristics. SUMMARY OF THE INVENTION In one embodiment, a semiconductor device includes a silicate interface layer and a high-k dielectric layer overlying the silicate interface layer. The high-k dielectric layer includes a metal alloy oxide. [Embodiment] The present invention provides an excellent dielectric layer structure and a manufacturing method thereof. In the description, many specific details are provided to provide a thorough understanding of the present invention. However, those skilled in the art should understand that such specific details are not required even if the present invention can be implemented. In some cases, well-known processes, device structures, and techniques have not been shown in detail to avoid obscuring the invention. 98898.doc 200537621 Referring to FIG. According to an embodiment of the present invention, a oxalate interface layer 12 formed of a hafnium salt material may be disposed on a conductive layer or a semiconductor substrate 10 such as a shixi substrate. The dielectric constant of the oxalate interface layer 12 is preferably larger than the dielectric constant of any one of a dioxide, a nitride, or a oxynitride. Preferably, the Shi Xi'acid interface layer has a thickness of about 5 to 50 angstroms. More preferably, the oxalate surface layer 12 has a thickness of about 5 angstroms to 100 angstroms (E of 2 angstroms to 4 angstroms is called the equivalent oxide thickness). The silicate interface layer 12 is preferably formed of a metal silicate material represented by the formula. Here, the metal “M” may be Hf, Hf, Zr, Ta, Ti, Sc, Ji, La, and Ming. However, this list is not intended to be exhaustive or to limit the invention. Any other metal suitable for the present invention can be used within the spirit and scope of the present invention. According to one aspect of the present invention, the metal silicate material (Mi x Six 〇2) shows an optimal value of the dielectric constant when the value "l-x" is greater than or equal to about 0 ". Preferably, the value "l-x" is not greater than about 0.5. More preferably, the value "i_x" is about 0.2 to about 0.4. In addition, a high-k dielectric layer 14 is disposed on the silicate interface layer 12 to form a multi-layered dielectric structure 15. The high-k dielectric layer 介 has a dielectric constant higher than that of SiO2. The dielectric constant of the high-k dielectric layer 14 is preferably higher than the dielectric constant of the silicate interface layer 12. The high-k dielectric layer also preferably has excellent coherency with the lower silicate interface layer 12 and does not react with the upper structure such as a gate electrode or a control gate. In the present invention, the silicate interface layer 12 substantially improves the interface characteristics. This is because the silicate interface layer 12 substantially prevents, for example, the reaction between the high-k dielectric layer 14 and the lower semiconductor substrate 10 or between the high-k dielectric layer and the lower electrode used to form the capacitor. In addition, because the formation rate of the osparate interface layer 12 of 98898.doc 200537621 is more negative than that of the dioxygenation jjy > U ... I, the shape of the fossil eve is more negative, and I is attached to the shixi substrate. The stable 'thus helps to form a reliable semiconductor device. Therefore, compared with the prior art method, the present invention reduces the interface trap density and substantially improves the interface characteristics. In comparison with these prior art methods, these can be maintained or reduced (equivalent emulsion thickness) 'because the metal silicate interface layer 12 has a relatively high dielectric constant of about 0 to about 3,000 Å. In addition, the salt metal salt interface layer 12 can maintain a substantially amorphous state even at a high temperature of 9 ° C during the subsequent heat treatment. Therefore, fewer grain boundaries are generated in the metal silicate interface layer 12, thereby reducing leakage current. Looking back now, the high-k dielectric layer 14 includes a metal alloy oxide. Gao Xunjie said that the alloy of manganese alloys preferably contains at least two interdiffusion metal elements. The metal alloy oxide of the high-k dielectric layer 14 may be the & material of at least two metal oxides. It is better that the at least two metal elements are uniformly mixed, and its union: < the best homogeneous mixing at the atomic level. However, depending on the application, these at least two metal elements may not be uniformly mixed, but sufficiently mixed to serve as a dielectric material within the spirit and scope of the present invention. According to one aspect of the present invention, at least two metal oxides forming the high-k dielectric layer 14 may be selected to have a minimum net solid charge in the high-k dielectric layer Η, eg, close to zero. In this connection, the metal oxide may include, but is not limited to, hafnium oxide, zirconia, oxide button, aluminum oxide, titanium oxide, yttrium oxide, gill oxide, sharp oxide, lanthanum oxide, or barium oxide. In another aspect, the metal oxide can be described as samarium aluminum oxide, 98898.doc 200537621 misaligned alloy oxide, button aluminum oxide, titanium aluminum oxide, yttrium aluminum oxide, or hafnium aluminum Oxide. However, this list is not intended to be exhaustive or to limit the invention. Any other metal suitable for the present invention can be used within the spirit and scope of the present invention. Those skilled in the art will understand that metal aluminum alloy oxides can be expressed as metal aluminates, such as hafnium aluminate (HfAlO). The dielectric constant of the high-k dielectric layer 14 including the metal alloy oxide may be greater than the dielectric constant of the oxalate interface layer 12. • In addition, the metal alloy oxide can be represented by the formula AyBi y〇z, (〇 < y < 1).佳佳 地 'A is the same as M above or from the same cycle family as μ. In other words, the metal of the silicate interface layer 12 is preferably the same as the metal of the metal alloy oxide (high-k dielectric layer 14). For example, if the multilayer dielectric structure 15 includes a hafnium silicate interface layer 2, the high-k dielectric layer 14 may include a hafnium alloy oxide layer, such as a mixture of hafnium oxide and alumina. Similarly, if the silicate interface layer 12 includes a silicic acid interfacial layer 12, the high-k dielectric layer 14 includes a hafnium aluminum alloy oxide layer, such as a mixture of zirconia and alumina. As a result, the device characteristics can be improved. For example, the interface characteristics can be improved due to the electrical continuity between the oxalate interface layer 12 and the upper high-k dielectric layer 14. More preferably, A and 乂 are a group of metals and B is a group of χIII metals. By way of example, A is zirconium or hafnium and B is aluminum. According to the aspect, V may be about 0.5 to about 0.9 to have a high dielectric constant and a south crystallization temperature. According to another aspect, the combination ratio of A and B is about! : Between 丨 and about 5: 丨. This is because the higher the A content, the higher the dielectric constant, but the lower the crystallization temperature, which leads to an increase in leakage current. Ideally, the high-k dielectric layer 14 has a substantially non-crystalline crystal structure ' More preferably, the combination ratio is about 2: because the net fixed charge of the obtained high-k dielectric layer 14 is smaller than k. In this case, eight is preferably 铪 or 鍅; and B is preferably aluminum. The high-k dielectric layer 14 may have a thickness of about 2 to 60 angstroms. Here, 2 Angstroms is the basic thickness of an atomic layer 'and 60 Angstroms represents the upper limit of the thickness to prevent the bursting phenomenon during the subsequent annealing process. As is known in the art, radicals trapped in the dielectric layer during formation can burst from the dielectric layer during subsequent annealing, thereby destroying the dielectric layer, such as leaving holes in the dielectric layer. If such a burst occurs, subsequent processing steps, such as multiple gate deposition, can be significantly suppressed. Fig. 2 illustrates a method of manufacturing the above-mentioned multilayer dielectric structure 15 for use in a semiconductor device. For clarity and conciseness, if the manufacturing steps are known or well known, the details are omitted. As described above, the silicate interface layer 12 may be formed on the conductive layer or the semiconductor substrate 10. The metal silicate interface layer 12 is preferably formed of a material as described with reference to FIG. More preferably, the metal silicate interface layer 12 can be formed using ALD (atomic layer deposition) technology. Therefore, in contrast to prior art methods that require a high thermal budget, a low thermal budget process is possible in the context of the present invention. In addition, Dream uses ALD (Atomic Layer Deposition) technology, which can use a wider range of previous bodies, and can form a film with a tightly controlled thickness that would not be possible with conventional chemical vapor deposition (CVD). In detail, it is known in this technology that the ALD (atomic layer) for forming the metal silicate interface layer 12 can be performed by alternately and repeatedly performing pulsation and purification steps on the metal source, the stone source, and the oxygen source. Deposition) technology. Under the condition of 98898.doc • 11-200537621 鍅 interface layer 12, ZrCl4 can be used as a metal source. Similarly, in the case of a hafnium silicate interface layer, HfCl4 can be used as a metal source. Similarly, the silicon source can include SiH4 or SiCl4H2. The oxygen source may include H20, ozone, oxygen, alcohols, such as IPA, D20, or H202. In the same way, other spirits applicable to the present invention can be used within the spirit and scope of the present invention. Table 1 illustrates these exemplary precursors. Table 1 Source Zirconium Source Silicon Source Halide HfCl4 ZrCl4 SiCl4 Alkoxide Hf (OtC4H9) 4Hf (OC2H5) 4 & (OtC4H9) 4 Si (OC4H9) 4Si- (OCH3) 4Si (OC2H5) 4 Ammonium Hf (N (C2H5) 2) 4H- f (N (CH3) 2) 4, Hf (N (CH3C2H5)) 4 Zr (N (C2H5) 2) 4- Zr (N9CH3) 2) 4? Zr (N (CH3C2H5)) 4 Si (N (C2H5) 2) 4_ Si (N (CH3) 2) 4, Si (N (CH3) 2) 3H, HfCl2 (hmds) 2 Alkoxylamine Hf (dmae) 4 Zr (dmae) 4 Si (dmae) 4 ETC SiH4, SiCl4H2, Si2Cl6 * dmae (dimethylamine)
或者，若金屬有機化學氣相沉積（MOCVD)技術或反應性 濺鍍技術在厚度或組合物方面提供與ALD(原子層沉積）技 術類似之控制水平，則可使用MOCVD(金屬有機化學氣相 沉積）技術或反應性濺鍍技術來形成矽酸鹽介面層12。可使 用諸如 Hf(〇-Si-R3)4 或 Zr(0-Si-R3)4,（R=C2H5)之前軀物來執 行MOCVD(金屬有機彳匕學氣相沉積）技術。同樣，可使用諸 如第三丁氧化銓之铪來源、諸如第三丁氧化锆之鍅來源， 及諸如四乙氧基原石夕烧（tetraethoxyorthosilane)或原石夕酸四 乙酯（TEOS)之矽來源。 98898.doc -12- 200537621 一接者，如上文參看圖】所述，形成包括金屬合金氧化物之 高k介電層14 ,以覆於矽酸鹽介面層12上。 更β羊細地，根據一態樣，為形成高k介電層Μ，藉由 ALD(原子層沉積)技術形成一具有—第一金屬元素之 層18。然後’亦藉由ALD(原子層沉積)技術形成一覆於該第 一層18上、具有-第二金屬元素之第二層20。第一及第二Alternatively, if metal organic chemical vapor deposition (MOCVD) technology or reactive sputtering technology provides a level of control similar in thickness or composition to ALD (atomic layer deposition) technology, then MOCVD (metal organic chemical vapor deposition) can be used ) Technology or reactive sputtering technology to form the silicate interface layer 12. MOCVD (Metal-Organic Vapor Deposition) technology can be performed using precursors such as Hf (〇-Si-R3) 4 or Zr (0-Si-R3) 4, (R = C2H5). Similarly, sources of rhenium such as terbium tert-butoxide, rhenium sources such as tertiary butoxide, and silicon sources such as tetraethoxyorthosilane or tetraethyl ortho-ethyl ester (TEOS) can be used. 98898.doc -12- 200537621 One by one, as described above with reference to the drawings, a high-k dielectric layer 14 including a metal alloy oxide is formed to cover the silicate interface layer 12. More specifically, according to one aspect, in order to form a high-k dielectric layer M, a layer 18 having a first metal element is formed by an ALD (atomic layer deposition) technique. Then, a second layer 20 with a second metal element is formed on the first layer 18 by ALD (atomic layer deposition) technology. First and second
金屬元素可為一可形成諸如氧化銓、氧化鍅、氧化鈕、ZThe metal element may be one that can form, for example, hafnium oxide, hafnium oxide, oxide button, Z
銘氧化欽、氧化紀、氧化錄、氧化航、氧化鋼或氧化 鋇之氧化物的金屬。 一另方面，右矽酸鹽介面層12係由矽酸鍅形成，則上層 咼k介電層14宜藉由交替地堆疊Zr〇2層與A〗"3層，加上以 下將進-步描述之隨後熱處理來形成。在此狀況下，因為 石夕酸鹽介面層12之金屬與金屬合金氧化物層（高k介電層14) 中所含的金屬之-相同’介面特性可由於料鹽介面層Η 與上層高k介電層14之間的電連貫性而得以改良（如上所 =)。類似地，若矽酸鹽介面層12係由矽酸姶形成，則高k 介電層14宜藉由交替地堆疊Hf〇2層與Μ"3層，及以下將進 一步描述之隨後熱處理來形成。 々以第一層18具有一第一預定電荷，且第二層20具有一與 第一層1 8之預定電荷相反的第二預定電荷更佳。其中，並 以第一預定電荷為正固定電荷，且第二預定電荷為負固定 電荷最佳。按此思路，第一層i 8可由氧化铪、氧化錘、氧 化I '氧化鋁、氧化鈦、氧化釔、氧化鳃、氧化銃、氧化 鑭或氧化鋇形成，且第二層2〇可由氧化鋁形成。 98898.doc -13 - 200537621 一因此，根據本發明之一態樣，使高k介電層"之淨固定電 何最小化係為可能。就此而冑，在先前技術中，固定電荷 存在-問題，其導致會減低通道遷移率之庫侖散射。然而， 在本發明之-態樣中，先前技術之固定電荷問題可藉由以 諸如上述氧化給或氧化錯之材料形成之第_層18中之正固 定電荷，補償由諸如氧化銘之材料形叙第二層2〇中之負 固定電荷來克服，尤其是當金屬氧化物係在原子級上均句 混合或在隨後的製造製程期間互相擴散時。 第二層20之厚度可約為第一層18之厚度的一半。若第一 層18係由諸如氧化铪或氧化鍅之材料形成，且第二層係 由氧化鋁形成，則尤其如此，因為咸信氧化鋁中之固定電 荷量大約比氧化铪或氧化錯之固定電荷量多兩倍。舉例而 言，第一層18可形成大約1〇埃之厚度，且第二層2〇可形成 大約5埃之厚度。 根據本發明之一實施例，所得之結構隨後受到退火或熱 處理’以形成圖1所示之多層介電結構15。舉例而言，退火 溫度可大於約900°C，以使圖2所示之第一層18與第二層2〇 結合或混合而形成包含至少兩互相擴散之金屬元素之高k 介電層14。較佳地，退火溫度約為95(rc。更佳地，退火溫 度足夠高，以使至少兩金屬元素在原子級上在高k介電層14 中均勻混合而形成一金屬合金氧化物層。 參看圖3 ’根據另一態樣’在為進行熱處理或退火以形成 圖1所示之多層介電結構15之前，在所得結構上形成一或多 個額外的第一及第二層18、20。另一導電層24可形成於高k 98898.doc -14- 200537621 介電層14上以形成各種半導體裝置。同樣，在退火之前， 最上層22可包括氧化鋁以改良高k介電層“與導電層以之 間的介面特性。 在另一態樣中，高k介電層14可由m〇CVD(金屬有機化學 • 氣相沉積）技術來形成。較佳地，同時供應兩金屬元素之來 源以形成包括金屬合金氧化物之高k介電層14。或者，金屬 合金氧化物層可使用反應性濺鍍技術來形成。反應性濺鍍 技術係藉由在金屬沉積期間注入氧氣至處理腔室中來執 響行。 以上描述的本發明可用於形成如下所述之M〇s(金屬氧 化物半導體）電晶體。同樣，本發明亦可應用於半導體裝置 之任何介電質’諸如非揮發性記憶體之閘極間介電層或儲 存電容器之介電層，其全部在本發明精神及範疇内。 詳言之，參看圖4，一MOS(金屬氧化物半導體）電晶體41 包括一半導體基板1〇〇、一形成於基板1〇〇上之矽酸鹽介面 _ 層120a，及一形成於矽酸鹽介面層120a之上用以形成閘極 介電層120之高k介電層120b。矽酸鹽介面層120a及高k介電 層120b均係由關於圖1所述之介電材料形成。此外，MOS(金 屬氧化物半導體）電晶體41可進一步包含一閘電極130，該 閘電極包括（例如）一多晶矽層130a、一矽化物層130b及一形 成於鄰接閘電極130處的源極/汲極區域。閘電極130可由金 屬形成。視需要，可沿著閘電極130之相對側形成一隔片 150，以完成具有一通道區域107之半導體裝置41。 參看圖5，根據另一實施例，一非揮發性記憶體裝置5 1 98898.doc 200537621 包括一半導體基板200、一具有一覆於基板200上之閘極絕 緣層209之浮動閘極210、一形成於浮動閘極210之上的矽酸 鹽介面層220a，及一形成於矽酸鹽介面層220a之上用以形 成閘極間介電層220的高k介電層220b。矽酸鹽介面層220a 及高k介電層220b均由關於圖1所述之介電材料形成。同 樣，一控制閘極230覆於閘極間介電層220上。如此項技術 中已知，控制閘極23 0可包括一多晶矽層230a及一矽化物層 23 0b。可另外形成諸如隔片250及源極/汲極區域206之其它 習知結構以完成具有通道區域207之非揮發性記憶體裝置 5 1。在該實施例中，關於圖丨所述之多層介電結構僅可應用 於閘極間介電層220或閘極絕緣層209。或者，該多層介電 結構可應用於閘極間介電層220及閘極絕緣層209。 參看圖6,根據另一實施例，一電容器61包括一下端電極 31〇、一形成於下端電極310之上的矽酸鹽介面層320a，及 一形成於矽酸鹽介面層320a之上以形成一電容器介電層 320的高k介電層320b。矽酸鹽介面層320a及高k介電層320b 係由關於圖1所述之介電材料形成。電容器6丨另外包含一覆 於電容器介電層320上之上端電極330。電容器61電連接至 一半導體基板300。 應注意，在本發明之精神及範疇内，圖1至圖6所示之基 板1 〇可為半導體或導體，諸如摻雜的多晶矽。同樣，基板 10亦可為單結晶矽基板或絕緣物上矽（S0I)基板。 圖7為說明對使用參看圖4所述之實施例所形成之結構的 結構分析圖，其中矽酸鹽介面層12〇&可為HfSi〇2，且高k介 98898.doc -16 - 200537621 電層可具有式Hf〇 67Al〇 67。 參看圖7 ’符號③指示矽濃度，符號⑫指示銓濃度，且符 號③指示铭濃度。較佳地，铪及鋁二者在整個高k介電層 120b中均具有均勻之濃度。矽酸鹽介面層12〇a可包含自高k 介電層120b擴散之鋁原子，且高k介電層12〇b可包含自矽酸 鹽介面層120a擴散之矽原子。 此外’在矽酸鹽介面層丨2〇a中，鋁濃度自矽酸鹽介面層 120a之上表面朝基板1〇〇減小，且矽濃度自矽酸鹽介面 120a之上表面朝高k介電層uob之上表面減小。 或者’由式人331-：/〇2表示的高]<:介電層1201)中的}^值可自矽 酸鹽介面層120a與高k介電層120b之底表面之間的介面朝 而k介電層120b之上表面減小。a之濃度沿著高k介電層120b 之厚度具有一梯度。同樣，在高k介電層12〇b内，B之濃度 可與A之濃度成反比。換言之，y值可端視閘極介電層12〇 之向度而變化。若A與矽酸鹽介面層120a之金屬M相同，且 φ B包括與上層電極結構（諸如閘電極、控制閘極或電容器上 知電極）在化學上穩定的材料，則尤其如此。因此，用本發 明之此等實施例可形成可靠之半導體裝置結構。 根據本發明之另一態樣，區段Q中㊁與⑦之濃度可端視閘 極介電層120之高度由一些函數來步進或改變。 總之，與諸如併有氮化矽或氮氧化物介面層或無介面層 的矽酸鹽表體層（bulk layer)之先前技術介電層結構相比， 用本發明之實施例可改良介面特性且可保持或減少EOT(等 效氧化物厚度）。換言之，藉由結合矽酸鹽介面層12與高k 98898.doc -17- 200537621 介電層14，可達成具有改良之介面特性之低EOT(等§文氧 物厚度），該矽酸鹽介面層12之介電常數較佳大於氧化石夕 氮化矽或氮氧化物中任一者之介電常數。 在以本發明之較佳實施例描述及說明其原則之後，應明 白，可不脫離此等原則在配置與細節上修改本發明。吾等 主張在下列申請專利範圍之精神及範疇内的所有修改及變 化。 【圖式簡單說明】Metals that are oxidized, oxidized, oxidized, oxidized, steel, or oxides of barium oxide. On the other hand, the right silicate interface layer 12 is formed of rhenium silicate, and the upper 咼 k dielectric layer 14 should preferably be formed by alternately stacking the ZrO2 layer and A layer " 3 layers, plus the following will be added- The steps described are followed by heat treatment to form. In this case, because the -same 'interface characteristics of the metal in the oxalate interface layer 12 and the metal contained in the metal alloy oxide layer (high-k dielectric layer 14) can be attributed to the fact that the salt interface layer Η is higher than the upper layer The electrical continuity between the k dielectric layers 14 is improved (as noted above). Similarly, if the silicate interface layer 12 is formed of hafnium silicate, the high-k dielectric layer 14 should preferably be formed by alternately stacking the Hf02 layer and the M " 3 layer, and subsequent heat treatment as described further below. . It is more preferable that the first layer 18 has a first predetermined charge, and the second layer 20 has a second predetermined charge which is opposite to the predetermined charge of the first layer 18. Among them, it is best that the first predetermined charge is a positive fixed charge and the second predetermined charge is a negative fixed charge. According to this idea, the first layer i 8 may be formed of hafnium oxide, hammer oxide, oxidized aluminum oxide, titanium oxide, yttrium oxide, gill oxide, hafnium oxide, lanthanum oxide, or barium oxide, and the second layer 20 may be formed of aluminum oxide. form. 98898.doc -13-200537621-Therefore, according to one aspect of the present invention, it is possible to minimize the net fixed power of the high-k dielectric layer ". In view of this, in the prior art, there is a problem with fixed charges, which results in Coulomb scattering that reduces channel mobility. However, in the aspect of the present invention, the fixed charge problem of the prior art can compensate for the shape of the material formed by a material such as an oxide by correcting the positive fixed charge in the first layer 18 formed with a material such as the above-mentioned oxide or oxide. Solve the negative fixed charge in the second layer 20 to overcome, especially when the metal oxides are mixed at the atomic level or diffused during the subsequent manufacturing process. The thickness of the second layer 20 may be about half the thickness of the first layer 18. This is especially true if the first layer 18 is formed of a material such as hafnium oxide or hafnium oxide, and the second layer is formed of alumina, as the amount of fixed charge in the salt letter alumina is approximately fixed compared to that of hafnium oxide or oxidation The charge is twice as much. For example, the first layer 18 may be formed to a thickness of about 10 angstroms, and the second layer 20 may be formed to a thickness of about 5 angstroms. According to an embodiment of the present invention, the resulting structure is subsequently annealed or thermally treated 'to form a multilayer dielectric structure 15 as shown in FIG. For example, the annealing temperature may be greater than about 900 ° C., so that the first layer 18 and the second layer 20 shown in FIG. 2 are combined or mixed to form a high-k dielectric layer 14 containing at least two interdiffusion metal elements. . Preferably, the annealing temperature is about 95 ° C. More preferably, the annealing temperature is sufficiently high so that at least two metal elements are uniformly mixed in the high-k dielectric layer 14 at the atomic level to form a metal alloy oxide layer. 3, according to another aspect, before performing heat treatment or annealing to form the multilayer dielectric structure 15 shown in FIG. 1, one or more additional first and second layers 18, 20 are formed on the resulting structure. Another conductive layer 24 may be formed on the high-k 98898.doc -14-200537621 dielectric layer 14 to form various semiconductor devices. Also, prior to annealing, the uppermost layer 22 may include alumina to improve the high-k dielectric layer " And the conductive layer. In another aspect, the high-k dielectric layer 14 may be formed by mCVD (metal organic chemistry • vapor deposition) technology. Preferably, two metal elements are simultaneously supplied. The source is to form a high-k dielectric layer 14 including a metal alloy oxide. Alternatively, the metal alloy oxide layer may be formed using a reactive sputtering technique. The reactive sputtering technique involves injecting oxygen into the processing chamber during metal deposition Let's ring in the room. The invention described above can be used to form Mos (metal oxide semiconductor) transistors as described below. Similarly, the invention can also be applied to any dielectric of a semiconductor device, such as between gates of non-volatile memory The dielectric layer or the dielectric layer of the storage capacitor is all within the spirit and scope of the present invention. In detail, referring to FIG. 4, a MOS (metal oxide semiconductor) transistor 41 includes a semiconductor substrate 100 and a semiconductor substrate 100. A silicate interface layer 120a on the substrate 100, and a high-k dielectric layer 120b formed on the silicate interface layer 120a to form the gate dielectric layer 120. The silicate interface layer 120a Both the high-k dielectric layer 120b and the high-k dielectric layer 120b are formed of the dielectric material described with reference to FIG. 1. In addition, the MOS (metal oxide semiconductor) transistor 41 may further include a gate electrode 130, which includes, for example, a polycrystalline silicon. Layer 130a, a silicide layer 130b, and a source / drain region formed adjacent to the gate electrode 130. The gate electrode 130 may be formed of metal. If necessary, a spacer 150 may be formed along the opposite side of the gate electrode 130, To finish with a channel area 1 Semiconductor device 41 of 07. Referring to FIG. 5, according to another embodiment, a non-volatile memory device 5 1 98898.doc 200537621 includes a semiconductor substrate 200 and a semiconductor substrate 200 having a gate insulating layer 209 overlying the substrate 200. A floating gate 210, a silicate interface layer 220a formed on the floating gate 210, and a high-k dielectric layer formed on the silicate interface layer 220a to form a gate-to-gate dielectric layer 220 220b. Both the silicate interface layer 220a and the high-k dielectric layer 220b are formed of the dielectric material described with respect to FIG. 1. Similarly, a control gate 230 is overlaid on the inter-gate dielectric layer 220. As known in the art, the control gate 230 may include a polycrystalline silicon layer 230a and a silicide layer 230b. Other conventional structures such as a spacer 250 and a source / drain region 206 may be additionally formed to complete a nonvolatile memory device 51 having a channel region 207. In this embodiment, the multi-layer dielectric structure described in FIG. 1 can be applied only to the inter-gate dielectric layer 220 or the gate insulating layer 209. Alternatively, the multilayer dielectric structure can be applied to the inter-gate dielectric layer 220 and the gate insulating layer 209. Referring to FIG. 6, according to another embodiment, a capacitor 61 includes a lower terminal electrode 310, a silicate interface layer 320a formed on the lower electrode 310, and a silicate interface layer 320a formed to form A high-k dielectric layer 320b of a capacitor dielectric layer 320. The silicate interface layer 320a and the high-k dielectric layer 320b are formed of the dielectric material described with respect to FIG. The capacitor 6 further includes an upper terminal electrode 330 overlying the capacitor dielectric layer 320. The capacitor 61 is electrically connected to a semiconductor substrate 300. It should be noted that within the spirit and scope of the present invention, the substrate 10 shown in FIGS. 1 to 6 may be a semiconductor or a conductor, such as doped polycrystalline silicon. Similarly, the substrate 10 may be a single crystal silicon substrate or a silicon-on-insulator (SOI) substrate. FIG. 7 is a structural analysis diagram illustrating a structure formed by using the embodiment described with reference to FIG. 4, wherein the silicate interface layer 12 ＆ amp; may be HfSi〇 2 and high-k 98898.doc -16-200537621 The electrical layer may have a formula Hf67A67. Referring to FIG. 7, the symbol ③ indicates the silicon concentration, the symbol ⑫ indicates the radon concentration, and the symbol ③ indicates the concentration of the silicon. Preferably, both hafnium and aluminum have uniform concentrations throughout the high-k dielectric layer 120b. The silicate interface layer 120a may include aluminum atoms diffused from the high-k dielectric layer 120b, and the high-k dielectric layer 120a may include silicon atoms diffused from the silicate interface layer 120a. In addition, in the silicate interface layer 20a, the aluminum concentration decreases from the upper surface of the silicate interface layer 120a toward the substrate 100, and the silicon concentration from the upper surface of the silicate interface layer 120a toward the high-k substrate. The upper surface of the electric layer uob decreases. Or 'high represented by Formula 331-: / 〇2] <: The value of ^ in the dielectric layer 1201) can be obtained from the interface between the silicate interface layer 120a and the bottom surface of the high-k dielectric layer 120b The upper surface of the k dielectric layer 120b decreases. The concentration of a has a gradient along the thickness of the high-k dielectric layer 120b. Similarly, in the high-k dielectric layer 12b, the concentration of B may be inversely proportional to the concentration of A. In other words, the value of y may vary depending on the orientation of the gate dielectric layer 120. This is especially true if A is the same as metal M of the silicate interface layer 120a, and φB includes a material that is chemically stable with the upper electrode structure (such as a gate electrode, control gate, or capacitor known electrode). Therefore, a reliable semiconductor device structure can be formed using these embodiments of the present invention. According to another aspect of the present invention, the concentration of ytterbium and ytterbium in the segment Q can be stepped or changed by some functions depending on the height of the gate dielectric layer 120. In summary, compared with prior art dielectric layer structures such as a silicon nitride or oxynitride interface layer or a silicate bulk layer without an interface layer, embodiments of the present invention can improve interface characteristics and EOT (equivalent oxide thickness) can be maintained or reduced. In other words, by combining the silicate interface layer 12 with the high-k 98898.doc -17- 200537621 dielectric layer 14, a low EOT (e.g., § oxygen oxide thickness) with improved interface characteristics can be achieved. The silicate interface The dielectric constant of the layer 12 is preferably larger than the dielectric constant of any of silicon oxide, silicon nitride, or oxynitride. After the principles of the present invention have been described and illustrated, it should be clear that the present invention can be modified in configuration and details without departing from these principles. We claim all modifications and changes within the spirit and scope of the following patent application scope. [Schematic description]
圖1為說明根據本發明之一實施例之半導體裝置的橫截 面視圖。 圖2為根據本發明之另一實施例之半導體裝置的橫截面 視圖。 圖3為根據本發明之另一實施例之半導體裝置的橫截面 視圖。 圖4說明用於MOS(金屬氧化物半導體）電晶體中的本發 明之一實施例。 圖5說明用於非揮發性記憶體裝置中的本發明之一實施 例0 圖6說明用於電容器中的本發明之一實施例。 圖7為說明對使用參看圖4所述之實施例而形成之結構的 結構分析。 【主要元件符號說明】 10 半導體基板 12 矽酸鹽介面層 98898.doc • 18 - 200537621 14 高k介電層 15 多層介電結構 18 第一層 20 第二層 22 最上層 24 導電層 41 MOS(金屬氧化物半導體）電晶體 51 非揮發性記憶體裝置FIG. 1 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention. FIG. 2 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention. FIG. 3 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention. Fig. 4 illustrates an embodiment of the present invention used in a MOS (metal oxide semiconductor) transistor. Fig. 5 illustrates an embodiment of the present invention used in a non-volatile memory device. Fig. 6 illustrates an embodiment of the present invention used in a capacitor. FIG. 7 is a structural analysis illustrating a structure formed using the embodiment described with reference to FIG. 4. FIG. [Description of main component symbols] 10 Semiconductor substrate 12 Silicate interface layer 98898.doc • 18-200537621 14 High-k dielectric layer 15 Multi-layer dielectric structure 18 First layer 20 Second layer 22 Top layer 24 Conductive layer 41 MOS ( Metal oxide semiconductor) transistor 51 non-volatile memory device
61 電容器 100 半導體基板 107 通道區域 120 閘極介電層 120a 石夕酸鹽介面層 120b 高k介電層 130 閘電極 130a 多晶矽層 130b 矽化物層 150 隔片 200 半導體基板 206 源極/ >及極區 207 通道區域 209 閘極絕緣層 210 浮動閘極 220 閘極間介電層 98898.doc -19- 200537621 220a 石夕酸鹽介面層 220b 高k介電層 230 控制閘極 230a 多晶石夕層 230b 矽化物層 250 隔片 300 半導體基板 310 下端電極 320 電容器介電層 320a 矽酸鹽介面層 320b 高k介電層 330 上端電極 98898.doc -20-61 capacitor 100 semiconductor substrate 107 channel area 120 gate dielectric layer 120a osmite interface layer 120b high-k dielectric layer 130 gate electrode 130a polycrystalline silicon layer 130b silicide layer 150 spacer 200 semiconductor substrate 206 source / Pole region 207 Channel region 209 Gate insulation layer 210 Floating gate 220 Dielectric layer between gates 98898.doc -19- 200537621 220a Stone salt interface layer 220b High-k dielectric layer 230 Control gate 230a Polycrystalline stone Layer 230b silicide layer 250 spacer 300 semiconductor substrate 310 lower electrode 320 capacitor dielectric layer 320a silicate interface layer 320b high-k dielectric layer 330 upper electrode 98898.doc -20-
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| KR1020040005817A KR100678626B1 (en) | 2004-01-29 | 2004-01-29 | Multilayer dielectric film of microelectronic device and manufacturing method thereof |
| US11/027,256 US7371633B2 (en) | 2001-02-02 | 2004-12-30 | Dielectric layer for semiconductor device and method of manufacturing the same |
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| US6844604B2 (en) * | 2001-02-02 | 2005-01-18 | Samsung Electronics Co., Ltd. | Dielectric layer for semiconductor device and method of manufacturing the same |
| JP2003026520A (en) * | 2001-07-11 | 2003-01-29 | Sumitomo Chem Co Ltd | Insecticide and nematicide composition |
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2005
- 2005-01-27 JP JP2005019030A patent/JP4722501B2/en not_active Expired - Fee Related
- 2005-01-28 TW TW094102747A patent/TWI282128B/en not_active IP Right Cessation
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7910981B2 (en) | 2006-10-03 | 2011-03-22 | Macronix International Co., Ltd. | Semiconductor device and method of manufacturing the same |
| US8207571B2 (en) | 2006-10-03 | 2012-06-26 | Macronix International Co., Ltd. | Non-volatile memory device with a threshold voltage change rate controlled by gate oxide phase |
| US8378410B2 (en) | 2006-10-03 | 2013-02-19 | Macronix International Co., Ltd. | Semiconductor device and method of manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2005217409A (en) | 2005-08-11 |
| CN100474613C (en) | 2009-04-01 |
| JP4722501B2 (en) | 2011-07-13 |
| TWI282128B (en) | 2007-06-01 |
| CN1655362A (en) | 2005-08-17 |
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