TW200624010A - High speed circuitized substrate with reduced thru-hole stub, method for fabrication and information handling system utilizing same - Google Patents

High speed circuitized substrate with reduced thru-hole stub, method for fabrication and information handling system utilizing same

Info

Publication number
TW200624010A
TW200624010A TW094132230A TW94132230A TW200624010A TW 200624010 A TW200624010 A TW 200624010A TW 094132230 A TW094132230 A TW 094132230A TW 94132230 A TW94132230 A TW 94132230A TW 200624010 A TW200624010 A TW 200624010A
Authority
TW
Taiwan
Prior art keywords
circuitized substrate
thru
substrate
high speed
handling system
Prior art date
Application number
TW094132230A
Other languages
Chinese (zh)
Other versions
TWI403251B (en
Inventor
Benson Chan
John M Lauffer
Original Assignee
Endicott Interconnect Tech Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/955,741 external-priority patent/US6995322B2/en
Application filed by Endicott Interconnect Tech Inc filed Critical Endicott Interconnect Tech Inc
Publication of TW200624010A publication Critical patent/TW200624010A/en
Application granted granted Critical
Publication of TWI403251B publication Critical patent/TWI403251B/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/877—Bump connectors and die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

A circuitized substrate including a plurality of conductive and dielectric layers and also a plurality of conductive thru-holes therein for passing high speed signals, e.g., from one component to another mounted on the substrate. The substrate utilizes a signal routing pattern which uses the maximum length of each of the thru-holes wherever possible to thereby substantially eliminate signal loss (noise) due to thru-hole "stub" resonance. A multilayered circuitized substrate assembly using more than one circuitized substrate, an electrical assembly using a circuitized substrate and one or more electrical components, a method of making the circuitized substrate and an information handling system incorporating one or more circuitized substrate assemblies and attached components are also provided.
TW094132230A 2004-09-30 2005-09-19 High-speed circuitized substrate having reduced perforated conductor bars, method of manufacturing the same, and data processing system using the same TWI403251B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/955,741 US6995322B2 (en) 2003-01-30 2004-09-30 High speed circuitized substrate with reduced thru-hole stub, method for fabrication and information handling system utilizing same

Publications (2)

Publication Number Publication Date
TW200624010A true TW200624010A (en) 2006-07-01
TWI403251B TWI403251B (en) 2013-07-21

Family

ID=36377943

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094132230A TWI403251B (en) 2004-09-30 2005-09-19 High-speed circuitized substrate having reduced perforated conductor bars, method of manufacturing the same, and data processing system using the same

Country Status (3)

Country Link
JP (1) JP2006108644A (en)
CN (1) CN1758830B (en)
TW (1) TWI403251B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI510943B (en) * 2012-07-16 2015-12-01 賽諾西斯公司 Method for designing physical characteristics of integrated circuits, method for perforated interconnection, and integrated circuit
TWI832699B (en) * 2023-02-13 2024-02-11 光林智能科技股份有限公司 Circuit board module and manufacturing method thereof

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8723047B2 (en) 2007-03-23 2014-05-13 Huawei Technologies Co., Ltd. Printed circuit board, design method thereof and mainboard of terminal product
CN101031182A (en) * 2007-03-23 2007-09-05 华为技术有限公司 Printing circuit-board and its designing method
US7645943B2 (en) * 2007-07-11 2010-01-12 Delphi Technologies, Inc. Configurable printed circuit board
TW201515530A (en) * 2013-10-11 2015-04-16 Adv Flexible Circuits Co Ltd Anti-attenuation structure of high-frequency signal connection pad in circuit board
CN107396534B (en) * 2016-05-16 2019-10-18 明泰科技股份有限公司 Impedance Matching Architecture for Transmission Lines
US10999923B2 (en) * 2018-04-26 2021-05-04 Juniper Networks, Inc. Structure for circuit interconnects
KR102602697B1 (en) * 2018-05-21 2023-11-16 삼성전자주식회사 Electronic apparatus having package base substrate
CN109661116B (en) * 2018-11-28 2021-08-03 惠州中京电子科技有限公司 Method for remedying defect of blind hole chassis for positioning circuit board
CN110740591B (en) * 2019-10-25 2021-06-25 珠海杰赛科技有限公司 A blind hole processing method of a multilayer printed board
TWI812331B (en) * 2022-07-06 2023-08-11 凌華科技股份有限公司 Circuit board structure to enhance the pdn for mobile pci express module
CN115942606A (en) * 2022-12-27 2023-04-07 东软睿驰汽车技术（沈阳）有限公司 Multi-layer circuit board and its preparation method

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5912809A (en) * 1997-01-21 1999-06-15 Dell Usa, L.P. Printed circuit board (PCB) including channeled capacitive plane structure
US5995376A (en) * 1997-05-20 1999-11-30 National Instruments Corporation Chassis which includes configurable slot 0 locations
US6160718A (en) * 1998-12-08 2000-12-12 Viking Components Multi-chip package with stacked chips and interconnect bumps
US6288902B1 (en) * 1999-05-25 2001-09-11 Hewlett-Packard Company Modular data storage system for reducing mechanical shock and vibrations
CN1316858C (en) * 2001-04-27 2007-05-16 日本电气株式会社 High frequency circuit base board and its producing method
JP3666411B2 (en) * 2001-05-07 2005-06-29 ソニー株式会社 High frequency module device
US6822876B2 (en) * 2002-02-05 2004-11-23 Force10 Networks, Inc. High-speed electrical router backplane with noise-isolated power distribution
JP3803596B2 (en) * 2002-03-14 2006-08-02 日本電気株式会社 Package type semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI510943B (en) * 2012-07-16 2015-12-01 賽諾西斯公司 Method for designing physical characteristics of integrated circuits, method for perforated interconnection, and integrated circuit
US9209129B2 (en) 2012-07-16 2015-12-08 Synopsys, Inc. Self-aligned via interconnect using relaxed patterning exposure
TWI832699B (en) * 2023-02-13 2024-02-11 光林智能科技股份有限公司 Circuit board module and manufacturing method thereof
US12363834B2 (en) 2023-02-13 2025-07-15 Leotek Corporation Circuit board module and manufacturing method thereof

Also Published As

Publication number Publication date
CN1758830A (en) 2006-04-12
CN1758830B (en) 2010-08-18
TWI403251B (en) 2013-07-21
JP2006108644A (en) 2006-04-20

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees