TW200642210A - Scalable universal serial bus architecture - Google Patents

Scalable universal serial bus architecture

Info

Publication number
TW200642210A
TW200642210A TW095103835A TW95103835A TW200642210A TW 200642210 A TW200642210 A TW 200642210A TW 095103835 A TW095103835 A TW 095103835A TW 95103835 A TW95103835 A TW 95103835A TW 200642210 A TW200642210 A TW 200642210A
Authority
TW
Taiwan
Prior art keywords
serial
coupled
serial bus
master scheduler
data
Prior art date
Application number
TW095103835A
Other languages
English (en)
Chinese (zh)
Inventor
Lee-Chee Ee
Chee-Yu Ng
Original Assignee
Koninkl Philips Electronics Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv filed Critical Koninkl Philips Electronics Nv
Publication of TW200642210A publication Critical patent/TW200642210A/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0042—Universal serial bus [USB]

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
  • Computer And Data Communications (AREA)
  • Bus Control (AREA)
TW095103835A 2005-02-08 2006-02-03 Scalable universal serial bus architecture TW200642210A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US65142905P 2005-02-08 2005-02-08

Publications (1)

Publication Number Publication Date
TW200642210A true TW200642210A (en) 2006-12-01

Family

ID=36793423

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095103835A TW200642210A (en) 2005-02-08 2006-02-03 Scalable universal serial bus architecture

Country Status (5)

Country Link
EP (1) EP1851640A2 (fr)
JP (1) JP2008530650A (fr)
CN (1) CN101180618B (fr)
TW (1) TW200642210A (fr)
WO (1) WO2006085272A2 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7886090B2 (en) * 2006-01-04 2011-02-08 Freescale Semiconductor, Inc. Method for managing under-runs and a device having under-run management capabilities
CN102163180B (zh) * 2011-01-20 2013-02-13 电子科技大学 一种i2c总线接口电路模块及其控制方法
JP2014081952A (ja) * 2014-01-08 2014-05-08 Renesas Electronics Corp ホストコントローラ

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6199137B1 (en) * 1999-01-05 2001-03-06 Lucent Technolgies, Inc. Method and device for controlling data flow through an IO controller
US6256700B1 (en) * 1999-03-30 2001-07-03 Dell Usa, L.P. Bus/port switching system and method for a computer

Also Published As

Publication number Publication date
WO2006085272A2 (fr) 2006-08-17
EP1851640A2 (fr) 2007-11-07
JP2008530650A (ja) 2008-08-07
WO2006085272A3 (fr) 2006-11-23
CN101180618B (zh) 2010-05-19
CN101180618A (zh) 2008-05-14

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