TW200701312A - Method for forming leadless semiconductor packages - Google Patents

Method for forming leadless semiconductor packages

Info

Publication number
TW200701312A
TW200701312A TW094120452A TW94120452A TW200701312A TW 200701312 A TW200701312 A TW 200701312A TW 094120452 A TW094120452 A TW 094120452A TW 94120452 A TW94120452 A TW 94120452A TW 200701312 A TW200701312 A TW 200701312A
Authority
TW
Taiwan
Prior art keywords
forming
leadframe
dambars
metal layer
die
Prior art date
Application number
TW094120452A
Other languages
Chinese (zh)
Other versions
TWI259518B (en
Inventor
Sang-Bae Park
Yong-Gill Lee
Hyung-Jun Park
Chang-Young Sohn
Original Assignee
Advanced Semiconductor Eng
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Priority to TW094120452A priority Critical patent/TWI259518B/en
Application granted granted Critical
Publication of TWI259518B publication Critical patent/TWI259518B/en
Publication of TW200701312A publication Critical patent/TW200701312A/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

The present invention includes providing a leadframe including a metal layer formed on an upper surface of the leadframe and a plurality of units in an array arrangement, in which each unit includes a die pad, a plurality of leads, and a plurality of outer dambars, adhering a die to the die pad, forming a plurality of conductive wires to electrically connect bond pads of the die with bond regions of the leads, forming an encapsulation covering the leadframe, forming a patterned photoresist layer on a lower surface of the leadframe to expose a plurality of interval regions and the outer dambars, performing an etching process to expose the metal layer located in the interval regions and the outer dambars, cutting off the metal layer located in the interval regions by a half cutting process, and performing a singulation process to singulate the units.
TW094120452A 2005-06-20 2005-06-20 Method for forming leadless semiconductor packages TWI259518B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW094120452A TWI259518B (en) 2005-06-20 2005-06-20 Method for forming leadless semiconductor packages

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW094120452A TWI259518B (en) 2005-06-20 2005-06-20 Method for forming leadless semiconductor packages

Publications (2)

Publication Number Publication Date
TWI259518B TWI259518B (en) 2006-08-01
TW200701312A true TW200701312A (en) 2007-01-01

Family

ID=37873439

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094120452A TWI259518B (en) 2005-06-20 2005-06-20 Method for forming leadless semiconductor packages

Country Status (1)

Country Link
TW (1) TWI259518B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9905515B2 (en) 2014-08-08 2018-02-27 Mediatek Inc. Integrated circuit stress releasing structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9905515B2 (en) 2014-08-08 2018-02-27 Mediatek Inc. Integrated circuit stress releasing structure

Also Published As

Publication number Publication date
TWI259518B (en) 2006-08-01

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Legal Events

Date Code Title Description
MK4A Expiration of patent term of an invention patent