TW200719476A - LDMOS with independently biased source - Google Patents
LDMOS with independently biased sourceInfo
- Publication number
- TW200719476A TW200719476A TW095124699A TW95124699A TW200719476A TW 200719476 A TW200719476 A TW 200719476A TW 095124699 A TW095124699 A TW 095124699A TW 95124699 A TW95124699 A TW 95124699A TW 200719476 A TW200719476 A TW 200719476A
- Authority
- TW
- Taiwan
- Prior art keywords
- ldmos
- base
- type substrate
- type
- separates
- Prior art date
Links
- 239000000758 substrate Substances 0.000 abstract 3
- 230000008878 coupling Effects 0.000 abstract 1
- 238000010168 coupling process Methods 0.000 abstract 1
- 238000005859 coupling reaction Methods 0.000 abstract 1
- 239000012535 impurity Substances 0.000 abstract 1
- 229910044991 metal oxide Inorganic materials 0.000 abstract 1
- 150000004706 metal oxides Chemical class 0.000 abstract 1
- 230000003071 parasitic effect Effects 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/65—Lateral DMOS [LDMOS] FETs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
- H10D62/149—Source or drain regions of field-effect devices
- H10D62/151—Source or drain regions of field-effect devices of IGFETs
- H10D62/156—Drain regions of DMOS transistors
- H10D62/157—Impurity concentrations or distributions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/113—Isolations within a component, i.e. internal isolations
- H10D62/115—Dielectric isolations, e.g. air gaps
- H10D62/116—Dielectric isolations, e.g. air gaps adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
- H10D64/512—Disposition of the gate electrodes, e.g. buried gates
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/273,222 US20070108517A1 (en) | 2005-11-12 | 2005-11-12 | LDMOS with independently biased source |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW200719476A true TW200719476A (en) | 2007-05-16 |
Family
ID=38039856
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW095124699A TW200719476A (en) | 2005-11-12 | 2006-07-06 | LDMOS with independently biased source |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US20070108517A1 (zh) |
| CN (1) | CN1964071A (zh) |
| TW (1) | TW200719476A (zh) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI426567B (zh) * | 2010-03-03 | 2014-02-11 | Himax Tech Ltd | 製造半導體裝置的方法 |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040256692A1 (en) * | 2003-06-19 | 2004-12-23 | Keith Edmund Kunz | Composite analog power transistor and method for making the same |
| US7122876B2 (en) * | 2004-08-11 | 2006-10-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Isolation-region configuration for integrated-circuit transistor |
| US8174071B2 (en) * | 2008-05-02 | 2012-05-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | High voltage LDMOS transistor |
| US20110195553A1 (en) * | 2010-02-08 | 2011-08-11 | Chun-Yu Chou | Method of fabricating semiconductor device |
| US8581339B2 (en) * | 2011-08-08 | 2013-11-12 | Macronix International Co., Ltd. | Structure of NPN-BJT for improving punch through between collector and emitter |
| JP5801713B2 (ja) * | 2011-12-28 | 2015-10-28 | 株式会社ソシオネクスト | 半導体装置とその製造方法、およびcanシステム |
| CN104103685B (zh) * | 2013-04-02 | 2018-07-06 | 中芯国际集成电路制造(上海)有限公司 | 一种具有降低纵向寄生晶体管效应的器件结构及其制作方法 |
| US9059281B2 (en) | 2013-07-11 | 2015-06-16 | International Business Machines Corporation | Dual L-shaped drift regions in an LDMOS device and method of making the same |
| CN104701373A (zh) * | 2013-12-10 | 2015-06-10 | 中芯国际集成电路制造(上海)有限公司 | Ldmos晶体管及其形成方法 |
| CN110190114B (zh) * | 2019-05-31 | 2021-01-01 | 西安电子科技大学 | 一种栅控双极-场效应复合碳化硅垂直双扩散金属氧化物半导体晶体管 |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5067002A (en) * | 1987-01-30 | 1991-11-19 | Motorola, Inc. | Integrated circuit structures having polycrystalline electrode contacts |
| US5028977A (en) * | 1989-06-16 | 1991-07-02 | Massachusetts Institute Of Technology | Merged bipolar and insulated gate transistors |
| US5112761A (en) * | 1990-01-10 | 1992-05-12 | Microunity Systems Engineering | Bicmos process utilizing planarization technique |
| US5374569A (en) * | 1992-09-21 | 1994-12-20 | Siliconix Incorporated | Method for forming a BiCDMOS |
| US6528850B1 (en) * | 2000-05-03 | 2003-03-04 | Linear Technology Corporation | High voltage MOS transistor with up-retro well |
| US6900091B2 (en) * | 2002-08-14 | 2005-05-31 | Advanced Analogic Technologies, Inc. | Isolated complementary MOS devices in epi-less substrate |
-
2005
- 2005-11-12 US US11/273,222 patent/US20070108517A1/en not_active Abandoned
-
2006
- 2006-07-06 TW TW095124699A patent/TW200719476A/zh unknown
- 2006-08-02 CN CNA2006100991885A patent/CN1964071A/zh active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI426567B (zh) * | 2010-03-03 | 2014-02-11 | Himax Tech Ltd | 製造半導體裝置的方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1964071A (zh) | 2007-05-16 |
| US20070108517A1 (en) | 2007-05-17 |
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