TW200746152A - Method and apparatus for accessing nonvolatile memory with read error by changing read reference - Google Patents

Method and apparatus for accessing nonvolatile memory with read error by changing read reference

Info

Publication number
TW200746152A
TW200746152A TW096116342A TW96116342A TW200746152A TW 200746152 A TW200746152 A TW 200746152A TW 096116342 A TW096116342 A TW 096116342A TW 96116342 A TW96116342 A TW 96116342A TW 200746152 A TW200746152 A TW 200746152A
Authority
TW
Taiwan
Prior art keywords
read
nonvolatile memory
changing
read reference
accessing nonvolatile
Prior art date
Application number
TW096116342A
Other languages
English (en)
Other versions
TWI328232B (en
Inventor
Chun-Hsiung Hung
Han-Sung Chen
Original Assignee
Macronix Int Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Macronix Int Co Ltd filed Critical Macronix Int Co Ltd
Publication of TW200746152A publication Critical patent/TW200746152A/zh
Application granted granted Critical
Publication of TWI328232B publication Critical patent/TWI328232B/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/52—Protection of memory contents; Detection of errors in memory contents
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C2029/0409—Online test

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Read Only Memory (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
TW096116342A 2006-05-08 2007-05-08 Method and apparatus for accessing nonvolatile memory with read error by changing read reference TWI328232B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US74673306P 2006-05-08 2006-05-08
US11/735,911 US7471562B2 (en) 2006-05-08 2007-04-16 Method and apparatus for accessing nonvolatile memory with read error by changing read reference

Publications (2)

Publication Number Publication Date
TW200746152A true TW200746152A (en) 2007-12-16
TWI328232B TWI328232B (en) 2010-08-01

Family

ID=38661035

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096116342A TWI328232B (en) 2006-05-08 2007-05-08 Method and apparatus for accessing nonvolatile memory with read error by changing read reference

Country Status (3)

Country Link
US (1) US7471562B2 (zh)
CN (1) CN101114530B (zh)
TW (1) TWI328232B (zh)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7773421B2 (en) * 2006-05-08 2010-08-10 Macronix International Co., Ltd. Method and apparatus for accessing memory with read error by changing comparison
US8077516B2 (en) * 2006-05-08 2011-12-13 Macronix International Co., Ltd. Method and apparatus for accessing memory with read error by changing comparison
KR101466698B1 (ko) * 2008-02-19 2014-11-28 삼성전자주식회사 메모리 장치 및 메모리 데이터 읽기 방법
JP4898858B2 (ja) * 2009-03-02 2012-03-21 パナソニック株式会社 符号化器、復号化器及び符号化方法
US8406053B1 (en) 2011-09-21 2013-03-26 Sandisk Technologies Inc. On chip dynamic read for non-volatile storage
US9036417B2 (en) 2012-09-06 2015-05-19 Sandisk Technologies Inc. On chip dynamic read level scan and error detection for nonvolatile storage
US10319460B2 (en) 2013-08-14 2019-06-11 Infineon Technologies Ag Systems and methods utilizing a flexible read reference for a dynamic read window
CN109716282B (zh) 2018-12-07 2020-06-26 长江存储科技有限责任公司 用于编程存储器系统的方法
US11043277B1 (en) * 2020-05-07 2021-06-22 Micron Technology, Inc. Two multi-level memory cells sensed to determine multiple data values

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JP2830308B2 (ja) * 1990-02-26 1998-12-02 日本電気株式会社 情報処理装置
JPH0729395A (ja) * 1993-06-25 1995-01-31 Mitsubishi Electric Corp Ｅｅｐｒｏｍ装置
US5603001A (en) * 1994-05-09 1997-02-11 Kabushiki Kaisha Toshiba Semiconductor disk system having a plurality of flash memories
US5606532A (en) * 1995-03-17 1997-02-25 Atmel Corporation EEPROM array with flash-like core
JPH09204367A (ja) * 1996-01-25 1997-08-05 Mitsubishi Electric Corp フラッシュディスクカードにおけるフラッシュメモリデータのリフレッシュ方法
US5754567A (en) * 1996-10-15 1998-05-19 Micron Quantum Devices, Inc. Write reduction in flash memory systems through ECC usage
US6839875B2 (en) * 1996-10-18 2005-01-04 Micron Technology, Inc. Method and apparatus for performing error correction on data read from a multistate memory
US5956743A (en) * 1997-08-25 1999-09-21 Bit Microsystems, Inc. Transparent management at host interface of flash-memory overhead-bytes using flash-specific DMA having programmable processor-interrupt of high-level operations
US6272659B1 (en) * 1998-05-18 2001-08-07 Cirrus Logic, Inc. Error correction code processor employing adjustable correction power for miscorrection minimization
US6041001A (en) * 1999-02-25 2000-03-21 Lexar Media, Inc. Method of increasing data reliability of a flash memory device without compromising compatibility
JP3975245B2 (ja) * 1999-12-16 2007-09-12 株式会社ルネサステクノロジ 記録再生装置および半導体メモリ
US6349056B1 (en) * 2000-12-28 2002-02-19 Sandisk Corporation Method and structure for efficient data verification operation for non-volatile memories
JP4059472B2 (ja) * 2001-08-09 2008-03-12 株式会社ルネサステクノロジ メモリカード及びメモリコントローラ
US6683817B2 (en) * 2002-02-21 2004-01-27 Qualcomm, Incorporated Direct memory swapping between NAND flash and SRAM with error correction coding
JP3796457B2 (ja) * 2002-02-28 2006-07-12 富士通株式会社 不揮発性半導体記憶装置
US6799256B2 (en) * 2002-04-12 2004-09-28 Advanced Micro Devices, Inc. System and method for multi-bit flash reads using dual dynamic references
JP3914839B2 (ja) * 2002-07-11 2007-05-16 エルピーダメモリ株式会社 半導体記憶装置
US6992932B2 (en) * 2002-10-29 2006-01-31 Saifun Semiconductors Ltd Method circuit and system for read error detection in a non-volatile memory array
US20040153902A1 (en) * 2003-01-21 2004-08-05 Nexflash Technologies, Inc. Serial flash integrated circuit having error detection and correction
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US7350044B2 (en) * 2004-01-30 2008-03-25 Micron Technology, Inc. Data move method and apparatus
JP2006048783A (ja) * 2004-08-02 2006-02-16 Renesas Technology Corp 不揮発性メモリおよびメモリカード
TWI248617B (en) * 2004-08-13 2006-02-01 Prolific Technology Inc Data storage device
US7061804B2 (en) * 2004-11-18 2006-06-13 Qualcomm Incorporated Robust and high-speed memory access with adaptive interface timing
US7447078B2 (en) * 2005-04-01 2008-11-04 Sandisk Corporation Method for non-volatile memory with background data latch caching during read operations

Also Published As

Publication number Publication date
CN101114530B (zh) 2010-06-09
TWI328232B (en) 2010-08-01
CN101114530A (zh) 2008-01-30
US20070258297A1 (en) 2007-11-08
US7471562B2 (en) 2008-12-30

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