TW200746263A - Semiconductor device including a strained superlattice between at least one pair of spaced apart stress regions and associated methods - Google Patents

Semiconductor device including a strained superlattice between at least one pair of spaced apart stress regions and associated methods

Info

Publication number
TW200746263A
TW200746263A TW095125961A TW95125961A TW200746263A TW 200746263 A TW200746263 A TW 200746263A TW 095125961 A TW095125961 A TW 095125961A TW 95125961 A TW95125961 A TW 95125961A TW 200746263 A TW200746263 A TW 200746263A
Authority
TW
Taiwan
Prior art keywords
pair
spaced apart
stress regions
semiconductor device
strained superlattice
Prior art date
Application number
TW095125961A
Other languages
Chinese (zh)
Inventor
Robert J Mears
Scott A Kreps
Original Assignee
Mears R J Llc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/457,269 external-priority patent/US7531828B2/en
Priority claimed from US11/457,276 external-priority patent/US20070015344A1/en
Application filed by Mears R J Llc filed Critical Mears R J Llc
Publication of TW200746263A publication Critical patent/TW200746263A/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/01—Manufacture or treatment
    • H10D62/021—Forming source or drain recesses by etching e.g. recessing by etching and then refilling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/751—Insulated-gate field-effect transistors [IGFET] having composition variations in the channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/798—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being provided in or under the channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/81—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation
    • H10D62/815—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation of structures having periodic or quasi-periodic potential variation, e.g. superlattices or multiple quantum wells [MQW]
    • H10D62/8161—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation of structures having periodic or quasi-periodic potential variation, e.g. superlattices or multiple quantum wells [MQW] potential variation due to variations in composition or crystallinity, e.g. heterojunction superlattices
    • H10D62/8162—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation of structures having periodic or quasi-periodic potential variation, e.g. superlattices or multiple quantum wells [MQW] potential variation due to variations in composition or crystallinity, e.g. heterojunction superlattices having quantum effects only in the vertical direction, i.e. layered structures having quantum effects solely resulting from vertical potential variation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/81—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation
    • H10D62/815—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation of structures having periodic or quasi-periodic potential variation, e.g. superlattices or multiple quantum wells [MQW]
    • H10D62/8161—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation of structures having periodic or quasi-periodic potential variation, e.g. superlattices or multiple quantum wells [MQW] potential variation due to variations in composition or crystallinity, e.g. heterojunction superlattices
    • H10D62/8162—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation of structures having periodic or quasi-periodic potential variation, e.g. superlattices or multiple quantum wells [MQW] potential variation due to variations in composition or crystallinity, e.g. heterojunction superlattices having quantum effects only in the vertical direction, i.e. layered structures having quantum effects solely resulting from vertical potential variation
    • H10D62/8163—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation of structures having periodic or quasi-periodic potential variation, e.g. superlattices or multiple quantum wells [MQW] potential variation due to variations in composition or crystallinity, e.g. heterojunction superlattices having quantum effects only in the vertical direction, i.e. layered structures having quantum effects solely resulting from vertical potential variation comprising long-range structurally-disordered materials, e.g. one-dimensional vertical amorphous superlattices

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

A semiconductor device may include at least one pair of spaced apart stress regions, and a strained superlattice layer between the at least one pair of spaced apart stress regions and including a plurality of stacked groups of layers. Each group of layers of the strained superlattice layer may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
TW095125961A 2005-07-15 2006-07-14 Semiconductor device including a strained superlattice between at least one pair of spaced apart stress regions and associated methods TW200746263A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US69994905P 2005-07-15 2005-07-15
US11/457,269 US7531828B2 (en) 2003-06-26 2006-07-13 Semiconductor device including a strained superlattice between at least one pair of spaced apart stress regions
US11/457,276 US20070015344A1 (en) 2003-06-26 2006-07-13 Method for Making a Semiconductor Device Including a Strained Superlattice Between at Least One Pair of Spaced Apart Stress Regions

Publications (1)

Publication Number Publication Date
TW200746263A true TW200746263A (en) 2007-12-16

Family

ID=37070665

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095125961A TW200746263A (en) 2005-07-15 2006-07-14 Semiconductor device including a strained superlattice between at least one pair of spaced apart stress regions and associated methods

Country Status (6)

Country Link
EP (1) EP1905092A1 (en)
JP (1) JP2009500873A (en)
AU (1) AU2006270125A1 (en)
CA (1) CA2612127A1 (en)
TW (1) TW200746263A (en)
WO (1) WO2007011789A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9685514B2 (en) 2012-05-09 2017-06-20 Taiwan Semiconductor Manufacturing Co., Ltd. III-V compound semiconductor device having dopant layer and method of making the same

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8524562B2 (en) * 2008-09-16 2013-09-03 Imec Method for reducing Fermi-Level-Pinning in a non-silicon channel MOS device
US9445967B2 (en) * 2008-10-29 2016-09-20 Koninklijke Philips N.V. Automated CPR device

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6621131B2 (en) * 2001-11-01 2003-09-16 Intel Corporation Semiconductor transistor having a stressed channel
US6830964B1 (en) * 2003-06-26 2004-12-14 Rj Mears, Llc Method for making semiconductor device including band-engineered superlattice
US20040262683A1 (en) * 2003-06-27 2004-12-30 Bohr Mark T. PMOS transistor strain optimization with raised junction regions
US6946350B2 (en) * 2003-12-31 2005-09-20 Intel Corporation Controlled faceting of source/drain regions

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9685514B2 (en) 2012-05-09 2017-06-20 Taiwan Semiconductor Manufacturing Co., Ltd. III-V compound semiconductor device having dopant layer and method of making the same

Also Published As

Publication number Publication date
CA2612127A1 (en) 2007-01-25
AU2006270125A1 (en) 2007-01-25
EP1905092A1 (en) 2008-04-02
WO2007011789A1 (en) 2007-01-25
JP2009500873A (en) 2009-01-08

Similar Documents

Publication Publication Date Title
TW200707649A (en) Method for making a semiconductor device including a superlattice having at least one group of substantially undoped layers
TW200715549A (en) Method for making a semiconductor device including band-engineered superlattice using intermediate annealing
TW200742061A (en) Semiconductor device comprising a lattice matching layer
TW200717794A (en) Semiconductor device including a superlattice having at least one group of substantially undoped layers
TW200723451A (en) Method for making a semiconductor device including a superlattice with regions defining a semiconductor junction
TW200701452A (en) Semiconductor device including a superlattice with regions defining a semiconductor junction
TW200707591A (en) Method for making a semiconductor device comprising a superlattice dielectric interface layer
WO2005013371A3 (en) Semiconductor device including band-engineered superlattice
WO2007075942A3 (en) Electronic device including a selectively polable superlattice and associated methods
TW200742057A (en) Spintronic devices with constrained spintronic dopant
WO2006107897A3 (en) Semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junction
TW200644234A (en) Method for making a semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junction
TW200729481A (en) Semiconductor device including a front side strained superlattice layer and a back side stress layer
WO2006127225A3 (en) Semiconductor device comprising a superlattice dielectric interface layer
GB2417133B (en) Method for fabricating lateral semiconductor device
TW200746263A (en) Semiconductor device including a strained superlattice between at least one pair of spaced apart stress regions and associated methods
TW200620279A (en) MRAM over sloped pillar and the manufacturing method thereof
ATE407378T1 (en) THREE-DIMENSIONAL PHOTONIC CRYSTAL AND FUNCTIONAL DEVICE CONTAINING SAME
TW200742058A (en) Semiconductor device including a strained superlattice and overlying stress layer and related methods
TW200725752A (en) Method for making a semiconductor device including regions of band-engineered semiconductor superlattice to reduce device-on resistance
TW200709410A (en) Semiconductor device including a strained superlattice layer above a stress layer and associated methods
TW200711124A (en) Method for making a microelectromechanical systems (MEMS) device including a superlattice
TW200707723A (en) Method for making a semiconductor device having a semiconductor-on-insulator (SOI) configuration and including a superlattice on a thin semiconductor layer
TW200721480A (en) Method for making a semiconductor device including a front side strained superlattice layer and a back side stress layer
TW200717701A (en) Method for making a semiconductor device including shallow trench isolation (STI) regions with a superlattice therebetween