200822302 20803twf.doc/t 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種封裝基板，且特別是有關於一種 具有埋入式電容之封裝基板。 【先前技術】 埋入式電容（embedded capacitor)可整合於封裝基板 (package substrate)的製程中，並可增進電子構裝中主動 元件（active component)的效率，提昇電氣性質，以及降 低組裝的成本，因而成為電子載板（carrier )的主流趨勢。 目别國内所開發的埋入式電容多以小尺寸的陶莞電容為 主’一般區分為單層陶瓷電容（Single iayer ceramic capacitors, MLCC)以及積層陶瓷電容（Multilayercemmic capacitors, MLCC )，也可稱為獨立式電容（出似你 capacitor)，但由於傳統的獨立式電容的電容量較低，且介 電係數較低，因而無法提昇傳統線路基板的性能。 a月參考圖1，其缘示習知一種内埋獨立式電容的封裝 基板的示意圖。此封裝基板100的内部結構及其製程大致 如下·首先，提供一芯板（c〇re b〇ard) 110、多個介電材 料121〜124以及焊接多個獨立式電容13〇的二銅箔（c〇pper foil) 142、144，接著對位並壓合這些介電材料121〜124 及具有獨立式電容13〇的二銅箔142、144於芯板11〇上， 以使二銅箔142、144及獨立式電容13〇分別位於上層的介 電材料121、122之間以及下層的介電材料123、124之間， 以形成一核心疊層板（corelaminatedb〇ard) 16〇。接著， 5 200822302 20803twf.doc/t 以機械鑽孔的方式，形成多數個導通孔15〇於核心疊層板 160内’避開獨立式電容130,並導通上下二銅箔μ〕、144。 此外’核心疊層板160的表面線路162也可使用導電孔（via hole) 164與獨立式電容130相導通。 值得注思的是，由於獨立式電容13〇必須避開導通孔 150的位置，使得電容13〇的放置位置及可用的面積受限 =導通孔150的數量及位置，降低自由度。同時，在基板 壓合的過程中，容易造成獨立式電容130的破壞及損傷， 、 因而降低其可靠度。 【發明内容】 ^本赉明的目的就是在提供一種具有埋入式電容的封 裝基板，用以提高埋入式電容的配置空間及自由度。 壯本叙明的另一目的是提供一種具有埋入式電容的封 ^基板，其藉由高介電常數及低介電損失的介電材料來提 高封裝基板的性能。 Q 壯本叙明的另一目的是提供一種具有埋入式電容的封 • 裝基板，其藉由覆蓋一保護層以避免埋入式電容的損傷。 ‘ 本發明提出一種具有埋入式電容的封裝基板，包括一 ，路芯板、至少一介電層、至少一埋入式電容以及至少一 =屬層。線路芯板之表面具有至少一線路層，且線路芯板 具有至少_導通孔，其與線路層導通。此外，介電層覆蓋 於線，層上，且介電層中具有至少一導電孔。另外，埋二 谷14至屬層相連接，並埋入於介電層中，其中金屬層 復蓋於介電層上，並藉由導電孔與線路層相導通。 6 200822302 20803twf.doc/t 弟線路心板、至少一埋入式電容、匕括 電層。第一線路芯板之表面具有至板以 弟一線路芯板具有至少一第一導诵$夕孟屬層，且 通。此外，埋入式電容埋入於第:二金：層相導 :相連接。第二線路芯板之表面4=，金屬 路芯板具有至少—黛 另、、泉路層’且第二線 介電層疊合於第一第其:線路層相導通。另外， ,nni κ路心板與弟二線路芯板之間。 -線路夂電容的封裝基板，包括 -線路層。線路芯板之表：且c介電層以及至少 板具有至少—導通孔，苴二^ 金屬層，且線路芯 電容埋入於線路芯板中了二全;im。此外，埋入式 於線路芯板上，而介電且 日相連接。介電層覆蓋BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a package substrate, and more particularly to a package substrate having a buried capacitor. [Previous Technology] An embedded capacitor can be integrated in a package substrate process, and can improve the efficiency of an active component in an electronic package, improve electrical properties, and reduce assembly cost. And thus become the mainstream trend of electronic carriers. The embedded capacitors developed in China are mainly based on small-sized ceramic capacitors, which are generally classified into Single iayer ceramic capacitors (MLCC) and Multilayercemmic capacitors (MLCC). It is called a stand-alone capacitor (like your capsule), but because of the low capacitance and low dielectric constant of conventional stand-alone capacitors, the performance of traditional circuit boards cannot be improved. Referring to Fig. 1, a schematic view of a conventional package substrate in which a self-contained capacitor is embedded is shown. The internal structure of the package substrate 100 and the process thereof are as follows. First, a core plate 110, a plurality of dielectric materials 121 to 124, and two copper foils for soldering a plurality of independent capacitors 13A are provided. (c〇pper foil) 142, 144, and then align and press the dielectric materials 121 to 124 and the two copper foils 142 and 144 having the free-standing capacitors 13A on the core plate 11 to make the two copper foils 142 144 and the freestanding capacitor 13 are respectively located between the upper dielectric materials 121, 122 and the lower dielectric materials 123, 124 to form a core laminate 16 〇. Next, 5 200822302 20803twf.doc/t is formed by mechanical drilling, and a plurality of via holes 15 are formed in the core laminate 160 to avoid the freestanding capacitor 130 and to turn on the upper and lower copper foils μ, 144. In addition, the surface line 162 of the core laminate 160 can also be electrically connected to the freestanding capacitor 130 using a via hole 164. It is worth noting that since the free-standing capacitor 13〇 must avoid the position of the via 150, the placement position and available area of the capacitor 13〇 are limited = the number and position of the via 150 are reduced, and the degree of freedom is reduced. At the same time, in the process of pressing the substrate, the damage and damage of the free-standing capacitor 130 are easily caused, thereby reducing the reliability. SUMMARY OF THE INVENTION The purpose of the present invention is to provide a package substrate having a buried capacitor for improving the arrangement space and degree of freedom of the buried capacitor. Another object of the present invention is to provide a package substrate having a buried capacitor which improves the performance of the package substrate by a dielectric material having a high dielectric constant and a low dielectric loss. Another object of Q Zhuang is to provide a package substrate with a buried capacitor that covers a protective layer to avoid damage to the buried capacitor. The present invention provides a package substrate having a buried capacitor, comprising: a core board, at least one dielectric layer, at least one buried capacitor, and at least one sub-layer. The surface of the line core has at least one wiring layer, and the circuit core has at least a via which is electrically connected to the wiring layer. In addition, the dielectric layer covers the lines, the layers, and the dielectric layer has at least one conductive via. In addition, the buried valley 14 is connected to the genus layer and buried in the dielectric layer, wherein the metal layer covers the dielectric layer and is electrically connected to the wiring layer through the conductive holes. 6 200822302 20803twf.doc/t Brother circuit board, at least one buried capacitor, including electrical layer. The surface of the first circuit core board has at least one first guiding layer to the board and the core board of the board. In addition, the buried capacitor is buried in the first: two gold: layer phase conduction: connected. The surface of the second circuit core board 4 =, the metal core board has at least - 黛 another, the spring road layer ' and the second line is dielectrically laminated to the first one: the circuit layer is electrically connected. In addition, between the nni κ road core board and the second line core board. - The package substrate of the tantalum capacitor, including - the wiring layer. The circuit core board: and the c dielectric layer and at least the board have at least a via hole, a metal layer, and the line core capacitor is buried in the line core board; In addition, it is embedded in the line core board and dielectrically connected to the solar phase. Dielectric layer coverage
Cj 蓋於介電層上，並與埋;電性^埋孔。另外，線路層覆 依照本發明的實施例所 第—保護層，其覆蓋於埋 〔封裝基板更包括- 層具有-開孔，而埋入式電。此外，上述之金屬 裝基板更包括-第二保護層，面顯露於開孔中，封 面上。其中，M一仅罐麻 其復盍於此埋入式電容之表 而第二保護屬之材質為環氧樹脂或聚醯亞胺， 依照本; 少—表面線路層，其配置於=之封裝基板更包括至 層具有至少—接點，其與 之表面上，表面線路 ^㈢或線路層電性連接。此外， 7 200822302 20803twf.doc/t 封震基板更包括-防銲層， 具有至少-開口，其顯露接點设皿表面線路層，而防銲層 f發明又提出—種具有埋人式電容 心板、一埋入式電容、— 衷土板匕括 人式電容埋人於m 二―金屬層。埋 上。此外，金屬層覆蓋於芯板上容 之材質口==醯亞胺，二保護層 置於ΐί::ίΓ入式電容因基板結構的改良，因此可配 配置”田 1及自不需避開導通孔的位置，故可增加其 低介電損失的陶究複合材料來取代傳統的獨立 谷’進而調高封裝基板的性能。再者，本發明中之埋 免護層覆蓋’因而在基板壓合過程中，可避 兄皮私或知傷，進而提高其可靠度。 為讓本發明之上述和其他目的、特徵和優點能更明顯 f重’下文特舉較佳實施例，並配合所附圖式，作詳細說 ^4 下 〇 【實施方式】 圖2繪示本發明第一實施例之具有埋入式電容的封裝 土板的局部示意圖。此封裝基板200主要包括一線路芯板 8 200822302 20803twf.doc/t 210、一介電層220、至少一埋入式電容230以及一金屬層 240。其中，線路怒板210例如是以玻纖布（giass拙er) 和環氧樹脂（epoxy resin)為絕緣材料的銅箔基板，以增 加封裝基板200的強度及支撐性。此外，線路芯板21〇還 具有至少一導通孔216，其可藉由機械鑽孔的方式先形成 一通孔，再以化學電鍍的方式形成一導體於通孔的内壁 J 上，以形成導通上、下銅箔的導通孔216，而銅箔經過圖 ' 案化蝕刻之後，可形成所需的線路層，以傳遞訊號。 、 如圖2所示，本發明之埋入式電容230配置於介電層 220中，而介電層220可包括第一介電層222以及一第二 介電層224,其分別覆蓋於線路芯板21〇的第一線路層212 以及第二線路層214上。值得注意的是，由於導通孔216 預先形成於線路芯板210中，因此不需在後續的製程中形 成，因此可避免導通孔216的位置影響埋入式電容的配置 空間。如圖2所示，埋入式電容230可配置於導通孔216 下方的第一介電層222中，因此不受導通孔210的影響， 故可增加埋入式電容230的配置空間及自由度。 > 在本實施例中，埋入式電容230可為獨立式電容，其 預先焊接於一金屬層240 (例如銅箔）上，再將介電層220 及金屬層240壓合於線路芯板210上，以使埋入式電容230 内埋於介電層220中。當然，本發明更可利用高介電常數 的環氧樹脂-陶瓷複合材料（Epoxy-ceramic composite)作 為介電材料232，以提高電容量。其中，金屬層24〇可包 括一第一金屬層242以及一第二金屬層244，第一金屬層 9 200822302 20803twf.doc/tCj is covered on the dielectric layer and buried; electrical ^ buried hole. In addition, the circuit layer is covered by a protective layer according to an embodiment of the present invention, which covers the buried [the package substrate further includes a layer having an opening and a buried type of electricity. In addition, the metal substrate further includes a second protective layer, and the surface is exposed in the opening and the sealing surface. Among them, M-only can be reclaimed on the surface of the buried capacitor and the second protection material is epoxy resin or polyimine, according to the present; less-surface circuit layer, which is arranged in the package of = The substrate further includes a layer having at least a contact electrically connected to the surface line (3) or the circuit layer. In addition, 7 200822302 20803twf.doc/t the shock-proof substrate further comprises a solder mask, having at least an opening, which exposes the surface layer of the contact plate, and the solder resist layer f is further proposed to have a buried capacitor core The board, a buried capacitor, and the earth-filled board are buried in the m-metal layer. Buried. In addition, the metal layer covers the material of the core plate == 醯 imine, and the second protective layer is placed on the ΐί:: Γ Γ 电容 因 因 因 因 因 因 因 因 因 因 因 因 因 因 因 因 因 因 因 因 因 因 因 因 因 因 因 因 因 因The position of the via hole can increase the ceramic dielectric material with low dielectric loss to replace the traditional independent valley' and thereby improve the performance of the package substrate. Furthermore, the buried layer of the present invention covers the substrate and thus the substrate is pressed. The above and other objects, features and advantages of the present invention will become more apparent in the course of the <RTIgt; </ RTI> </ RTI> <RTIgt; FIG. 2 is a partial schematic view of a packaged earth plate having a buried capacitor according to a first embodiment of the present invention. The package substrate 200 mainly includes a circuit core board 8 200822302 20803 twf.doc/t 210, a dielectric layer 220, at least one buried capacitor 230, and a metal layer 240. The line anger plate 210 is, for example, a gibbs cloth and an epoxy resin. ) a copper foil substrate that is an insulating material The strength of the package substrate 200 and the supportability of the package substrate 200. In addition, the circuit core plate 21A further has at least one via hole 216, which can form a through hole by mechanical drilling, and then form a conductor through chemical plating. The inner wall J of the hole is formed to form a via hole 216 for conducting the upper and lower copper foils, and after the copper foil is patterned and etched, a desired circuit layer can be formed to transmit a signal. As shown in FIG. The buried capacitor 230 of the invention is disposed in the dielectric layer 220, and the dielectric layer 220 may include a first dielectric layer 222 and a second dielectric layer 224 respectively covering the first line of the circuit core board 21〇 The layer 212 and the second circuit layer 214. It is noted that since the via hole 216 is formed in the circuit core board 210 in advance, it does not need to be formed in a subsequent process, so that the position of the via hole 216 can be prevented from affecting the buried type. As shown in FIG. 2, the buried capacitor 230 can be disposed in the first dielectric layer 222 under the via hole 216, and thus is not affected by the via hole 210, so that the buried capacitor 230 can be added. Configure space and degrees of freedom. > in this In the embodiment, the buried capacitor 230 can be a self-contained capacitor, which is soldered to a metal layer 240 (for example, a copper foil), and then the dielectric layer 220 and the metal layer 240 are pressed onto the circuit core 210. The buried capacitor 230 is buried in the dielectric layer 220. Of course, the present invention can utilize a high dielectric constant epoxy-ceramic composite as the dielectric material 232 to increase the capacitance. The metal layer 24A may include a first metal layer 242 and a second metal layer 244, the first metal layer 9 200822302 20803twf.doc/t
242覆蓋於第一介雷展299 p ^ A 斤人+ 日2上，且弟一金屬層242可藉由 弟一介電層222中的導電:^ ώ楚 J守电孔226與弟一線路層212相導 通。此外，第二金屬層244覆蓋於第二介電層224上，且 ^金屬層244可藉由第二介電層η4中的導電孔挪與 弟一線路層214相導通。 ϋ所述，傳統的獨立式電容的電容量較低，本實施242 is overlaid on the first Jielei exhibition 299 p ^ A kg person + day 2, and the brother-metal layer 242 can be electrically conductive through the dielectric layer 222: ^ ώ楚J 守电孔226 and brother-one line Layer 212 is electrically conductive. In addition, the second metal layer 244 covers the second dielectric layer 224, and the metal layer 244 can be electrically connected to the wiring layer 214 through the conductive holes in the second dielectric layer η4. As described in the above, the capacitance of the conventional free-standing capacitor is low, this implementation
ϋ改、為^介電常數的環氧樹脂_喊複合電容或其他陶 瓮同:子複δ電谷’將可提高電容量，減少介電損失，進 而提高封裝基板200的性能。 、 狀在本實施例中，完成埋入式電容的組裝製程之後，封 裝基板2GG更可依據電路的需求，利用增層法依序製作多 2内連線結構25G’以使原來四層線路的基板可增加為 八曰八層十層或十二層的線路。其中，相鄰二線路層 之間的”電層254可藉由雷射鑽孔形成多個凹孔以及 填^導電材料，以使相冑二線路層252相互導通。最後， 封裝基板200的最外層的表面線路層256再以一防銲層 260覆蓋，而防銲層26〇具有至少一開口加]， ^ 表面線路層256的接點。在本實施例中，上接點2二^ 電丨生連接至少一晶片或被動元件（未繪示），而下接點258b 用以電f生連接一印刷電路板（未繪示），以使封襄基板2〇〇 作為上、下元件之間訊號傳輸的媒介。 接著，圖3繪示本發明第二實施例之具有埋入式電容 的封裝基板的局部示意圖。此封裝基板300主要包括一芯 板310、至少一埋入式電容330、一第一保護層338以及一 10 200822302 20803twf.doc/t 金屬層340。其中，芯板3丨〇例如是以破纖布（glass fiber ) 和環氧樹脂（epoxy resin)為絕緣材料的基板，以增加封 I基板300的強度及支撐性。此外，埋入式電容mo可埋 入於芯板310中，並與金屬層340相連接。在本實施例中， 埋入式電容330可為高介電常數的環氧樹脂-陶瓷複合電 容或其他陶瓷/高分子複合電容，經高溫燒結後形成於金屬 ^ 層340上，再覆蓋一電極材料於介電材料332上，以形成 “ 一電極334連接金屬層340。 ^ 值得注意的是，為了避免壓合的過程中，破壞或損傷 埋入式電容330，在壓合基板之前，更可以第一保護層338 覆蓋於埋入式電容330上。此第一保護層338例如是環氧 树月曰或聚醯亞胺之類的高分子材料，具有較佳的抗壓強 度，更可預防壓合前的蝕刻製程、電鍍製程以及表面處理 的反應劑影響埋入式電容330及其電極的特性。此外，在 金屬層340的另一側的開孔342内，亦可藉由選擇性填入 一第二保護層336，以覆蓋埋入式電容330的一表面，其 • 材質及功效如同第一保護層338，同樣可避免埋入式電容 330損壞。 圖4繪示本發明第三實施例之具有埋入式電容的封裝 基板的局部示意圖。此封裝基板4〇〇主要包括一第一線路 芯板410、一介電層420、至少一埋入式電容43〇以及—第 一，路芯板440。其中，第一與第二線路芯板41〇、44〇例 疋以玻纖布（glassflber)和J展氧樹脂（ep〇Xyresin)為 絕緣材料的銅箔基板，以增加封裝基板4〇〇的強度及支撐 200822302 20803twf.doc/t 〆匕卜；丨電層420亦可為固化態或半固化態的玻纖環 乳^脂，其疊合於第-與第二線路芯板41G、44G之間。在 =貝施例中，第一線路芯板41〇的二相對表面分別具有一 金屬層412，且第—線路怒板410具有至少-第一導通孔 =二其與金屬層412相導通，而埋入式電容43〇可埋入於 第-線路芯板41G中，並與金屬層412相連接。同樣，第 二線路芯板_的二相對表面分別具有-線路層442，且 Ϊ 板_具有至少一第二導通孔444，其與線路 層442相導通。 t亡所示，本實施例之埋入式電容430可為高介電常 ，的環氧樹胳-陶瓷複合電容或其他陶瓷/高分子複合電 容，以增~加封裝基板400的性能。此外，在壓合基板之前， 圖3之第一保護層338更可覆蓋於圖4之埋入式電容43〇 上。同樣，第二保護層336亦可填入於金屬層412的另一 側的開孔416中，以保護埋入式電容及其電極的特性。 、同樣，請參考圖4，本發明之封裝基板400更可藉由 機械鑽孔的方式先形成—通孔，再以化學電鍍的方式形成 -導體於通孔的内壁上，⑽成導通金屬層化與線路層 442的導通孔450。當然，導通孔45〇内可依昭封 _的厚度填入絕緣性或導電性的填孔材料价在二; 洋述同樣，在完成埋入式電容430的組裝製程之後，封 裝基板400更可依據電路的需求，利用增層法或其他製程 依序製作多層的内連線結構（未繪示），而最外層的^面 線路層如圖1所示，以防銲層覆蓋，且防銲層具有至少一 12 200822302 2〇803twf.doc/t =，用巧露表面線路層之接點，贿 通上、下元件之媒介。 接著，圖5綠示本發明第四實施例之具有埋 =反 至少一介電層520、至少一埋入式電容530 =-線路層54〇。其中，線路芯板51〇例如是以玻 A/_gassflber)和環氧樹脂（epoxyresin)為絕緣材料 八鋼4基板以増加封I基板5⑻的強度及支撐性。此外， 2電層52G亦可為固化態或半固化態的環氧樹脂或聚酿亞 月女，以增層的方式覆蓋於線路芯板51〇上。在本實施例中， 線，芯板510的二相對表面分別具有—金屬層512，且線 路芯板510具有至少一導通孔Μ4，其與金屬層512相導 通’而埋入式電容53〇可埋入於線路芯板別中，並盥 屬層512相連接。 “ 在本實施例中，介電層520可為單層或多層，而線路 層540可為單層或多層。以多層為例，介電層52〇中具有 多個以雷射鑽孔並填入導電材料的導電孔522，以電性連 接上、下相鄰的線路層540。當然，線路層540亦可藉由 導電孔524連接至金屬層512，或封裝基板5〇〇藉由^少 一貫通孔550貫穿線路芯板51〇、介電層52〇以及線路層 540，以使金屬層512與線路層54〇相導通。 曰 承上所示，本實施例之埋入式電容530可為高介電常 數的環氧樹脂•陶瓷複合電容或其他高分子及陶瓷複合電 容，以增加封裝基板的性能。此外，在壓合基板之前:圖 13 200822302 20803twf.doc/t 3而更可覆蓋於圖5之埋入式電㈣^ ^ 而弟-倾層338亦可選擇性填入於金屬層5i2的另一側 的開以保護埋入式電容530及其電極的特性。 同樣，在完成埋入式電容53〇的組裳製程之後， 基板500更可依據電_ f求，增層法或依 序製作多層咖連錢構（树示），㈣外相表Tampering, epoxy resin _ shouting composite capacitors or other ceramics: sub-complex δ electric valleys will increase the capacitance and reduce the dielectric loss, thereby improving the performance of the package substrate 200. In this embodiment, after the assembly process of the buried capacitor is completed, the package substrate 2GG can sequentially fabricate the multiple 2 interconnect structures 25G' by the build-up method according to the requirements of the circuit to make the original four-layer line. The substrate can be increased to eight or eight layers of ten or twelve layers. Wherein, the "electric layer 254 between adjacent two circuit layers can form a plurality of recessed holes by laser drilling and fill the conductive material so that the two second circuit layers 252 are electrically connected to each other. Finally, the most of the package substrate 200 The outer surface wiring layer 256 is further covered by a solder resist layer 260, and the solder resist layer 26 has at least one opening plus ^, ^ surface wiring layer 256. In this embodiment, the upper contact 2 2 The twins are connected to at least one chip or passive component (not shown), and the lower contact 258b is used to electrically connect a printed circuit board (not shown) so that the sealing substrate 2 is used as the upper and lower components. 3 is a schematic diagram of a package substrate having a buried capacitor according to a second embodiment of the present invention. The package substrate 300 mainly includes a core board 310 and at least one buried capacitor 330. a first protective layer 338 and a 10 200822302 20803 twf.doc/t metal layer 340. The core board 3 is, for example, a substrate made of a glass fiber and an epoxy resin. In order to increase the strength and supportability of the package I substrate 300. The input capacitor mo can be buried in the core board 310 and connected to the metal layer 340. In this embodiment, the buried capacitor 330 can be a high dielectric constant epoxy-ceramic composite capacitor or other ceramic/ The polymer composite capacitor is formed on the metal layer 340 after being sintered at a high temperature, and then covers an electrode material on the dielectric material 332 to form an "electrode 334 connecting metal layer 340. It is worth noting that in order to avoid damage or damage to the buried capacitor 330 during the pressing process, the first protective layer 338 may be overlaid on the buried capacitor 330 before the substrate is pressed. The first protective layer 338 is, for example, a polymer material such as epoxy tree or polythene, which has better compressive strength, and can prevent the etching process, the plating process and the surface treatment reaction before the pressing. The agent affects the characteristics of the buried capacitor 330 and its electrodes. In addition, in the opening 342 of the other side of the metal layer 340, a second protective layer 336 may be selectively filled to cover a surface of the buried capacitor 330, and the material and the effect are the same. The protective layer 338 also prevents the buried capacitor 330 from being damaged. 4 is a partial schematic view showing a package substrate having a buried capacitor according to a third embodiment of the present invention. The package substrate 4A mainly includes a first circuit core plate 410, a dielectric layer 420, at least one buried capacitor 43A, and a first, a core plate 440. Wherein, the first and second circuit core plates 41〇, 44 are 铜 疋 疋 疋 glass glass glass glass glass glass glass glass glass glass glass glass glass glass glass glass glass glass glass glass glass glass glass glass glass glass glass glass glass glass 以 以 以 以 以 以 以 以 以 增加Strength and support 200822302 20803twf.doc/t; the electric layer 420 may also be a cured or semi-cured glass fiber ring emulsion laminated on the first and second circuit core plates 41G, 44G between. In the example of the first embodiment, the opposite surfaces of the first circuit core plate 41 have a metal layer 412, and the first line anger plate 410 has at least a first via hole = two, which is electrically connected to the metal layer 412. The buried capacitor 43A can be buried in the first line core plate 41G and connected to the metal layer 412. Similarly, the opposite surfaces of the second circuit core board _ have a circuit layer 442, respectively, and the dam plate _ has at least one second via hole 444 which is electrically connected to the wiring layer 442. As shown in the above, the buried capacitor 430 of the present embodiment can be a high dielectric constant epoxy-ceramic composite capacitor or other ceramic/polymer composite capacitor to increase the performance of the package substrate 400. In addition, the first protective layer 338 of FIG. 3 can be overlaid on the buried capacitor 43A of FIG. 4 before the substrate is pressed. Similarly, the second protective layer 336 may also be filled in the opening 416 on the other side of the metal layer 412 to protect the characteristics of the buried capacitor and its electrodes. Similarly, referring to FIG. 4, the package substrate 400 of the present invention can be formed by mechanical drilling first, and then formed by electroless plating, and the conductor is formed on the inner wall of the through hole, and (10) is turned into a metal layer. The via 450 of the wiring layer 442 is formed. Of course, the thickness of the insulating or conductive hole-filling material can be filled in the via hole 45 依 in the thickness of the sealing hole ;. In the same manner, after the assembly process of the buried capacitor 430 is completed, the package substrate 400 can be further According to the requirements of the circuit, the multi-layered interconnect structure (not shown) is sequentially formed by the build-up method or other processes, and the outermost layer of the circuit layer is as shown in FIG. 1 , covered with a solder mask, and solder-proof. The layer has at least one 12 200822302 2〇803twf.doc/t =, and uses the contact of the surface layer of the surface to bribe the medium of the upper and lower components. Next, FIG. 5 shows a fourth embodiment of the present invention having a buried/reverse at least one dielectric layer 520 and at least one buried capacitor 530=-circuit layer 54A. Among them, the line core plate 51 is made of, for example, glass A/_gassflber) and epoxy resin (epoxyresin) as the insulating material. The strength and supportability of the I substrate 5 (8) are sealed by the eight steel plates. In addition, the 2 electrical layer 52G may also be a cured or semi-cured epoxy resin or a polystyrene, covering the circuit core board 51〇 in a layered manner. In this embodiment, the two opposite surfaces of the core and the core plate 510 respectively have a metal layer 512, and the circuit core plate 510 has at least one via hole 4, which is electrically connected to the metal layer 512, and the buried capacitor 53 can be used. Buried in the circuit core board, and the samarium layer 512 is connected. In this embodiment, the dielectric layer 520 may be a single layer or a plurality of layers, and the circuit layer 540 may be a single layer or a plurality of layers. In the case of multiple layers, the dielectric layer 52 has a plurality of laser holes and fills therein. The conductive holes 522 of the conductive material are electrically connected to the upper and lower adjacent circuit layers 540. Of course, the circuit layer 540 may also be connected to the metal layer 512 through the conductive holes 524, or the package substrate 5 A through hole 550 penetrates the circuit core plate 51, the dielectric layer 52, and the circuit layer 540, so that the metal layer 512 is electrically connected to the circuit layer 54. As shown in the bearing, the buried capacitor 530 of the embodiment can be It is a high dielectric constant epoxy resin/ceramic composite capacitor or other polymer and ceramic composite capacitor to increase the performance of the package substrate. In addition, it can be covered before pressing the substrate: Figure 13 200822302 20803twf.doc/t 3 The embedded electric (four) ^ ^ in Fig. 5 can also be selectively filled in the other side of the metal layer 5i2 to protect the characteristics of the buried capacitor 530 and its electrodes. After the embedded capacitor 53 〇 is formed, the substrate 500 can be added according to the electric _ f Glechoma coffee or making a multilayer structure (tree shown), (iv) external phase sequence table by
:層:二防銲層覆蓋，且防銲層具有至二開 I、= :層之接點，以使基板作為導通 j著，圖6繪示以圖3之具有埋入式電 裝J⑽部示意圖。當完成埋入式電容33= ，且广衣壬之後’封叙基板600更可依據電路的需求，以拗 廣法或其他製程依序製作多層的喊線結構_ = 線結構602包括至少一介電声61〇以；, ^ 7丨冤層61ϋ以及至少一線路屑 62 =夕層為例，介電層610包括多個第一介電層 以及第二介電層614，第一介電層612覆蓋於第—金屬居 34〇上，而第二介電層614可覆蓋於芯板31〇上或第二二 屬層344上。此外，線路層62〇包括多個第一線路層 62^以及第二線路層626，第一線路層622、624可藉由第 電，612中的導電孔616相互導通，而第二線路層 玎藉由第二介電層6丨4中的導電孔618與第二金屬層344 相互導通。再者，第一線路層622、624與第二線路層626 之間可藉由至少一導通孔028相互導通。 综上所述，在第一實施例中，本發明中之埋入式電容 14 200822302 20803twf.doc/t 因基板結構的改良，因此可配置於適當的位置上，不需避 開導通孔的位置，故可增加其配置空間及自由度。此外， 本發明之封裝基板可採用高介電係數以及低介電損失的高 分子陶瓷複合材料來取代傳統的獨立式電容，進而提高封 裝基板的性能。再者，本發明中之埋入式電容以至少一保 濃層覆蓋’因而在基板壓合過程中，可避免破壞或損傷， 進而提高其可靠度。 雖然本發明已以較佳實施例揭露如上，然其並非用以: Layer: The second solder mask is covered, and the solder resist layer has a contact to the second I, =: layer so that the substrate is turned on, and FIG. 6 shows the embedded electric device J (10) in FIG. schematic diagram. When the buried capacitor 33= is completed, and after the 广 壬 ' ' 封 封 封 封 封 封 封 封 封 封 封 封 基板 基板 基板 基板 基板 基板 基板 基板 基板 基板 基板 基板 基板 基板 基板 基板 基板 基板 基板 基板 基板 基板 基板 基板 基板 基板 或 线 线For example, the electroacoustic 61 〇 , , the 7 丨冤 layer 61 ϋ and the at least one line chip 62 夕 layer, the dielectric layer 610 includes a plurality of first dielectric layers and a second dielectric layer 614, the first dielectric layer 612 covers the first metal layer 34, and the second dielectric layer 614 may cover the core plate 31 or the second two layer 344. In addition, the circuit layer 62 includes a plurality of first circuit layers 62 and a second circuit layer 626. The first circuit layers 622 and 624 can be electrically connected to each other through the conductive holes 616 in the first electrode 612, and the second circuit layer The conductive holes 618 in the second dielectric layer 6丨4 and the second metal layer 344 are electrically connected to each other. Furthermore, the first circuit layers 622, 624 and the second circuit layer 626 can be electrically connected to each other by at least one via hole 028. In summary, in the first embodiment, the buried capacitor 14 200822302 20803twf.doc/t of the present invention can be disposed at an appropriate position due to the improvement of the substrate structure, without avoiding the position of the via hole. Therefore, it can increase its configuration space and freedom. In addition, the package substrate of the present invention can replace the conventional free-standing capacitor with a high dielectric constant and low dielectric loss high molecular ceramic composite material, thereby improving the performance of the package substrate. Furthermore, the buried capacitor of the present invention is covered with at least one of the protective layers. Thus, damage or damage can be avoided during the substrate press-fitting process, thereby improving reliability. Although the present invention has been disclosed above in the preferred embodiment, it is not intended to be used
Ο 限定本發明，任何所屬技術領域中具有通常知識者，在不脫 離本發明之精神和範圍内，當可作些許之更動與潤飾，因 此本發明之保護範圍當視後附之申請專利範圍所界定者 〇 、 圖式簡單說明】 圖 圖1繪示習知一種内埋獨立式電容的封裝基板的示意 圖2繪示本發明第一實施例之具有埋入式電容的 基板的局部示意圖。 、</ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> <RTIgt; BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic view showing a conventional package substrate with a buried capacitor. FIG. 2 is a partial schematic view showing a substrate having a buried capacitor according to a first embodiment of the present invention. ,
圖3繪示本發明第二實施例之具有埋入 基板的局部示意圖。 “的封I 圖4繪示本發明第三實施例之具有埋入 基板的局部4圖。 “的封裝 圖5繪示本發明第四實施例之具有埋 基板的局部示意圖。 '電各的封襄 圖6綠示以圖3之具有埋入式電容之基板為核心層的 15 200822302 20803twf.doc/t 封裝基板的局部示意圖。 【主要元件符號說明】 100 :封裝基板 110 :芯板 121〜124 :介電材料 130 :獨立式電容 142、144 :銅箔 150 :導通孔 160 :核心疊層板 162 :表面線路 164 :導電孔 200 :封裝基板 210 :線路芯板 212 :第一線路層 214 :第二線路層 216 :導通孔 220 :介電層 222 :第一介電層 224 :第二介電層 226、228 :導電孔 230 :埋入式電容 240 :金屬層 242 ··第一金屬層 244 ··第二金屬層 16 200822302 20803twf.doc/t 250 内連線結構 252 線路層 254 介電層 256 表面線路層 258a、258b :接點 260 :防銲層 262 :開口 300 :封裝基板 310 :芯板 330 :埋入式電容 332 :介電材料 334 :電極 336 :第二保護層 338 :第一保護層 340 :金屬層 342 :開孔 400 :封裝基板 410 ··第^ 一線路怒板 412 :金屬層 414 :第一導通孔 416 :開孔 420 :介電層 430 ·•埋入式電容 440 :第二線路芯板 17 200822302 20803twf.doc/t 442 :線路層 444 :第二導通孔 450 :導通孔 500 :封裝基板 510 :線路芯板 512 :金屬層 514 :導通孔 516 :開孔 520 :介電層 522、524 :導電孔 530 :埋入式電容 540 ··線路層 550 :貫通孔 600 :封裝基板 602 :内連線結構 610 :介電層 612 :第一介電層 614 :第二介電層 616、618 ·導電孔 620 :線路層 622、624 :第一線路層 626 ··第二線路層 628 :導通孔 18Fig. 3 is a partial schematic view showing a buried substrate in accordance with a second embodiment of the present invention. Fig. 4 is a partial view of a fourth embodiment of the present invention having a buried substrate. Fig. 5 is a partial schematic view showing a buried substrate according to a fourth embodiment of the present invention. 'Electrical seals Fig. 6 shows a partial schematic view of the package substrate with the substrate of the buried capacitor of Fig. 3 as the core layer 15 200822302 20803 twf.doc/t. [Main component symbol description] 100: package substrate 110: core plates 121 to 124: dielectric material 130: free-standing capacitors 142, 144: copper foil 150: via hole 160: core laminate 162: surface wiring 164: conductive hole 200: package substrate 210: line core plate 212: first circuit layer 214: second circuit layer 216: via hole 220: dielectric layer 222: first dielectric layer 224: second dielectric layer 226, 228: conductive hole 230: buried capacitor 240: metal layer 242 · first metal layer 244 · second metal layer 16 200822302 20803twf.doc / t 250 interconnect structure 252 wiring layer 254 dielectric layer 256 surface wiring layer 258a, 258b : Contact 260 : solder resist layer 262 : opening 300 : package substrate 310 : core plate 330 : buried capacitor 332 : dielectric material 334 : electrode 336 : second protective layer 338 : first protective layer 340 : metal layer 342 : Opening 400 : Package substrate 410 · · 1st line anger plate 412 : Metal layer 414 : First via hole 416 : Opening hole 420 : Dielectric layer 430 · Buried capacitor 440 : Second line core board 17 200822302 20803twf.doc/t 442: circuit layer 444: second via 450: via 500: package base 510: Line core board 512: Metal layer 514: Via hole 516: Opening hole 520: Dielectric layer 522, 524: Conductive hole 530: Buried capacitor 540 · Line layer 550: Through hole 600: Package substrate 602: Inside Wiring structure 610: dielectric layer 612: first dielectric layer 614: second dielectric layer 616, 618 · conductive hole 620: circuit layer 622, 624: first circuit layer 626 · second circuit layer 628: conduction Hole 18