200847183 卵 ii_2TW 23601twf.doc/p 九、發明說明： 【發明所屬之技術領域】 ^發明是有_-__控财法，且特別是有關 於一種記憶體插槽時脈的控制方法。 【先前技術】 近年來’電子產品的使用率越來越高，導致電子產品 之間的電磁干擾影變 2。其中’個人電腦的制日異普遍，無論U作上i 而1 ’或疋生活上㈣樂，個人電腦已經進駐人類日常生 活:H般環境中最常產生電磁干擾之設備之一。為 了提南運算雜，個人電腦之時脈喊（dGek)的 t越高’其㈣顯成為高_數位訊號在元件間進行 傳輸，導致電磁干擾日益嚴重。 一般而言，個人電腦上之時脈產生 至所有記㈣減。“，當雜魏_法正虎 ===，=記憶體插槽，記憶體模組同樣無法 產生任何㈣’僅是徒增電軒擾而已。而記 法運作之常見範例如下所述： '、、、'”、、 乾例卜記憶體模組未插入記憶體插槽。範 憶體插槽上雖已插人記㈣餘，但是模二 ，存在檢測（Se㈣職職De⑽SPD)二二 ，（checksum)不正確’則表示此記憶體模組有二二 耗例3，記憶體模組插人方法錯誤。範例4，記憶體' 已插入記憶體模組且其序列存在檢測資料之錯^檢查^亦 200847183 . * itjuu/UU62TW 23601twf.doc/p 正確’但若序列存在檢測資料中之某一參數不被記憶體控 制器（Memory Control Hub, MCH)所支援，表示記憶體模 組之規格與晶片組不符合。範例5,記憶體模組測試失敗， 即存取資料時失敗。 知上所述，g 體极組沒有在運作時，持續提供其 時脈訊號是無意義的，只會增加電磁干擾，連帶影響到電 腦其他it件的運作。因此，如何能夠自_測記憶麵組 • 的運作狀態，而適時關閉時脈訊號，即是本發明所欲解決 的主要課題。 ^ 【發明内容】 本叙明^供一種§己憶體插槽時脈的控制方法，能夠根 據記憶體模組的運作狀態，自動將提供給讀取發生錯誤之 記憶體插槽的時脈訊號關閉。 本發明提出一種記憶體插槽時脈的控制方法，適用於 控制提供給多個記憶體插槽之時脈訊號，其中這些記憶體 插槽係用以插入兄憶體模組。此方法首先提供時脈訊號給 f有織雜槽。接著，讀取贿在記顧模組上之規格 貧^，亚判斷規格資料的讀取是否發生錯誤，當讀取發生 錯决4 ’關閉提供給讀取發生錯誤之記憶體插槽的時脈訊 號。 在本發明之一實施例中，更包括當讀取沒有發生錯誤 2 ’判斷規格資料之錯誤檢查碼（checksum)是否正確。 當錯誤檢查碼不正確時，關閉提供給讀取發生錯誤之記憶 體插槽的日守脈訊號。另一方面，當錯誤檢查碼正確時，檢 200847183 iri/u/uuo2TW 23601twf.doc/p 查記憶體模組上之規格資料是否均被讀取，若仍有規格資 料未讀取，則繼續讀取其他記憶體模組上之規格資料，並 重複上述步驟，直到所有記憶體模組上之規格資料均讀取 完畢為止。 ' 在本發明之-實施例中，上述之讀取儲存在記憶麵 組上之規格資料的步驟包括讀取記憶體插槽之配置資料， 而配置資料記錄記憶體插槽之硬體位址。並且，依照硬體 位址讀取儲存在記憶體模組上之規格資料。 版 ^在本發明之一實施例中，上述之關閉提供給讀取發生 錯误之記憶體插槽的時脈訊號的步驟包括將配置資料中對 應於讀取發生錯誤之記憶體插槽之開_位設定為關閉。 亚且，根據配置資料，關閉提供給讀取發生錯誤之記悚體 插槽的時脈訊號。 〜 在本發明之—實施射，上述之將配置資料中對應於 1發生錯誤之記賊鋪之開_位設定為㈣的步驟 更包純行記㈣模組之初始化程式，而在初始化 =執行的過程中，設定配置資料。接下來，在初始化程 =仃完畢後，才根據配置資料，_提供给讀取發生錯 误之記憶體插槽的時脈訊號。 在本發明之—實補巾，上述之關提供給讀取發生 記憶體插槽的時脈訊號的步驟包括直接控制時脈產 r t genemG〇關閉時脈訊號。或者，透過晶片组 (chipset)關閉時脈訊號。 、、 在本發明之—實施例中，上述之關閉提供給讀取發生 7 200847183 U^UU7UU»2TW 23601twf.doc/p 錯誤之記憶體插槽的時脈訊號的步驟包括藉由週邊組件互 連（Peripheral Component Interconnect，PCI )組態 (configuration )、内積體電路（Inter Integrated Circuit， I2C )、輸入輪出埠（inpUt Output port，10 port)以及記憶 體映射輸入輪出（Memory Mapped Input Output，ΜΜΙΟ ) 其中之一的關閉方式關閉時脈訊號。其中，關閉方式記錄 於配置資料之關閉方式攔位中。200847183 Egg ii_2TW 23601twf.doc/p Nine, invention description: [Technical field of invention] The invention has a _-__ money control method, and in particular, a control method for a memory slot clock. [Prior Art] In recent years, the use rate of electronic products has become higher and higher, resulting in electromagnetic interference between electronic products. Among them, the personal computer system is universal, whether it is i or 1 or 疋 life (4) music, personal computers have been stationed in human daily life: one of the most common electromagnetic interference devices in the H-like environment. In order to carry out the operation of the South, the clock of the personal computer (dGek) is higher, and its (four) becomes a high-digit signal transmitted between components, resulting in an increasingly serious electromagnetic interference. In general, the clock on a personal computer is generated to all (four) minus. "When Wei Wei_Fa Zhenghu ===, = memory slot, the memory module can't produce any (4)' is just an increase in power. The common examples of the operation of the notation are as follows: ', , , ', , , dry memory module is not inserted into the memory slot. Although the memory of the Fan Yi body slot has been inserted (4), but the second model, there is detection (Se (four) job De (10) SPD) 22, (checksum) is incorrect 'is that the memory module has two or two consumption examples 3, memory The method of inserting the body module is wrong. Example 4, the memory 'has been inserted into the memory module and its sequence has the error of the detection data ^Check ^ also 200847183 . * itjuu/UU62TW 23601twf.doc/p correct 'but if the sequence exists in the detection data one of the parameters is not Supported by the Memory Controller Hub (MCH), the specifications of the memory module do not match the chipset. Example 5, the memory module test failed, that is, the access to the data failed. As mentioned above, when the g body group is not in operation, it is meaningless to continuously provide its clock signal, which only increases electromagnetic interference, which affects the operation of other parts of the computer. Therefore, how to control the operation state of the memory quilt and to turn off the clock signal in time is the main problem to be solved by the present invention. ^ [Description of the Invention] This description provides a control method for the clock slot of the suffix, which can automatically provide the clock signal to the memory slot in which the error is read according to the operating state of the memory module. shut down. The invention provides a method for controlling the clock slot of a memory slot, which is suitable for controlling a clock signal provided to a plurality of memory slots, wherein the memory slots are used for inserting a brother memory module. This method first provides a clock signal to f with a weaving groove. Then, read the bribe on the record module, the specification is poor, the sub-judgment specification data is read incorrectly, and when the read occurs, the error occurs. 4' Close the clock provided to the memory slot where the error occurred. Signal. In an embodiment of the present invention, it is further included whether the error check code (checksum) of the specification data is not correct when the error 2 ′ is not read. When the error check code is incorrect, turn off the daily pulse signal supplied to the memory slot where the error occurred. On the other hand, when the error check code is correct, check 200847183 iri/u/uuo2TW 23601twf.doc/p to check whether the specification data on the memory module is read. If the specification data is still not read, continue reading. Take the specification data on other memory modules and repeat the above steps until the specifications on all memory modules are read. In the embodiment of the present invention, the step of reading the specification data stored on the memory ferrule includes reading the configuration data of the memory slot and configuring the hardware address of the data recording memory slot. And, the specification data stored on the memory module is read according to the hardware address. In one embodiment of the present invention, the step of turning off the clock signal provided to the memory slot in which the error has occurred is to include opening the memory slot corresponding to the read error in the configuration data. The _ bit is set to off. In addition, according to the configuration data, the clock signal provided to the slot in which the error is read is turned off. ~ In the present invention - the implementation of the above, the configuration data corresponding to 1 error occurred in the opening of the thief shop _ bit is set to (four) step more pure line (four) module initialization program, and in the initialization = execution During the process, set the configuration data. Next, after the initialization process = 仃 is completed, according to the configuration data, _ is provided to the clock signal of the memory slot in which the error has been read. In the present invention, the step of providing the clock signal for reading the memory slot is as follows: directly controlling the clock generation r t genemG 〇 turning off the clock signal. Alternatively, the clock signal is turned off by the chipset. In the embodiment of the present invention, the step of closing the clock signal provided to the memory slot in which the error occurs is included by interconnecting peripheral components. (Peripheral Component Interconnect, PCI) configuration, Inter Integrated Circuit (I2C), inpUt Output port (10 port), and Memory Mapped Input Output (ΜΜΙΟ) ) One of the shutdown modes turns off the clock signal. The shutdown mode is recorded in the shutdown mode of the configuration data.
在本發明之一實施例中，上述之關閉提供給讀取發生 錯誤之記憶體插槽的時脈訊號的步驟包括藉由設定關閉方 式所對應之暫存裔為關閉，以關閉提供給讀取發生錯誤之 記憶體插槽的時脈訊號。其中，關閉方式所對應之暫存器 的位址記錄於配置資料之暫存器位址欄位中。 在本發明之一實施例中，上述之規格資料儲存於記憶 體模組上之電子可抹除可程式化唯讀記憶體（Electricaii^In an embodiment of the present invention, the step of closing the clock signal provided to the memory slot in which the error has occurred is included by turning off the temporary storage corresponding to the shutdown mode to turn off the supply to the read The clock signal of the memory slot in which the error occurred. The address of the temporary register corresponding to the shutdown mode is recorded in the register address field of the configuration data. In an embodiment of the invention, the above-mentioned specification data is stored in the memory module and the electronic erasable programmable read-only memory (Electricaii^
Erasable Programmable Read Only，EEPR0M)。而規格資 料為序列存在檢測（SerialpresenceDetect，SpD)資料。、 〜士本發明在判斷讀取記憶體模組上之規格資料發生錯 =時，便即時將提供給對應之記憶體插槽的時脈訊號關 二因此可減少產生非必要之時脈訊號，進—步降低電磁 十擾（Electr〇magnetic Interference EMI)。 為讓本發明之上述特徵和優點能更明顯易懂 t較佳實_，並配合所關式，作詳細制如下。 【實施方式】 會提供時脈 般而σ日"^脈產生器（clock generator ) 8 200847183 iifuu /UU52TW 23601twf.doc/p 訊號（clock)至所有記憶體插槽（sl〇〇。然而，在記情 體模組插人記㈣插槽發生錯誤而無法正常運作時，提^ 時脈訊號至記憶脑槽並無㈣，此時即可將時脈訊號關 ^，避免產生科要的電磁僧。本發卿是根據上述概 心所發展出來的-套記賴減時脈喻财法，能夠自 動將提供、，、“M取|生錯誤之記憶體插槽的時脈訊號關閉。 為了使本發明之内容更為日膽’町縣實關作為本發 明確實能夠據以實施的範例。 圖1疋依照本發明一實施例所繪示之記憶體插槽時脈 的控制方法流賴。請參關！，本方法_於控制提供 給多個記憶體插槽之時脈訊號，其中記憶體插槽係用以插 入體杈組。而記憶體模組例如是雙直列記憶體模組 (dual in-line memory module，DIMM)。 首先，步驟S101為執行開機自我測試（p〇wer 〇n Self Test，POST)。當電腦主機的啟動鍵被按下時，電腦内的 基本輸入輸出系統（Basic Input Output System，BIOS)將 會對電腦内的硬體設備進行完整的檢驗和測試。 队接著，在步驟S102中，由時脈產生器提供時脈訊號 給各個記憶體插槽，此時脈訊號例如是提供給記憶體模組 進行訊號同步之用。詳細地說，記憶體模組的存取動作， 必須與系統的時脈訊號同步，以確保資料進行存取的正確 性。 以下舉例說明記憶體插槽時脈的控制路徑。圖2是依 照本發明一實施例所繪示之記憶體插槽時脈的控制系統方 9 200847183 jli ljm / uv/〇2TW 23601twf.doc/p 塊圖。請參照圖2，此系統包括時脈產生器2〇1以及記憶 體插槽202〜209。本實施例是由時脈產生器2〇1直接控制 記憶體插槽202〜209之時脈訊號的開關，每當李 時，時脈產生器2〇1便會提供時脈訊 202〜209 。 另外，亦可透過晶片組（未繪示），一般為北橋晶片， 將記憶體插槽202〜209之時脈訊號的開關。換言^ 7時脈 φ 產生态將時脈訊號傳送至晶片組，再藉由控制晶片組 將時脈訊號傳送記憶體插槽202〜209。 請繼續參照圖1，步驟S103係讀取儲存在記憶體模組 上之規格資料。在步驟S103中，BIOS將直接去讀取記憶 體模組上之規格資料，以取得記憶體模組的相關資料。因 此，糸統便可根據規格資料，充份運用記憶體模組。 其中’規格資料例如是燒錄在記憶體模組上之電子可 抹除可程式化唯讀記憶體（Electrically ErasabieErasable Programmable Read Only, EEPR0M). The specification data is Serial Presence Detect (SpD) data. When the invention determines that the specification data on the read memory module is wrong=, the clock signal provided to the corresponding memory slot is immediately turned off, thereby reducing the generation of unnecessary clock signals. Step-by-step reduction of Electromagnetic Interference (EMI). In order to make the above features and advantages of the present invention more apparent and easy to understand, and in conjunction with the closed type, the detailed system is as follows. [Embodiment] A clock-like and clock generator 8 200847183 iifuu /UU52TW 23601twf.doc/p clock is provided to all memory slots (sl〇〇. However, in If the slot is wrong and cannot be operated normally, there is no (4) when the clock signal is sent to the memory brain slot. At this time, the clock signal can be turned off to avoid the electromagnetic 僧. According to the above-mentioned generalization, Benfa Qing is able to automatically turn off the clock signal of the memory slot that provides, and the "M" error. The content of the present invention is more exemplified by the fact that the present invention can be implemented according to the present invention. Fig. 1 is a diagram showing the control method of the memory slot clock according to an embodiment of the present invention. In this method, the method is to control the clock signal provided to the plurality of memory slots, wherein the memory slot is used to insert the body array, and the memory module is, for example, a dual in-line memory module (dual In-line memory module, DIMM). First, step S101 is performed. Machine self-test (p〇wer 〇n Self Test, POST). When the start button of the computer is pressed, the basic input and output system (BIOS) in the computer will be the hardware device in the computer. Perform a complete test and test. The team then, in step S102, the clock generator provides a clock signal to each memory slot, and the pulse signal is, for example, provided to the memory module for signal synchronization. In other words, the access operation of the memory module must be synchronized with the clock signal of the system to ensure the correct access of the data. The following describes the control path of the memory slot clock. Figure 2 is in accordance with the present invention. The control system of the memory slot clock shown in an embodiment is 9 200847183 jli ljm / uv/〇2TW 23601twf.doc/p block diagram. Referring to FIG. 2, the system includes a clock generator 2〇1 and The memory slots 202 to 209. In this embodiment, the clock generator 2〇1 directly controls the clock signals of the memory slots 202 to 209. Whenever Li, the clock generator 2〇1 will Provide time pulse 202~209. In addition, a chip set (not shown), generally a north bridge chip, switches the clock signals of the memory slots 202 to 209. In other words, the clock pulse φ generation state transmits the clock signal to the chip set. Then, the clock signal is transmitted to the memory slots 202 to 209 by controlling the chipset. Referring to FIG. 1, step S103 reads the specification data stored in the memory module. In step S103, the BIOS will go directly. Read the specification data on the memory module to obtain the relevant data of the memory module. Therefore, SiS can fully utilize the memory module according to the specifications. The specification data is, for example, an electronic erasable programmable read-only memory (Electrically Erasabie) programmed on a memory module.
Programmable Read Only，EEPROM)中的序列存在檢測 鲁 （SeriM Presence Detect，SPD)資料’係用來記錄記憶體模 組之種類、容量、速度、所需電壓等資訊。 一般電腦在啟動之後，BIOS便會直接去讀取spj)資 料。接著，晶片組（一般為北橋晶片）便可根據spD資料 • 來配置相對應之記憶體模組的工作時序（timing)與暫存 器，以使記憶體模組能夠正常運作。 然後，在步驟S104中，當讀取發生錯誤時，則將提 供給讀取發生錯誤之記憶體插槽的時脈訊號關閉。也就是 2〇〇847』^2TW 薦耐doc/p 說，當無法讀取到儲存在記憶體模組上之規格資料時，代 表記憶體模組與記憶體插槽間的連結或是記憶體模組與系 統間的相容性發生問題，此時便可將提供至其對應之記情 體插槽的時脈訊號關閉。 〜 值得一提的是，上述關閉時脈訊號的方式例如可直接 控制時脈產生器，藉由週邊組件互連（peripherai Component Interconnect，PCI)組態（conflgurati〇n)之關 馨閉方式來關閉時脈訊號；或者，可透過晶片組發送一個内 積體電路（Inter Integrated Circuit，I2C )指令，而關閉時脈 訊號。 以下再舉一實施例以更詳細地說明記憶體插槽時脈 的控制方法各步驟。圖3是依照本發明另一實施例所繪示 之記憶體插槽時脈的控制方法流程圖。請參照圖3，步驟 S301與步驟S3〇2與上述實施例之步驟sl〇i與步驟 相，，均是藉由BIOS執行開機自我測試，然後由時脈產 生為提供時脈訊號至各個記憶體插槽。 瞻在BIOS正常執行且記憶體插槽正常運作的狀況下， 乂驟^3〇3為執行記憶體模、組之初始化程式。初始化程式 例如是依據晶片組的技術文件規格，進行暫存器填值、改 位兀的動作，使得記憶體模組得以正常運作。 著，在步驟S304中，系統便會讀取記憶體插槽之 貝料，以取得記憶體插槽之硬體位址，此配置資料例 ^儲存於mos中，其中記錄了各個記憶體插槽之硬體 止。砰細地說，硬體工程師在設計主機板時，便會依各 11 200847183 jll i^v/uv〇2TW 23601twf.doc/p 個記憶體插槽在主機板上的位置及屬性給予一個硬體位址 (例如是I2C位址），並將此硬體位址記錄於配置資料中。 由上述可知，步驟S304的動作其實就是要讓系統知道目 前要讀取哪一個記憶體插槽上之記憶體模組。 然後，步驟S305為依照硬體位址讀取儲存在記憶體 模組上之規格資料，並判斷規格資料的讀取是否發生錯 誤。舉例來說，假設記憶體插槽的硬體位址為A〇，此硬體 • 位址A()則記錄在配置資料中。若有記憶體模組插入此記 憶體插槽，BIOS便可根據此硬體位址A〇，透過系統管理 匯流排（System Management Bus，SMBus)找到此記憶體 插槽，並與安插其上之記憶體模組溝通而讀取規格資料。 詳細地說，晶片組可透過系統管理匯流排或是〗2C匯 流排傳輸時脈訊號、資料以及指令（instructi〇n)等。圖4 疋依照本發明一實施例所繪示之記憶體模組之資料傳輸系 統的方塊圖。請參照圖4，此系統包括處理單元4〇1、晶片 鲁 組402及記憶體模組404。其中，晶片組402例如是北橋 曰曰片或南橋晶片，其中則包括主控器（master contr〇iier) 403 ;記憶體模組404中包括受控器（siave controller) 4〇5 及電子可抹除可程式化唯讀記憶體（EEPR0M) 406。 處理單元401是用以傳送指令通知晶片組402去讀取 規格資料。主控器403係藉由系統管理匯流排407與受控 裔405進行溝通。所有的指令均由主控器4〇3發出，而由 X控器405來接收並回覆資料給主控器4034EPROM406 是用來存放規格資料。 12 200847183 uruv /uu^2TW 23601twf.doc/p 晶片組402根據處理單元4〇i所傳送之指令，透過系 統管理匯流排407以自記憶體模組4〇4之EEPROM 406中 璜取規格資料。此時，藉由系統管理匯流排407，主控器 403將去偵測受控器405的回應訊息。當主控器4〇3無法 積測到受控器405之回應訊息時，表示記憶體模組4〇4可 月匕’又有插入纪憶體插槽。因此，受控器便不會發送回 應訊息。 請繼續簽照圖3，在步驟S305中，當無法讀取到規格 資料，便判斷讀取發生錯誤。此時，執行步驟S3〇6，設定 配置貧料中對應於讀取發生錯誤之記憶體插槽之開關欄位 為關閉，以根據開關攔位將提供至對應之記憶體插槽的時 脈訊號關。舉例來說，定義關攔位為丨表示開啟；反 之，開關攔位為〇表示關閉。這也就是說，在步驟S3〇2 中，當把時脈訊號提供給各個記憶體插槽時，配置資料中 的開關攔位均被設定為1;而在步驟幻〇6中，配置資料中 對應於讀取發生錯誤之記憶體鋪之關攔位將被設定為 0 〇 在步驟S305中，當讀取沒有發生錯誤時，執行步驟 =07^判斷規格資料之錯誤檢查碼（checksum)是否正確。 右=誤檢查碼不正確，執行步驟S3〇6，將配置資料中對應 發生錯疾之記憶體插槽之開關攔位設定為關閉。也 就^兄’舰格資料做錯誤檢查碼的檢查，檢查錯誤檢查 碼疋否與預設相符。舉例來說，假設SPD[o] +[〗]+… SPD[63]，表不錯誤檢查碼正確；否則若spD[〇] +[i]七 13 200847183 jut /uu〇2TW 23601twf.doc/p +[62]參SPD[63]，則表示錯誤檢查碼不正確。 另一方面，若錯誤檢查碼正確，則執行步驟S3〇8，檢 查所有記憶體模組上之規格資料是否均被讀取。若仍有規 格資料未讀取，則執行步驟S3〇4以繼續讀取其他記憶體 模組上之規格資料，並重複上述步驟S3〇4〜S3〇8，直到所 有記憶體模組上之規格資料皆讀取完畢為止。 而在步驟S306之後，同樣執行步驟S3〇8，檢查所有 φ 記憶體模組上之規格資料是否均被讀取，直到所有記憶體 模組上之規格資料皆讀取完畢為止。也就是說，在配^資 料中所有的硬體位址讀取完畢後，才執行步驟S3〇9。、 在步驟S309中，結束記憶體模組之初始化程式。當 讀取儲存在記憶體模組上之規格資料發生錯誤時，便將^ 生錯誤之記憶體模組對應於配置資料之開關攔位設定為^ 閉。 # 接下來’步驟S310即根據配置資料，關閉提供給讀 取發生錯誤之記憶體插槽的時脈訊號。藉由對應之關閉方 式’將對應之暫存器設定為關閉’以關閉提供給讀取發生 錯誤之記憶體插槽的時脈訊號。其中，例如是藉由週邊組 件互連（PCI)組態、内積體電路（I2c)、輸入輸出埠（Input Output port，10 port)以及記憶體映射輸入輪出（Mem〇ry Mapped Input Output，MMI0 )其中之一的關閉方式來關閉 時脈訊號。關閉方式記錄於配置資料之關閉方式欄位中。 圖5是依照本發明一實施例所繪示之配置資料的示意 圖。請參照圖5，配置資料中包括硬體位址攔位、關閉方 200847183 in^u/uu〇2TW 23601twf. doc/p 式攔位、暫存n位址攔位、數值攔位以及關攔位。i中， 硬體位址齡記憶_槽之硬舰址，關方式欄位 記錄關閉記紐插槽之時脈訊號的關方式，暫存器位址 攔位記錄關方式所對應之暫存n驗址及其妓，數值 攔位記錄暫存器位址之位元所要寫人的數值，開關棚位記 錄對應之§己憶體插槽為關閉或開啟。 另外’關閉方式欄位定義為0代表PCI組態關閉方 式、定義為1代表I2C _閉方式、定義為2代表1〇 p〇rt 關閉方式、絲為3代表ΜΜΙ〇關方式。數值攔位為根 據所使用的時脈產生（控制）器來定義寫人暫存器位址之 位元的數值’例如關閉方式為PCI組態，因此定義開啟之 數值（Vlaue.On)為〇，關閉之數值（vlaue〇ff)則定義 為1 °而開關攔位例如定義i為開啟時脈訊號，定義〇為 關閉時脈訊號。 以硬體位址攔位「A0」而言。在判斷讀取失敗後，即 ^關攔位狀為（）（關）。接著，根據開關位之設 疋，將對應之數值欄位所定義之關閉之數值1 ( Vlaue 〇ff) 寫入對應之暫存器位址「80!」之位元「0」内。接著，藉 由關閉方式攔位中選擇之PCI組態關閉方式，將提供給讀 取發生錯誤之記憶體插槽的時脈訊號關閉。 洋細地說’請繼續參照圖5，首先設定一變數「temp」， 用以存放數值攔位定義之數值（Vlaue 〇n、Vlaue 。 假设開關欄位等於1(開啟），則「temp」等於「Viaue 〇n」·， 否則，「temp」等於「Vlaue.Off」。接著，根據對應之關 15 200847183 ir ινν / uu〇2TW 23601twf.doc/p 閉方式攔位選擇關閉方式。 以開關攔位為關閉而言，則依據對應之數值欄位，將 「temp」設定為所定義之「vlaue〇ff」。當關閉方式搁位 定義為〇時，藉由PCI組態關閉方式將「temp」之值 (temp=l ) ’寫入Ρα組態空間之暫存器位址。當關閉方 式欄位定義為1時，藉由I2C關閉方式將「temp」之值 (temp=〇)寫入對應之暫存器位址。當關閉方式攔位定義 為2時’藉由i〇port關閉方式將「temp」之值（仿叫二工） 寫入對應之暫存器位址。當關閉方式欄位定義為3時，藉 由MMIO關閉方式將rtemp」之值（temp==〇)寫入對應之 暫存器位址。以此類推。 在將提供給讀取發生錯誤之記憶體插槽的時脈訊號 關閉後，請繼續參照圖3，步驟S311為繼續其他開機自我 測试，以將作業系統載入。因此，便可將不必要之時脈訊 5虎關閉。 綜上所述，本發明之記憶體插槽時脈的控制方法至少 具有下列優點： >。1·可自動將提供給讀取發生錯誤之記憶體插槽的時脈 訊號關閉，以降低電磁干擾。 2·關閉不必要之時脈訊號，以節省功率消耗。 〜雖然本發明已啸佳實施·露如上，然其並非用以 限定本發明，任何所屬技術領域中具有通常知識者，在不 脫離本發明之精神域_，#可作些許之更動與潤飾， 因此本發明之賴範圍當視後附之_請專聰圍所界定者 16 200847183 U^UU/UU82TW 23601twf.doc/p 為準。 【圖式簡單說明】 圖1是依照本發明一實施例所繪示之記憶體插槽時脈 的控制方法流程圖。 圖2是依照本發明一實施例所繪示之記憶體插槽時脈 的控制系統方塊圖。 圖3是依照本發明另一實施例所繪示之記憶體插槽時 脈的控制方法流程圖。 圖4是依照本發明一實施例所繪示之記憶體模組之資 料傳輸系統的方塊圖。 圖5是依照本發明一實施例所繪示之配置資料的示意 圖。 【主要元件符號說明】 201 :時脈產生器 202〜209 :記憶體插槽 401 ··處理單元 402 :晶片組 403 :主控器 404 :記憶體模組 405 :受控器Programmable Read Only, EEPROM) The SeriM Presence Detect (SPD) data is used to record the type, capacity, speed, and required voltage of the memory model. After the computer is started, the BIOS will directly read the spj) data. Then, the chipset (usually the Northbridge) can configure the corresponding timing and memory of the memory module according to the spD data to enable the memory module to operate normally. Then, in step S104, when an error occurs in the reading, the clock signal supplied to the memory slot in which the error has occurred is closed. That is, 2〇〇847』^2TW recommended doc/p said that when the specification data stored on the memory module cannot be read, it represents the connection between the memory module and the memory slot or the memory. There is a problem with the compatibility between the module and the system. At this point, the clock signal provided to its corresponding ticker slot can be turned off. ~ It is worth mentioning that the above method of turning off the clock signal can directly control the clock generator, for example, by means of a peripheral component interconnection (PCI) configuration (conflgurati〇n). The clock signal; or, an Inter Integrated Circuit (I2C) command can be sent through the chipset to turn off the clock signal. In the following, an embodiment will be described to explain in more detail the steps of the control method of the memory slot clock. FIG. 3 is a flow chart of a method for controlling a clock slot of a memory slot according to another embodiment of the invention. Referring to FIG. 3, step S301 and step S3〇2 are performed with the steps sl1i and the steps of the foregoing embodiment, and both are performed by the BIOS, and then the clock is generated to provide the clock signal to each memory. Slot. In the case that the BIOS is normally executed and the memory slot is operating normally, step ^3〇3 is an initialization program for executing the memory phantom and the group. The initialization program, for example, performs the operation of registering and relocating the scratchpad according to the technical file specification of the chipset, so that the memory module can operate normally. In step S304, the system reads the memory of the memory slot to obtain the hardware address of the memory slot, and the configuration data is stored in the mos, wherein each memory slot is recorded. Hard to stop. In a nutshell, when a hardware engineer designs a motherboard, it will give a hardware location based on the location and attributes of the memory slots on the motherboard. The address (for example, the I2C address) and record the hardware address in the configuration data. As can be seen from the above, the action of step S304 is to let the system know which memory module is to be read in the memory slot. Then, in step S305, the specification data stored on the memory module is read according to the hardware address, and it is determined whether the reading of the specification data is incorrect. For example, suppose the hardware address of the memory slot is A〇, and the hardware • address A() is recorded in the configuration data. If a memory module is inserted into the memory slot, the BIOS can find the memory slot through the system management bus (SMBus) according to the hardware address A, and the memory is inserted thereon. The body module communicates and reads the specification data. In detail, the chipset can transmit clock signals, data, and instructions (instructi〇n) through the system management bus or the 2C bus. 4 is a block diagram of a data transmission system of a memory module according to an embodiment of the invention. Referring to FIG. 4, the system includes a processing unit 4, a wafer set 402, and a memory module 404. The chipset 402 is, for example, a north bridge or a south bridge chip, and includes a master controller 403. The memory module 404 includes a slave controller 4〇5 and an electronic wiper. In addition to Programmable Read Only Memory (EEPR0M) 406. The processing unit 401 is configured to transmit an instruction to notify the chipset 402 to read the specification data. The master 403 communicates with the controlled person 405 via the system management bus 407. All instructions are sent by the main controller 4〇3, and the X controller 405 receives and replies the data to the main controller 4034EPROM406 for storing the specification data. 12 200847183 uruv /uu^2TW 23601twf.doc/p The chipset 402 retrieves the specification data from the EEPROM 406 of the memory module 4〇4 via the system management bus 407 according to the instructions transmitted by the processing unit 4〇i. At this time, by the system management bus 407, the main controller 403 will detect the response message of the controlled device 405. When the main controller 4〇3 cannot detect the response message of the controlled device 405, it means that the memory module 4〇4 can be inserted into the memory box slot. Therefore, the controlled device does not send a response message. Please continue to sign in Fig. 3. In step S305, when the specification data cannot be read, it is judged that an error has occurred in the reading. At this time, step S3〇6 is executed to set the switch field of the memory slot corresponding to the read error in the configured poor material to be closed, so as to provide the clock signal to the corresponding memory slot according to the switch block. turn off. For example, defining a blocking bit is 丨 for opening; conversely, a switch blocking is 〇 for closing. That is to say, in step S3〇2, when the clock signal is supplied to each memory slot, the switch block in the configuration data is set to 1; and in step Fantasy 6, in the configuration data The memory block corresponding to the reading error will be set to 0. In step S305, when no error occurs in the reading, step = 07^ is performed to determine whether the error check code (checksum) of the specification data is correct. . If the right = error check code is incorrect, go to step S3〇6 to set the switch block of the memory slot corresponding to the error in the configuration data to off. Also check the error check code for the ^ brother's ship data and check if the error check code matches the preset. For example, suppose SPD[o] +[]]+... SPD[63], the table does not check the correct code; otherwise if spD[〇] +[i]七13 200847183 jut /uu〇2TW 23601twf.doc/p +[62]Parameter SPD[63] indicates that the error check code is incorrect. On the other hand, if the error check code is correct, step S3 is performed to check whether the specification data on all the memory modules are read. If the specification data is still not read, execute step S3〇4 to continue reading the specification data on the other memory modules, and repeat the above steps S3〇4~S3〇8 until the specifications on all the memory modules. The data is all read. After step S306, steps S3 and 8 are also performed to check whether the specification data on all the φ memory modules are read until the specification data on all the memory modules are read. That is to say, after all the hardware addresses in the configuration data are read, step S3〇9 is executed. In step S309, the initialization program of the memory module is ended. When an error occurs in reading the specification data stored on the memory module, the memory block corresponding to the configuration data is set to be closed. #Next step S310, based on the configuration data, turns off the clock signal supplied to the memory slot in which the error occurred. The corresponding slot is set to "off" by the corresponding shutdown mode to turn off the clock signal provided to the memory slot in which the read error occurred. Among them, for example, by peripheral component interconnection (PCI) configuration, inner integrated circuit (I2c), input output port (10 port), and memory mapping input output (Mem〇ry Mapped Input Output, MMI0) ) One of the ways to turn off the clock signal. The shutdown mode is recorded in the shutdown mode field of the configuration data. FIG. 5 is a schematic diagram of configuration information according to an embodiment of the invention. Please refer to FIG. 5, the configuration data includes hardware address block, shutdown party 200847183 in^u/uu〇2TW 23601twf. doc/p type block, temporary n address block, value block and block. i, the hard address age memory _ slot hard address, the off mode field records the closing mode of the clock signal of the closing slot, the temporary storage address corresponding to the buffer address record mode The address and its 妓, the value of the value of the bit to be written by the bit of the scratchpad address, and the corresponding suffix slot of the switch shed record is turned off or on. In addition, the 'close mode field is defined as 0 for PCI configuration shutdown mode, 1 for I2C _ closed mode, 2 for 1〇 p〇rt closed mode, and 3 for wire. The value interception is to define the value of the bit of the write register address according to the clock generation (control) used. For example, the shutdown mode is PCI configuration, so the value of the open (Vlaue.On) is defined as 〇 The closed value (vlaue〇ff) is defined as 1 ° and the switch block defines, for example, i as the on-time pulse signal and 〇 as the off-clock signal. For the purpose of blocking the "A0" with the hardware address. After judging that the reading has failed, the closing position is () (off). Then, according to the setting of the switch bit, the value 1 (Vlaue 〇 ff) of the closed value defined by the corresponding value field is written into the bit "0" of the corresponding register address "80!". Then, the PCI configuration off mode selected in the Close mode block is used to turn off the clock signal supplied to the memory slot in which the error occurred. In detail, please refer to Figure 5. First, set a variable "temp" to store the value of the value block definition (Vlaue 〇n, Vlaue. If the switch field is equal to 1 (on), then "temp" is equal to "Viaue 〇n"·, otherwise, "temp" is equal to "Vlaue.Off". Then, according to the corresponding key 15 200847183 ir ινν / uu〇2TW 23601twf.doc/p closed mode, the off mode is selected. For the shutdown, the "temp" is set to the defined "vlaue〇ff" according to the corresponding value field. When the shutdown mode is defined as 〇, the "temp" is used by the PCI configuration shutdown mode. Value (temp=l) 'Write to the scratchpad address of the Ρα configuration space. When the close mode field is defined as 1, the value of "temp" (temp=〇) is written to the corresponding by I2C shutdown mode. The scratchpad address. When the shutdown mode is defined as 2, the value of "temp" (like the second job) is written to the corresponding scratchpad address by the i〇port shutdown mode. When the shutdown mode field is used. When defined as 3, the value of rtemp" (temp==〇) is written to the corresponding by MMIO shutdown mode. After the clock signal of the memory slot for reading the error is turned off, please continue to refer to FIG. 3, and step S311 is to continue the other boot self-test to load the operating system. Therefore, the unnecessary time pulse 5 can be turned off. In summary, the memory slot clock control method of the present invention has at least the following advantages: > 1 · can be automatically provided for reading The clock signal of the memory slot in which the error occurred is turned off to reduce electromagnetic interference. 2. Turn off unnecessary clock signals to save power consumption. ~ Although the present invention has been implemented, the above is not used. In order to limit the present invention, any person having ordinary knowledge in the technical field can make some changes and retouching without departing from the spirit domain of the present invention. Therefore, the scope of the present invention is attached to the _ The definition is 16 200847183 U^UU/UU82TW 23601twf.doc/p. [Simplified Schematic] FIG. 1 is a flow chart of a control method of a memory slot clock according to an embodiment of the invention. 2 is in accordance with this issue FIG. 3 is a flow chart of a control method of a memory slot clock according to another embodiment of the present invention. FIG. 4 is a flow chart of a method for controlling a clock slot of a memory slot according to another embodiment of the present invention. FIG. 5 is a block diagram of a data transmission system of a memory module according to an embodiment of the invention. FIG. 5 is a schematic diagram of configuration data according to an embodiment of the invention. [Key element symbol description] 201: Clock generator 202~209: Memory slot 401 ··Processing unit 402: Wafer group 403: Main controller 404: Memory module 405: Controlled device
406 ： EEPROM 407 :系統管理匯流排 S101〜S105 :本發明一實施例之記憶體插槽時脈的控 制方法各步驟 S301〜S311 :本發明另一實施例之記憶體插槽時脈的 控制方法各步驟 17406: EEPROM 407: system management bus S101 to S105: memory slot clock control method according to an embodiment of the present invention, steps S301 to S311: memory slot clock control method according to another embodiment of the present invention Step 17