200910548 九、發明說明： 【發明所屬之技術領域】 本發明係有關於-種半導體封裝構造，特別係有關於 一種可提高散熱效果之+導體封裝構造。 【先前技術】 習知半導體封裝構造係包含有—基板UG、—晶片 ^〇、複數個銲線130、一封膠體140及複數個銲球150, 該晶片120係設置於該基板110之一開口 111内，該些銲 線1 3 0係電性連接該晶片i 2〇與該基板11 〇，該封膠體1 係#封忒二銲線i 3 〇與該晶片i 2〇，該些銲球玉5〇係設置 於該基板110之-表面112，由於該晶片12()係設置於該 基板110之戎開口 i i丨内，且受到該封膠體i 4〇之密封保 護，因此該晶片120所產生之熱能常常無法即時導出’因 而導致電性失效。 【發明内容】 本發明之主要目的係在於提供一種半導體封裝構 造，其係包含一基板、一晶片以及一散熱裝置，該晶片係 S史置於該基板之—開口内並電性連接該基板，該散熱裝置 係設置於該基板之一上表面，該散熱裝置係定義有一受熱 區及一散熱區，該受熱區係對應於該晶片，該散熱裝置係 包含有一第一矽基板及一第二矽基板，該第一矽基板之一 第一凹槽係對應結合該第二矽基板之一第二凹槽以形成 一熱官結構’該熱管結構係具有一吸熱部及一冷卻部，其 中該吸熱部係位於該受熱區，該冷卻部係位於該散熱區。 6 200910548 由於該熱管結構之該吸熱部能將該晶片所產生之熱能攜 至該冷卻部，使得該半導體封裝構造之散熱效果提昇。 【實施方式】 請參閱第2圖，依據本發明之一具體實施例係揭示一 種半導體封裝構造200,其係包含一基板21〇、一晶片22〇 以及一散熱裝置230，該基板21〇係具有一上表面2ιι、 一下表面212、一第一開口 213、複數個第一連接墊214、 複數個苐—連接墊215及複數個第三連接墊216，該第一 開口 21 3係形成於該下表面2丨2，在本實施例中，該第一 開口 213係貫穿該上表面211及該下表面212，該些第一 連接墊214係設置於該基板21〇之該上表面211，該些第 二連接墊215及該些第三連接墊216係設置於該基板210 之該下表面212，該晶片220係設置於該第一開口 213内 並以複數個銲線240電性連接該些第二連接墊2丨5，該晶 片220係具有一主動面221及一背面222,該散熱裝置230 係设置於该基板210之該上表面211，該散熱裝置2 3 〇係 包含有一第一矽基板23〇a及一第二矽基板23〇b，該第一 矽基板230a係形成有複數個第一凹槽23 1，該第二石夕基板 23 Ob係形成有複數個第二凹槽232’其中該些第一凹槽231 及該些第二凹槽232係對應結合，以形成複數個第一熱管 結構23 3 ( Heat Pipe )’其中該些第一凹槽23 1與該此第二 凹槽2 3 2之形狀係可為三角形、矩形或梯形等幾何圖案， 該些第一凹槽23 1與該些第二凹槽232係可由該第一矽基 板23 0a與該第二矽基板230b直接於晶圓製程中形成，以 7 200910548 簡化製作β亥些第一熱管結構233之步驟。請參閱第3圖， 其係為忒散熱裝置230之上視圖，該散熱裝置23〇係定義 有一文熱區234及一散熱區235，該受熱區234係對應於 該晶片220’請再同時參閱第2及3圖，該散熱裝置23〇 係具有一第一表面236 '一第二表面237、一工作流體（圖 未、、θ出）及複數個第二開口 23 8，該些第一熱管結構23 3 係具有吸熱部233a及一冷卻部233b，該些第一熱管結 構2 3 3係為迴路式设计，在本實施例中，該些第一熱管結 構233係為平行排列，該吸熱部233a係位於該受熱區 234,該冷卻部23313係位於該散熱區235,該工作流體係 «又置於4些第-熱f結構233内，藉由該工作流體將該晶 片220所產生之熱能由該吸熱部233&傳送至該冷卻部 23 3b，以避免該晶片22〇因過熱而導致電性失效，該些第 二開口 238係貫穿該第一表面236及該第二表面237，或 者，請參閱第4圖，在另一實施例中，該些第一熱管結構 233係為交錯排列，該吸熱部233a係位於該受熱區， 該冷卻部233b係位於該散熱區235。較佳地，該晶片22〇 之該背面222係透過該第一開口 2丨3並以一具散熱功能之 接著劑（圖未繪出）貼設於該散熱裝置23 〇之該第二表面 237，使得該晶片220所產生之熱能直接導至該散熱裝置 230 ° 此外，該半導體封裝構造2〇〇係另包含有複數個電子 元件250、複數個銲球260及一封膠體270，該些電子元 件2 5 0係§又置於3亥些第二開口 2 3 8内並電性連接至該基板 8 200910548 210之該些第一連接墊214，該些電子元件25〇係可選自 於被動tl件或晶片’該些銲球26〇係設置於該基板2丨〇之 3亥下表面212且電性連接該基板21〇之該些第三連接墊 21 6以外接外部元件’該封膠體27〇係密封該些銲線24〇 及該晶片220。由於本發明之該散熱裝置23〇係具有該些 第一熱管結構233，藉由該些第一熱管結構233之該吸熱 β 233a (丈熱區）將該晶片22〇所產生之熱能攜至該冷卻 部233b (散熱區），使得該散熱裝置23〇具有良好之散熱 功能，同時提昇該半導體封裝構造2〇〇之散熱效果。 另，請參閱第5圖，在另一具體實施例，該半導體封 裝構造200係可另包含有一均熱板28〇，該均熱板28〇係 設置於該散熱裝置230之該第一表面236,使得該晶片22〇 所產生之熱能同時由該散熱裝置23〇及該均熱板28〇快速 發散，較佳地，該均熱板28〇係包含有一第三矽基板28〇& 及一第四矽基板280b，該第三矽基板28〇a係形成有複數 個第三凹槽281，該第四矽基板28〇b係形成有複數個第四 凹槽282，且該些第三凹槽28丨係對應結合於該些第四凹 槽282以形成複數個第二熱管結構283，該均熱板28〇係 具有一第三表面284及一第四表面285，該均熱板280之 該第四表面285係接觸該些電子元件25〇，以將該些電子 元件250所產生之熱能直接導出，並藉由增加該些第二熱 管結構283使該半導體封裝構造200之散熱效果倍增。 本發明之保護範圍當視後附之申請專利範圍所界定 者為準，任何熟知此項技藝者，在不脫離本發明之精神和 200910548 範圍内所作之任何變化與修改，均屬於本發明之保護範 圍。 【圖式簡單說明】 第1圖·習知半導體封裴構造之截面示意圖。 第2圖&據本發明之—第〆具體實施命丨，一冑半導體封 裝構造之截面示意圖。 第3圖：依據本發明之一第一具體實施例，該導體封裝構 造之一散熱裝置之上視圖。 第4圖：依據本發明之—第一具體實施例，該導體封裝構 造之另一種散熱裝置之上視圖。 第5圖：依據本發明之_第二具體實施例，另一種半導體 封裝構造之截面示意圖。 【主要元件符號說明】 100 半導體封裝構造 110 基板 111 開 120 晶片 130 銲 150 辉球 200 半導體封裝構造 210 基板 211 上 213 第一開口 214 第 216 第三連接墊 220 晶 222 背面 230 散 230b 第二矽基板 231 第 233 第一熱管結構 233a 吸 U 112 表面 線 140 封膠體 表面 212 下表面 一連接墊 215 第二連接墊 片 221 主動面 熱裝置 230a 第-石夕基板 —凹槽 232 第二凹槽 熱部 233b 冷卻部 10 200910548 234 受 熱區 235 散 熱 區 236 237 第 二表 面 238 第 —_ 開 V 240 250 電 子元 件 260 鲜球 270 280 均 熱板 280a 第 二 矽 基板 280b 281 第 三凹 槽 282 第 四 凹 槽 283 第 二熱 管結構 284 第 三 表 面 285 第一表面 銲線 封膠體 第四矽基板 第四表面 11BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package structure, and more particularly to a +-conductor package structure capable of improving heat dissipation. [Prior Art] A conventional semiconductor package structure includes a substrate UG, a wafer, a plurality of bonding wires 130, a gel 140, and a plurality of solder balls 150. The wafer 120 is disposed in an opening of the substrate 110. In the 111, the bonding wires 1 30 are electrically connected to the wafer i 2 〇 and the substrate 11 〇, the encapsulant 1 is a sealing wire i 3 〇 and the wafer i 2 〇, the solder balls The jade 5 is disposed on the surface 112 of the substrate 110. Since the wafer 12 is disposed in the opening ii of the substrate 110 and is sealed by the sealing body, the wafer 120 is The heat generated is often not immediately available 'and thus causes electrical failure. SUMMARY OF THE INVENTION The main object of the present invention is to provide a semiconductor package structure including a substrate, a wafer, and a heat dissipating device. The chip is placed in the opening of the substrate and electrically connected to the substrate. The heat dissipating device is disposed on an upper surface of the substrate, the heat dissipating device defines a heat receiving region and a heat dissipating region, wherein the heat receiving device corresponds to the wafer, and the heat dissipating device comprises a first crucible substrate and a second crucible a first groove of the first ruthenium substrate corresponding to a second groove of the second ruthenium substrate to form a thermal structure. The heat pipe structure has a heat absorbing portion and a cooling portion, wherein the heat absorbing portion The ministry is located in the heated zone, and the cooling section is located in the heat dissipation zone. 6 200910548 Since the heat absorbing portion of the heat pipe structure can carry the heat energy generated by the wafer to the cooling portion, the heat dissipation effect of the semiconductor package structure is improved. [Embodiment] Referring to FIG. 2, a semiconductor package structure 200 includes a substrate 21, a wafer 22, and a heat sink 230. The substrate 21 has a semiconductor package structure. An upper surface 2 ιι, a lower surface 212, a first opening 213, a plurality of first connection pads 214, a plurality of 苐-connection pads 215 and a plurality of third connection pads 216, the first opening 21 3 being formed under the In the embodiment, the first opening 213 is formed through the upper surface 211 and the lower surface 212. The first connecting pads 214 are disposed on the upper surface 211 of the substrate 21, The second connection pad 215 and the third connection pads 216 are disposed on the lower surface 212 of the substrate 210. The wafer 220 is disposed in the first opening 213 and electrically connected to the plurality of bonding wires 240. The second connection pad 2丨5, the wafer 220 has an active surface 221 and a back surface 222. The heat dissipation device 230 is disposed on the upper surface 211 of the substrate 210. The heat dissipation device 23 includes a first germanium substrate. 23〇a and a second substrate 23〇b, the first The substrate 230a is formed with a plurality of first recesses 23, and the second slabs 23b are formed with a plurality of second recesses 232', wherein the first recesses 231 and the second recesses 232 are Correspondingly combined to form a plurality of first heat pipe structures 23 3 ( Heat Pipe ), wherein the shapes of the first grooves 23 1 and the second grooves 2 3 2 may be triangular, rectangular or trapezoidal geometric patterns The first recesses 23 1 and the second recesses 232 can be formed directly from the first germanium substrate 23 0a and the second germanium substrate 230b in the wafer process, to simplify the fabrication of the beta A step of a heat pipe structure 233. Referring to FIG. 3, it is a top view of the heat sink 230. The heat sink 23 defines a hot zone 234 and a heat sink 235. The heat receiving zone 234 corresponds to the wafer 220'. In FIGS. 2 and 3, the heat sink 23 has a first surface 236 ′ a second surface 237 , a working fluid (not shown, θ out), and a plurality of second openings 23 8 . The structure 23 3 has a heat absorbing portion 233a and a cooling portion 233b. The first heat pipe structure 233 is a loop design. In the embodiment, the first heat pipe structures 233 are arranged in parallel, and the heat absorbing portion is arranged. 233a is located in the heated area 234, the cooling part 23313 is located in the heat dissipation area 235, and the working flow system is further disposed in the four first-heat-f structures 233, and the heat energy generated by the wafer 220 is generated by the working fluid. The heat transfer portion 233 & is transferred to the cooling portion 23 3b to prevent electrical failure of the wafer 22 due to overheating. The second openings 238 extend through the first surface 236 and the second surface 237, or Referring to FIG. 4, in another embodiment, the first heat pipe junctions 233 is a staggered system, the heat absorbing portion of the heat receiving section 233a located at the Department, the Department of the cooling portion 233b is located in the thermal zone 235. Preferably, the back surface 222 of the wafer 22 is through the first opening 2丨3 and is attached to the second surface 237 of the heat sink 23 by a heat-dissipating adhesive (not shown). The heat generated by the wafer 220 is directly conducted to the heat sink 230 °. The semiconductor package structure 2 further includes a plurality of electronic components 250, a plurality of solder balls 260, and a gel 270. The component 205 is placed in the second opening 2 3 8 and electrically connected to the first connection pads 214 of the substrate 8 200910548 210. The electronic components 25 can be selected from passive The solder ball 26 is disposed on the lower surface 212 of the substrate 2 and electrically connected to the third connection pads 21 6 of the substrate 21 to be externally connected to the external component 'the sealant The wire bonds 24 and the wafer 220 are sealed. The heat dissipating device 23 of the present invention has the first heat pipe structure 233, and the heat generated by the wafer 22 is carried by the heat absorption β 233a (heating zone) of the first heat pipe structure 233. The cooling portion 233b (heat dissipation region) enables the heat dissipation device 23 to have a good heat dissipation function, and at the same time, the heat dissipation effect of the semiconductor package structure 2 is improved. In addition, referring to FIG. 5 , in another embodiment, the semiconductor package structure 200 can further include a heat equalizing plate 28 , which is disposed on the first surface 236 of the heat sink 230 . The heat generated by the wafer 22 is simultaneously dissipated by the heat sink 23 and the heat equalizing plate 28. Preferably, the heat sink 28 includes a third substrate 28 and a a fourth 矽 substrate 280b, the third 矽 substrate 28 〇 a is formed with a plurality of third grooves 281, the fourth 矽 substrate 28 〇 b is formed with a plurality of fourth grooves 282, and the third concave The groove 28 is correspondingly coupled to the fourth grooves 282 to form a plurality of second heat pipe structures 283. The heat equalizing plate 28 has a third surface 284 and a fourth surface 285, and the heat equalizing plate 280 The fourth surface 285 contacts the electronic components 25 〇 to directly derive the thermal energy generated by the electronic components 250 , and multiplies the heat dissipation effect of the semiconductor package structure 200 by adding the second heat pipe structures 283 . The scope of the present invention is defined by the scope of the appended claims, and any changes and modifications made by those skilled in the art without departing from the spirit of the invention and the scope of range. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view showing a conventional semiconductor sealing structure. Fig. 2 is a schematic cross-sectional view showing a semiconductor package structure according to the present invention. Fig. 3 is a top plan view of a heat sink of the conductor package structure in accordance with a first embodiment of the present invention. Figure 4 is a top plan view of another heat sink of the conductor package construction in accordance with the first embodiment of the present invention. Figure 5 is a cross-sectional view showing another semiconductor package structure in accordance with a second embodiment of the present invention. [Main component symbol description] 100 semiconductor package structure 110 substrate 111 open 120 wafer 130 solder 150 glow ball 200 semiconductor package structure 210 substrate 211 upper 213 first opening 214 216 third connection pad 220 crystal 222 back 230 scattered 230b second Substrate 231 233 first heat pipe structure 233a suction U 112 surface line 140 encapsulant surface 212 lower surface a connection pad 215 second connection pad 221 active surface thermal device 230a - lithography substrate - groove 232 second groove heat Portion 233b Cooling section 10 200910548 234 Heated zone 235 Heat sink zone 236 237 Second surface 238 No. - _ Open V 240 250 Electronic component 260 Fresh ball 270 280 Heat spreader 280a Second turn substrate 280b 281 Third groove 282 Fourth concave Slot 283 second heat pipe structure 284 third surface 285 first surface wire sealant fourth 矽 substrate fourth surface 11