200919675 « 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種電路板及其製法，更詳而+之 -係關於藉由電料通孔作爲線路層之間的電性連接°之雷 路板及其製法。 电 【先前技術】200919675 « IX. INSTRUCTIONS: TECHNICAL FIELD OF THE INVENTION The present invention relates to a circuit board and a method of fabricating the same, and more particularly to the electrical connection between circuit layers by means of electrical vias. Lei Road board and its method of production. Electric [prior art]
Ik著半導體封裝技術的演進，半導體裝置 (Semlconductor device)已開發出不同的封裝型皞， r 半導體裝置主要係在一封壯茸, 統 罟係在封衣基板（package substrate)或 導線架上先設置一例如積體電路之半導體元件， 體元件電性連接在該封裝基板或導線架上，接著以膠體進 行封裝。而球栅陣列式(Bali gri“rray，職），例如 PBGA、TEBGA、FCBGA等，係為一種先進的半導體封裝技 術，其特點在於採用一封裝基板來安置半導體元件，並於 孩封裝基板背面才直置多冑個成栅狀陣列排列之錫球 (Solder ball)’使相同單位面積之半導體元件承载件上 :以容納更多輸入/輸出連接端（I/〇 c刪ecti〇n)以符合 高度集積化（Integration)之半導體晶片所需，藉由該些 錫球以電性連接外部電子裝置。 ~另為因應微處理器、晶片組、繪圖晶片等高效能晶片 之運算需|，佈有導線之電路板亦需提昇其傳遞晶片訊 號、改善頻寬、控制阻抗等功能，以因應高1/〇數封裝件 ，發展。然而，為符合半導體封裝件輕薄短小、多功能、 尚速度及高頻化的開發方向’半導體晶片封裝用之電路板 110418 5 200919675 ，已朝向細線路及小孔徑發展。現有電路板製程從傳統1〇〇 微米之線路尺寸··包括導線寬度（Line width)、線路間距 (Space)及深寬比（Aspect ratio)等，縮減至30微米，並 持續朝向更小的線路精度進行研發。 為k向半導體晶片封裝用之電路板之佈線密度，業界 遂發展出一種增層技術（Bui ld-up)，亦即在一核心電路板 (Core circuit board)表面利用線路增層技術交互堆疊多 層介電層及線路層，並於核心電路板令形成電鍍導通孔 (plated through-hole，PTH)及於該介電層中開設導電 盲孔（Conductive via)以供上下層線路之間電性連接。 請參閱第1A至1K圖，係為習知形成封裝用電路板之 製法剖視圖；首先提供一有機絕緣層所構成之核心板 10,於該核心板1〇兩表面分別具有金屬薄層1〇1(如第ia 圖所不），接著以雷射或機械鑽孔的方式形成複數貫穿之 通孔（thr〇ugh-hole)l〇2(如第1B圖所示）；然後，於該 核心板10之兩表面以及通孔1〇2中之表面形成一第一導 電層11a(如第1(：圖所示）；於該第—導電層ιι&表面電 鐘形成-第-金屬層12a，並於該通孔1Q2中形成一電鑛 孔、121(如帛1D圖所示）；之後以塞孔材料120填入Ik is advancing the semiconductor packaging technology. The semiconductor device (Semlconductor device) has developed different package types. The r semiconductor device is mainly used in a strong velvet, and the system is first on the package substrate or lead frame. A semiconductor component such as an integrated circuit is provided, and the body component is electrically connected to the package substrate or the lead frame, and then encapsulated by a colloid. Ball grid array (Bali gri "rray", such as PBGA, TEBGA, FCBGA, etc., is an advanced semiconductor packaging technology, which is characterized by using a package substrate to house semiconductor components, and on the back of the package substrate Directly stacking a plurality of gated arrays of solder balls to make the same unit area of the semiconductor component carrier: to accommodate more input/output connections (I/〇c ecti〇n) to match A semiconductor chip with a high degree of integration is required to electrically connect external electronic devices by the solder balls. ~ Another operation for high-performance chips such as microprocessors, chipsets, and graphics chips is required. The circuit board of the wire also needs to improve its function of transmitting the chip signal, improving the bandwidth, controlling the impedance, etc., in order to meet the requirements of high 1/〇 package. However, in order to meet the requirements of semiconductor package, it is light, short, versatile, fast and high. Frequency development direction of the circuit board for semiconductor chip packaging 110418 5 200919675, has been developed towards thin lines and small apertures. Existing circuit board process from the traditional 1 micron line Inch ·· including wire width, space, and aspect ratio, reduced to 30 microns, and continued to develop toward smaller line accuracy. The wiring density of the circuit board, the industry has developed a layer-up technology (Bui ld-up), that is, on the surface of a core circuit board (Core circuit board) using a line-growth technology to alternately stack multiple layers of dielectric layers and circuit layers, and A plated through-hole (PTH) is formed on the core circuit board, and a conductive via is formed in the dielectric layer to electrically connect the upper and lower lines. Please refer to FIGS. 1A to 1K. A cross-sectional view of a conventionally formed circuit board for packaging; firstly, a core board 10 composed of an organic insulating layer is provided, and a metal thin layer 1〇1 is respectively disposed on both surfaces of the core board (as shown in the ia diagram) And then forming a plurality of through holes (thr〇ugh-hole) l〇2 (as shown in FIG. 1B) by laser or mechanical drilling; then, on both surfaces of the core plate 10 and through holes The surface of 1〇2 forms a first guide The electric layer 11a (as shown in FIG. 1) is formed on the surface of the first conductive layer to form a first metal layer 12a, and an electric ore hole 121 is formed in the through hole 1Q2 (eg, 帛1D picture); then filled with plug material 120
後，該塞孔材料 又形成—薄化金屬層12a，，而該塞孔材 口名虫刻製程影響，於進行表面蝕刻製程之 120之兩端凸出於該薄化金屬層12a，表 110418 6 200919675 面(如第IF圖所不)；並藉由刷磨製程移除該塞孔材料 ⑽凸出之广位，使該核心板10表面平整（如第1G圖所 丁 i，接著，於该薄化金屬層12a，表面及塞孔材料120 之端面形成—第二導電層lib，且藉由該第二導電層nb 以電鍍形成-電鍍金屬層13 (如第1H圖所示)；J該帝 鑛金屬層13表面形成—阻層14 ’且該阻層 :製程形成有複數開口 14。以露出該電鏡金屬層= 伤表面（如第11圖所示）；以蝕刻製程移除該阻層14之門 口⑷中的電録金屬層13、第二導電層爪、薄化金屬層 卢、4-導電層lla及金屬薄層1〇1以形成圖案化之 二T路層15a’且於該電鍍導通孔121之兩端形成金屬 墊/51、(如第u圖所示）；之後，移除該阻層14，然後 \ ^板10及第—線路層15a表面形成線路增層結構 及線路增層結構16係包括有至少一介電層⑽、疊 1,,. ，於》亥”電層上之第二線路層脱，以及形成於該介電層 2亚電性連接該第二線路層脱及第一線路層…之導 希t 4(CCmdUCtlVe Μ8) 162，且部份之導電盲孔161 ^士 Ϊ第—線路層15^金屬墊15卜又於該線路增 表面具有電性連接該第二線路層15b之電性連 ㈣rd)162’且於該線路增層結構16表面具有一絕緣 值 '二1 7該絕緣保護層17表面具有複數個開口 170， 乂路出錢路增層結構16之電性連接塾162(如第Μ 圖所示）。 准，忒基孔材料120之端面係與該薄化金屬層12a， 110418 7 200919675 二面月平並位於該第二導電層爪下方，而該薄化金屬層 / ^之熱膨脹係數與塞孔材料⑽之熱膨脹係數不同，於 後績熱循環製程φμ , 中使该苐二導電層lib受該薄化金屬層 /、f孔材料12〇之不同熱應力的影響，且該塞孔材料 二：端面係高於該核心板10表面，而易形成結構上應 市之弱點，導致該第二導電層lib及該第一線路層 15a容易產生脫層分離的情況。 θ 因此，如何提出—種電路板及其製法，以避免習知雷 Γ路板之錢導通孔内之塞孔㈣與線路層之_敎膨脹 係數不同導致脫層分離的情況，實已成爲目前業界㈣克 服之難題。 竹允 【發明内容】 征-^上”知技術之缺點，本發明之—目的係在於提 ’、“路板及其製法’係為該電路板中塞孔材料之端面 =該核心板之表面，藉以避免於該電路板内部產生庫 力集中之情形。 ,i王應 之目的係在於提供—種電路板及其製法，係 減>、線路層之厚度以利於細線路製程。 括且述及其他目的，本發明提供—種電路板，係包 括具有至少一貫穿通孔之核心板；形成於該通孔中之電鍍 導通孔，填充於該電鍍導通孔 、又 ^ 灸基孔材枓，且該塞孔材 該核心板之表面;以及設於該核心板之兩 <屯鑛導通孔、及塞孔材料之端面的第—線路層，並 具设於該電鑛導通孔端面之金屬塾以與該電鑛導通孔 110418 8 200919675 - 電性連接。 .電層路層係由第二金屬層及第二導 .層、薄化金屬層、第—導電“二？屬層、第二導電 又依上述結構，復包括=屬溥層構成。 核心板及第一線路層二括二=增層結構，係形成於該 f —介電層、疊置於該介電增層結構係包括有至少 该介電層中並電性連接該第： 層以及形成於 '之複數導電盲孔以電性連接 電盲孔，且部份 該線路增層結構表面具有複數、”、層及金屬墊’又於 電性連接塾，並於該線路增層結構表連面第二線路層之 該絕緣保護層表面具有複數個開 緣保護層， 本發明復提供—種電路板 路出該電性連接塾。 有兩表面之核心板，於該核心^ :糸匕括.提供一具 面之通孔;於該通孔中形成至少-貫穿其兩表 内填充塞孔材料，且該塞孔材料之子L，，該電鑛導通孔 表面；以及於該核心板之二相 面：向於該核心板之 孔材料之端面形成第一線路芦，曰表面、電錢導通孔、及塞 導通孔電性連接。 θ使垓第一線路層與電鍍 依上述製法，該核心板中形成 包括：該核心板之兩表面具有導通孔之製程係 表面及開孔中之表㈣成 ^專層該金屬薄層 電層表面電鑛形成—第一金屬//層；以及於該第一導 錢導通孔。 “層，輕該通孔中形成該電 110418 9 200919675 又該電鍍導通孔内形成兮愛 战忒基孔材料之製程係包括：於 該％鐘v通孔内填充該塞孔材料· 二斤一 几材枓，移除該核心板二相對表 面之第一金屬層的部份厚度 形成一缚化金屬層，並使該 基孔材料兩端凸出於該薄化金 „ . A I屬層表面，移除該塞孔材料 凸出的部位，使該塞孔材料 赢τ办κ 叶兩螭表面與缚化金屬層之表面 齊平；移除該塞孔材料兩端 破斗 之部份材料，使該塞孔材料之 %?面不南於该核心板之矣 .Afterwards, the plug material is further formed into a thinned metal layer 12a, and the plug hole material is affected by the engraving process, and the thinned metal layer 12a protrudes from the two ends of the surface etching process 120, Table 110418 6 200919675 face (as shown in the IF figure); and removing the convexity of the plug hole material (10) by the brushing process, so that the surface of the core plate 10 is flat (as shown in Fig. 1G, then, The thinned metal layer 12a, the surface and the end surface of the plug material 120 form a second conductive layer lib, and the second conductive layer nb is plated to form a plating metal layer 13 (as shown in FIG. 1H); The surface of the metal layer 13 of the ore is formed with a resist layer 14' and the resist layer: the process is formed with a plurality of openings 14 to expose the electron mirror metal layer = the damaged surface (as shown in FIG. 11); the resist is removed by an etching process a galvanic metal layer 13, a second conductive layer, a thinned metal layer, a 4-conductive layer 11a, and a thin metal layer 1〇1 in the gate (4) of the layer 14 to form a patterned two-T-layer 15a' A metal pad /51 is formed on both ends of the plating via hole 121 (as shown in FIG. 5); after that, the resist layer 14 is removed, and then the ^1 plate 1 Forming a line build-up structure and a line build-up structure 16 on the surface of the 0 and the first circuit layer 15a includes at least one dielectric layer (10), a stack 1, and a second circuit layer on the "Hi" electrical layer, and Formed in the dielectric layer 2 electrically connected to the second circuit layer to the first circuit layer ... guide t 4 (CCmdUCtlVe Μ 8) 162, and a portion of the conductive blind hole 161 ^ Ϊ Ϊ - line layer 15 The metal pad 15 further has an electrical connection (four) rd) 162' electrically connected to the second circuit layer 15b on the line increasing surface and an insulation value '27' on the surface of the line build-up structure 16. The surface of the 17 has a plurality of openings 170, and the electrical connection 塾 162 of the circuit-adding structure 16 (as shown in FIG. 2). The end face of the quasi-base material 120 and the thinned metal layer 12a, 110418 7 200919675 The two-sided moon is located below the second conductive layer claw, and the thermal expansion coefficient of the thinned metal layer is different from the thermal expansion coefficient of the plug material (10), and is made in the post-heat cycle process φμ The two conductive layers lib are affected by different thermal stresses of the thinned metal layer/f hole material 12〇, and The hole material 2: the end face is higher than the surface of the core plate 10, and is easy to form a structurally weak point, which causes the second conductive layer lib and the first circuit layer 15a to easily cause delamination separation. θ Therefore, how Proposed a kind of circuit board and its manufacturing method to avoid the fact that the plug hole (4) in the money guiding hole of the conventional Thunder road board and the _敎 expansion coefficient of the circuit layer cause delamination and separation, which has become the industry (4) to overcome Zhu Yun [invention] The shortcomings of the technology of the levy - ^ on the technology, the purpose of the invention is to mention ', 'the road plate and its method' is the end face of the plug material in the circuit board = the core board The surface is used to avoid the situation where the concentration of the reservoir is concentrated inside the board. , i Wang Ying's purpose is to provide a kind of circuit board and its manufacturing method, reduce the thickness of the circuit layer to facilitate the fine line process. The invention provides a circuit board comprising: a core plate having at least one through hole; a plated through hole formed in the through hole, filled in the plated through hole, and the moxibustion hole hole枓, and the surface of the core plate of the plug hole material; and a first circuit layer disposed on the two ends of the core plate and the end face of the plug hole material, and disposed on the end face of the electric mine conduction hole The metal crucible is electrically connected to the electric ore via 110418 8 200919675. The electrical layer layer is composed of a second metal layer and a second conductive layer, a thinned metal layer, a first conductive “two-layer layer, and a second conductive layer according to the above structure, and the complex layer includes a germanium layer. And the first circuit layer is formed by a second layer of a build-up layer, and is formed on the f-dielectric layer, and the dielectric build-up structure includes at least the dielectric layer and electrically connected to the first layer and Forming a plurality of conductive blind vias to electrically connect the electrical blind vias, and some of the surface of the build-up structure has a plurality of, ", layers and metal pads" and electrical connections, and the build-up structure of the lines The surface of the insulating protective layer of the second circuit layer of the joint has a plurality of open edge protective layers, and the present invention provides a circuit board to exit the electrical connection. a core plate having two surfaces, wherein the core is provided with a through hole; and a through hole is formed in the through hole; and a material of the plug hole material The surface of the electroconductive ore hole; and the two phase surfaces of the core plate: a first line reed is formed on an end surface of the hole material of the core plate, and the surface of the crucible, the electric conduction hole, and the plug via are electrically connected. θ is used to make the first circuit layer and the electroplating according to the above-mentioned manufacturing method, and the core plate is formed by: a process system surface having a via hole on both surfaces of the core plate and a surface in the opening (4) forming a thin layer of the metal thin layer Surface electric ore formation - a first metal / / layer; and the first money guiding via. "Layer, lightly forming the electric hole in the through hole 110418 9 200919675 The process system for forming the base material of the enamel warp in the electroplated via hole comprises: filling the plug hole material in the through hole of the % clock v. a plurality of materials, removing a portion of the thickness of the first metal layer on the opposite surface of the core plate to form a binding metal layer, and causing both ends of the base material to protrude from the surface of the thinned gold layer. Removing the protruding portion of the plug material, so that the surface of the plug material is flush with the surface of the metallized layer; removing part of the material of the broken material at both ends of the plug material The % of the plug material is not souther than the core plate.
It 乂 ，以及移除該核心板二相對 表面，：化金屬層、第一導電層及金屬薄層。 5亥第一線路層復包括有 铲道、s π * ^ 方鱼屬墊，且该金屬墊設於該電 鍍導通孔之鳊面，且該第一 括.』 琛路層及金屬墊之製程係包 括.於该核心板二相對表面、带 之端面形成-第二導電料通孔、以及塞孔材料 層，且今阻M 該第二導電層表面形成一阻 :阻層中形成有複數開口 層，於該阻層之開口中的 弟一导電 金屬層，使該第二金屬屛及當 曰表面形成有-第二 層，且使該第一唆踗厗S 一導電層構成該第一線路 使W線路層與該電料通孔電性連接 除该阻層及其所覆蓋之第二導電層。 及移 本發明復提供兮· Μ & 製程，係包括：於該薄、、路層及金屬墊之另-種實施 於以一導電層上形成—阻 W層’ 口以露出該第二導電芦:J層中形成有複數開 形成第二金屬層 曰:：表面，於該阻層之開口中 屬層、第-導電層及全屬=屬層、第二導電層、薄化金 第—線路層與該電錢 曰且使该 ¥通孔電性連接；以及移除該阻層 110418 10 200919675 ，及其所覆蓋之薄化金屬層、第 本發明復提供該第'線路層導:二及塾金屬薄層。 程’係包括：於該核心板-相 〃蜀塾之又—實施製 -塞孔材料之端面形成-第二導電層=導通孔、以及 形成有-第二金屬層；於：厘。弟-導電層表面 層’且該阻層中形成有複數開口以露出:二面：成-阻 層；钱刻移除該阻層之開口中 ° ”之第二金屬 層；以及移除該阻層，使該未移除之第及第二導電 電層構成該第一線路層，且第、 i蜀層及第二導 孔電性連接。 使5亥第—線路層與該電鍍導通 本發明復提供該第—線路層及 程，係包括：於該薄化金屬層表面愈夷萄t再—實施製 形成有第二導電層；於該 帝、土孔材料之兩端表面 屬層；於該第二金屬層表面：:表成有第二金 有複數開口以露出該第二金^卩層’且相層中形成 移除該阻層之開口中之第之部份表面；以及蝕刻 屬層、第-導電層及金屬：屬：、第二導電層、薄化金 層、第二導電層、薄化二7第使=移除之第二金屬 連接。 第-線路層與該電鍍導通孔電性 本發明又依前述之萝蘚 介電層中並電性連接該第：-線路層、以及形成於該 亥弟-線路層之導電盲孔，且部份之 110418 11 200919675 複數導電盲孔以電性連接哕 線路增層結構表面、▲路層及金屬墊，又於該 傅衣面具有稷數電性 性連接墊，並於該鎗改秘思，丄 莰^弟一、-泉路層之電 絕緣保護層表面且有㈣彳_ 緣保4層’该It 乂 , and remove the opposite surface of the core plate, the metal layer, the first conductive layer and the thin metal layer. The first circuit layer of the 5th layer includes a shovel, s π * ^ square fish pad, and the metal pad is disposed on the surface of the plated through hole, and the process of the first . . 层 layer and the metal pad The method comprises: forming a second conductive material through hole on the opposite surface of the core plate 2, the end surface of the strip, and a plug material layer, and forming a resistance on the surface of the second conductive layer: a plurality of openings are formed in the resist layer a layer of a conductive metal layer in the opening of the resist layer, such that the second metal germanium and the surface of the germanium are formed with a second layer, and the first germanium S conductive layer constitutes the first The circuit electrically connects the W circuit layer to the electrical material via hole except the resistive layer and the second conductive layer covered thereby. And the method of the present invention includes: forming, in the thin layer, the road layer and the metal pad, forming a barrier layer on the conductive layer to expose the second conductive Reed: A plurality of layers are formed in the J layer to form a second metal layer:: a surface, in the opening of the resist layer, a layer, a first conductive layer, a total genus layer, a second conductive layer, a thinned gold- a circuit layer and the electric money 电 and electrically connecting the ¥ through hole; and removing the resist layer 110418 10 200919675, and the thinned metal layer covered by the same, the first invention provides the 'th line layer guide: two And a thin layer of tantalum metal. The process includes: forming the end face of the plug-in material in the core plate - the end face is formed - the second conductive layer = the via hole, and the second metal layer is formed; a conductive layer surface layer' and a plurality of openings are formed in the resist layer to expose: two sides: a resist layer; the second metal layer of the opening of the resist layer is removed; and the resistor is removed a layer, the unremoved first and second conductive layers form the first circuit layer, and the first, second and second vias are electrically connected. The fifth layer and the circuit layer are electrically connected to the present invention. The step of providing the first circuit layer and the process includes: forming a second conductive layer on the surface of the thinned metal layer and forming a second conductive layer on the surface of the emperor and the soil hole material; The surface of the second metal layer is: having a second gold having a plurality of openings to expose the second metal layer and forming a surface of the first portion of the opening in the phase layer to remove the resist layer; and etching the genus The layer, the first conductive layer and the metal: genus: a second conductive layer, a thinned gold layer, a second conductive layer, a thinned second VII, a second metal connection removed. The first circuit layer and the galvanic conduction The electroporation of the present invention is further in accordance with the foregoing radiant dielectric layer and electrically connected to the :---------- Conductive blind holes in the road layer, and some of the 110418 11 200919675 multiple conductive blind holes are electrically connected to the surface of the 增 line build-up structure, ▲ road layer and metal pad, and have a plurality of electrical connection pads on the surface And in the gun to change the mystery, 丄莰 ^ brother 1, the spring layer of the electrical insulation layer and there are (four) 彳 _ margin 4 layers '
Um數個開口以露出該電性連接塾。 目父於習知技術’本發明之電路板及其製法，歹 心板中形成有電錢導通孔’之後於該導通 入端衫 高於該核心板之表面的塞孔材料，而於後續製程: 層，可較習知技術形成更穩固之金屬墊結構，以及於該: 心板之二表面、電料通孔及塞孔材料之端面形成線路 層，且該線路層係電性連接該電錢導通孔，俾使該塞孔材 t之端面不南於該核心板之表面，於該後續電路板之熱循 壤製程中，避免因該塞孔姑料I f田闲 尤口亥基孔材科與其周圍之金屬材料熱膨脹 係數不同所產生之熱應力及因結構上之弱點形成應力隹 中’而導致脫層分離之缺失，且部份之複數導電盲 於該金屬墊上並對應於電鍍導通孔開口 ’而可增加; 孔之佈線空間。 【實施方式】 以下係藉由特定的具體實例說明本發明之實施方 式，熟悉此技藝之人士可由本說明書所揭示之内容輕易地 瞭解本發明之其他優點與功效。 請參閱第2A至2M圖，係為詳細説明本發明之電路板 之製法之第一實施例之剖面示意圖。 如第2A圖所示，首先，提供一係為有機絕緣層所構 成之核心板20，於該核心板20之表面呈有今屋$ ^ 八另i屬溥層201， Π0418 12 200919675 其中該金屬薄㉟201 一般係以導電性較佳之 主，本實施例係以銅荡基板（CCL)為例作說明。（Cu)為 如第2B圖所示，復以機械鑽孔方式或雷射 =。核心板2°中形成複數個貫穿該核心板2。之通ί 如第2C圖所示，接著，利 / 0丄 .、 切王'兄積例如減鑛 fUm is open to expose the electrical connection port. The parent is in the prior art process of the circuit board of the present invention and the method for manufacturing the same, in which the electric money conducting hole is formed in the core plate, and then the plug hole material is higher than the surface of the core plate. The layer can form a more stable metal pad structure than the prior art, and form a circuit layer on the surface of the core plate, the surface of the electric material through hole and the plug hole material, and the circuit layer is electrically connected to the electricity layer The money guide hole, so that the end face of the plug hole material t is not souther than the surface of the core plate, in the hot circuit process of the subsequent circuit board, avoiding the hole hole of the hole hole The thermal stress generated by the difference between the thermal expansion coefficient of the metal material and the surrounding metal material and the formation of the stress 隹 in the structural weakness point, resulting in the absence of delamination separation, and part of the multiple conductive blindness on the metal pad and corresponding to the plating conduction The opening of the hole can be increased; the wiring space of the hole. [Embodiment] The embodiments of the present invention are described below by way of specific examples, and those skilled in the art can readily understand other advantages and effects of the present invention from the disclosure of the present disclosure. Referring to Figures 2A through 2M, there are shown cross-sectional views illustrating a first embodiment of a method of fabricating a circuit board of the present invention. As shown in FIG. 2A, firstly, a core plate 20 composed of an organic insulating layer is provided, and on the surface of the core plate 20, there is a current floor of the ^ ^ 另 i 溥 201 layer 201, Π 0418 12 200919675 wherein the metal Thin 35201 is generally preferred to be electrically conductive. This embodiment is described by taking a copper-plated substrate (CCL) as an example. (Cu) is as shown in Figure 2B, with mechanical drilling or laser =. A plurality of core plates 2 are formed through the core plate 2 in the core plate. As shown in Figure 2C, then, Lee / 0丄., 切王's brother, such as mine reduction f
(Smmenng)或化學沈積例如無電•式，以於該核 2〇之金屬薄層2()1上及通孔2〇2中之表面形成一第一 ^ 電層2la’該第一導電層21a主要作為後述電鍍金 所需之電流傳導路徑’其可由金屬、合金或沉積數層金屬 層所構成’如選自銅、錫、錄、絡、鈦及銅-鉻合金等所 組群組之其中一者，或該第一導電層係為聚乙炔、聚 苯胺或有機硫聚合物等導電高分子材料。 如第2D圖所示，藉由該第—導電層21a作為電鍍之 電流傳導路徑，以於該核心板2〇之二表面的第一導電層 21a表面形成第一金屬層22a，並於該通孔202中形成電 鍍導通孔（Plated through hole, pth)221;其中，該第 一金屬層22a之材料可為諸如鉛、錫、銀、銅、金、级、 銻、鋅、鎳、鍅、鎂、銦、碲以及鎵等金屬之其中—者； 惟’依貫際操作之經驗，由於銅為成熟之電鑛材料且成本 較低，因此，該苐一金屬層22a以由電链銅所構成者為較 佳’但非以此為限。 如第2E圖所示’之後復填充一導電或不導電之塞孔 材料23(如絕緣性油墨或含銅導電膏等）以填滿該電錢導 Π0418 13 200919675 ，通孔2 21殘留之空隙。 、如第2F圖所示，該第一金屬層22a表面進行表面蝕 J 製程（surface uniform etching process, SUEP)以形 成-溥化金屬I 22a，，❿該塞孔材料23並不受表面餘刻 衣私（SUEP)之衫響，於進行表面蝕刻製程之後，該塞孔材 料23之兩端凸出於該薄化金屬層22&,表面。 如第2G圖所不，進行刷磨製程以移除凸出該薄化金 屬層22a，表面之塞孔材料23,以維持該核心板2〇表面之 C 平整性。 如第2H圖所示，利用離子機射、雷射、或钱刻製程 繼續移除部分之塞孔_23，使該塞孔㈣23之端面不 高於該核心板20之表面，而於後續製程填人金屬層，可 軚習知技術形成更穩固之金屬墊結構。(Smmenng) or chemical deposition, for example, an electroless type, to form a first electrical layer 2la' on the surface of the metal thin layer 2()1 and the via 2'2 of the core 2' It is mainly used as a current conduction path required for electroplating gold described later. It can be composed of a metal, an alloy or a plurality of deposited metal layers, such as selected from the group consisting of copper, tin, nickel, copper, copper and chromium alloys. Alternatively, the first conductive layer is a conductive polymer material such as polyacetylene, polyaniline or organic sulfur polymer. As shown in FIG. 2D, the first conductive layer 21a is used as a current conducting path for electroplating to form a first metal layer 22a on the surface of the first conductive layer 21a of the surface of the core plate 2, and the pass is formed. A plated through hole (pth) 221 is formed in the hole 202. The material of the first metal layer 22a may be, for example, lead, tin, silver, copper, gold, grade, bismuth, zinc, nickel, bismuth, magnesium. Among the metals such as indium, antimony and gallium; but only in the experience of continuous operation, since copper is a mature electric ore material and the cost is low, the first metal layer 22a is composed of electric chain copper. It is better 'but not limited to this. As shown in FIG. 2E, a conductive or non-conductive plug material 23 (such as an insulating ink or a copper-containing conductive paste) is filled to fill the gap of the electric hole guide 0418 13 200919675 and the through hole 2 21 . As shown in FIG. 2F, the surface of the first metal layer 22a is subjected to a surface uniform etching process (SUEP) to form a deuterated metal I 22a, and the plug material 23 is not affected by the surface remnant. The SUEP shirt is ringing, and both ends of the plug material 23 protrude from the surface of the thinned metal layer 22& after the surface etching process. As shown in Fig. 2G, a brushing process is performed to remove the plug material 23 protruding from the surface of the thinned metal layer 22a to maintain the C flatness of the surface of the core sheet 2. As shown in FIG. 2H, the portion of the plug hole _23 is continuously removed by the ion jet, laser, or engraving process so that the end face of the plug hole (4) 23 is not higher than the surface of the core plate 20, and is subsequently processed. Filling the metal layer can form a more stable metal pad structure by conventional techniques.
如第21圖所示，藉由例如钱刻製程移除該核心板別 二相對表面之薄化金屬層22a，、第一 薄層20卜 弟*㈣2la 如第2J圖所示，於該核心板2〇表面、電鍛 f/、以及塞孔材料23二端面形成一第二導㈣21b’該 弟-導電I 21b主要作為後述電鑛金屬材料所需之 傳導路徑，其可由金屬、合金或沉積數層 抓 或該第二導電層21b係為聚 s構成， η承〇炔、水本胺或有機硫 等導電高分子材料’’接著，於該第二導電層仙上形： 層24’該阻層24可為—例如乾膜或液態光阻等光阻声 (Photoresist)，其係利用印刷、旋塗或貼合等方 ^ 110418 14 200919675 於该第二導電層21b表面’再藉由曝光、顯影等方式加以 圖案^ ’以形成複數開σ 24G以露出該第二導電層训 之部分表面’其中部份開σ 2 4 Q係相對應形成於 通孔221之位置。 杈等 如第2K圖所示，藉由該第二導電層训作為電鑛之 電流傳導路徑，以於該等開口 24G中電鑛形成—第二 層22b’其中該第二金屬層挪之材料可為諸如叙、錫、 銀、銅、金、叙、錄、鋅、鎳、錯、鎂、銦、蹄以及嫁等 金屬之其中—者；，准，依實際操作之經驗，由於銅為成孰 之電鍍材料且成本較低，因此，該第二金屬層22b以由電 鑛銅所構成者為較佳，但非以此為限；該第二金屬層挪 = =21b構成該第一線路層25a，且藉由”錢 *通孔221電性連接該核心板2〇上表面及下表面之第一 線路層25a’該第一線路層25a中具有位於該電錢導通孔 221開孔上之金屬墊251。 如第2L圖所示，藉由例如脫膜及飯刻製程移除該阻 層24及其所覆蓋之第二導電層训以露出該第一線路声 25a及金屬墊251。 曰 刘弟利所示，最後’於該核心板2〇及第一線路層 25a表面形成'線路增層結構26，該線路增層結構 包括有至少一介電層260、疊置於該介電層上之第二線路 層25b’以及形成於該介電層中並電性連接該第二線路声 25b之導電盲孔26卜且部份之複數導電盲孔261電性連 接該第一線路層25&及金屬墊25卜又於該線路增層結構 110418 15 200919675 • 26表面具有複數電性i車垃兮楚_ μ 、， ％㈣接㈣-線路層25b之電性連接 塾2 6 2 ’亚於該線路增芦紝播 • 97 ^ 岭θ層、·Ό構26表面形成一絕緣保護層 27 ’戎纟巴緣保護層27表面且右诘 衣囟具有歿數個開口 270以對應露 出該電性連接塾2 6 2。 心 本發明後提供一種電路^ 板係包括：核心板2〇,係 具有兩表面，於該核心板2〇中 之通孔1電錄導通孔221Γ 其兩表面 电級導通孔22卜係形成於該通孔2〇2中之 ,^ 材料23，係填充於該電鍍導通孔221中，且 '該fL材料23之端面不高於該核心板20之表面;以及第 通孔22卜及塞孔材料23之端/ 2〇之兩表面、電錢導 ,a 〇 之舳面，该第一線路層25a係 居？“ 2b及第二導電層2lb組成，且該第一線路 層25a具有金屬墊251位於該雷辦^ ' + & * 茨冤鍍導通孔221開口以盥該 電鍍導通孔221電性連接。 〃、 ▲依上述結構，復包括—線路增層結構Μ )该核心板20及第一線路層25a / 、 係包括有至少一介電層26〇、疊置：，=構26 路層挪、以及形成於該介電層中電層^第二線 層25b之導電盲孔26卜且部 I連接该第二線路 、Φ 一外ώ 丨伪之歿數導電盲孔261電性 連接该弟一線路層25a及金屬墊？ M 本品目n 屬塾251，又於該線路增層結 構26表面具有稷數電性連接該第二線路層25b之電性連 接墊262，並於該線路增層結構％ 電1連 27，該絕緣保護層27表面且有複數個〃，絕緣保護層 電性連接塾262。 〜有複數個開口 270以露出該 110418 16 200919675 請參閱第3A至3D圖’係為詳細説明本發明之電路板 之製法之弟一貫施例之剖面示意圖。 如3A圖所示，提供一係如第2H圖所示之結構，於該 薄化金屬層22a，、電料通孔221、以及塞孔材料 核心板20表面形成一第二導電層仙：帛著，於該第二 導電層21b上形成有—阻層24，且該阻層24中形成有不; 數開口 240以露出該第二導電層別之部份表面。 如第3B圖所示’藉由該第二導電層⑽作為電鑛之 電流傳導路徑’以於該阻層24之各該開口 24〇中電㈣ 成-第二金屬層22b’ ^於該電鍵導通孔221 ^ 成有金屬墊251，使該第二金屬層22b、第二導 ， 薄化金屬層22a，、第一導電層21a :成 第-線路層心，且藉由該電鑛導通孔叫= 核心板20上表面及下表面之第一線路層25a，。連接5亥 如第3C ®所示’移除該阻層2 屬層况、第-導電層21a及金屬薄層:覆…化金 2二第:1圖1示’最後’於該核心板2°及第-線路層 面形成一線路增層結構26，該： 包括有至少-介電層260、疊置於該介電心構2係 層25b，以及形成於該介電層中並電ς弟-線路 2此之導電盲孔261，且部份之複數導電盲;層 接邊第-線路層仏及金屬塾251 =性連 Μ表面具有複數電性連接該第二、層結構 塾⑽，並於該線路增層結構層:b之電性連接 衣面形成一絕緣保護層 17 110418 200919675 • 2 7 ’該絕緣保護層2 7 # a亡> 士 出該電性連接墊262。、 稷數個開口 270以對應露 :且有^明復提供一種電路板，係包括：核心板2。，係 1 於該核心板20中形成至少-貫穿其兩表面 一 泠孔221，係形成於該通孔202中之 ，基孔材料23 ’係填充於該電錢導通孔⑵中，且 6玄基孔材料2 3之端面不古热j·方4六1 -線路層2 5 a，抑成二:广:心9板2 〇之表面;以及第 係形成於该核心板20之兩表 通孔221、及塞孔材料23 ,p E 十d之&面’该弟一線路層25a係 25 ^*Ί221)及第二導電層21b組成，該第一線路層 1第金屬層❿，、第一導電層21a、金屬薄層20! .一孟屬層22b構成，且具有金屬墊251位於該 通孔221端面以與該電鍍導通孔221電性連接'。 '又 依上述結構，復包括一線路增層結構2 該核心板20及第一線路# 25a#fe +糸形成於 層仏a表面该線路增層結構26 係匕括有至少一介電層26〇、疊置於該介電層上之 路層25b、以及形成於該介電層中並電性連接 ^路 層咖之導電盲孔261，且部份之複盲孔 =接該第-線路層25&及金屬替251，又於該線路增^ 構26表面具有複數電性連接該第二線路層咖之^ ^妾墊⑽，並於該線路增層結構26表面具有絕緣保護層 ，该絕緣保護層27表面具有複數個開口 27〇 電性連接墊262。 路出該 請參閱第4A至4E圖，係為詳細説明本發明之電路板 110418 18 200919675 之製法之第三實施例之剖面示意圖。 士第4A圖所不，首先，提供一係如第21圖所示之結 構’於§亥核心板2 〇面* /洛增、3： 假υ衣囟甩鍍導通孔221、以及塞孔材 料23二端面形成一第二導電層训，該第二導電層加 主要作為後述電鑛金屬材料所需之電流傳導路徑，其可由 金'、合金或沉積數層金屬層所構成，或該第二導電層 21b係為聚乙炔、聚苯胺或有機硫聚合物等導電高分子材 如第4B圖所示，接著，藉由該第二導電層训作為 電鍵之電流傳導路徑，以於該第二導電層训表面電鑛形 成一第 '一金屬層2 2 b ’並中兮楚—a /¾ K? /、中忒第一金屬層22b之材料可為 諸如錯、錫、銀、銅、今、朽、拉 .、一 金鉍、銻、鋅、鎳、锆、鎂、銦、 蹄以及叙專金屬之JL中一去.也 ^ 于蜀U者，惟，依實際操作之經驗 於銅為成熟之電錢材料且成本較低，因此，該第 22b以由電錢所構成者為較佳，但非以此為限。曰 如第4C圖所示，狹德於上合结 …、後於该第二金屬層22b上 層24,該阻層24可為一例如乾膜或液態光阻 (Ph〇t〇reSiSt)，其係利用印刷、旋塗或貼合等方式开^ 於該第二金屬層22b表面，再藉由曝光、顯影 ： 圖案化’以形成複數開σ 24。以露 2 之部分表面。 *屬層22b 如第4D圖所示’藉由例如蝕刻製程移除該阻 之開口 240中的第二金屬層饥及第二導電層^ 並移除該阻層24,使該第二金屬層 ’接耆 木—¥電層21b Π0418 19 200919675 第一線路層25a’且藉由該電鑛導通孔221電性連 m反2〇上表面及下表面之第一線路層❿，該第 層25a中具有位於該電鑛導通孔221開孔上之金屬 如弟4E圖所示，最後，於兮妨、、j 。 + 取俊於忒核心板20及第一線路層 2 5 a表面形成-線路增層結構2 6，該線路增層結構2 6係 Γ =至少一介電層⑽、叠置於該介電層上之第二線路 曰5b’以及形成於該介電層中並電性連接該第二線路声 现之導電盲孔26卜且部份之複數導電盲孔261電心 ，該第-、㈣層25a及㈣墊251，又於該線路增層結構 面具有m數電性連接該第二線路層25b之電性連接 墊262’並於該線路增層結構％表面形成—I緣保護層 27’該絕緣保護層27表面具有複數㈣口 m以對 出該電性連接墊262。 〜 本發明復提供一種電路板，係包括：才亥心板20,係 具有兩表面’於該核心板2〇中形成至少一貫穿其兩表面 之L孔202，电鍍導通孔221，係形成於該通孔2〇2中之 表面；塞孔材料23，係填充於該電鍵導通孔221中，且 該塞孔材料23之端面不高於該核心板2〇之表面；以及第 一線路層25a ’係形成於該核心板20之兩表面、電鍍導 通孔221、及塞孔材料23之端面，該第-線路層25a係· 由第二金屬層22b及第二導電層2lb組成，且該第一線路 層25a具有金屬墊251位於該電鍍導通孔221端面以與該 電鍍導通孔221電性連接。 110418 20 200919675 依上述結構，復包括—線路增層結構26,係形成於 該核心板20及第一绩改® . 々成方、 #勺杯右5 表面，該線路增層結構％ 係包括有至少一介電層26〇、疊 + -^ 9r, 、，l 1於5亥"电層上之第二線As shown in FIG. 21, the thinned metal layer 22a of the opposite surface of the core board is removed by, for example, a credit engraving process, and the first thin layer 20 is abbreviated as shown in FIG. 2J on the core board. 2〇 surface, electric forging f/, and the second end surface of the plug material 23 form a second guide (four) 21b'. The younger-conductive I 21b is mainly used as a conductive path required for the later-described electric ore metal material, which may be metal, alloy or deposition number. The layer or the second conductive layer 21b is composed of poly s, and the conductive polymer material such as η acetylene, water-based amine or organic sulfur is then formed on the second conductive layer: layer 24' The layer 24 can be, for example, a photoresist film such as a dry film or a liquid photoresist, which is printed, spin-coated or laminated, etc. on the surface of the second conductive layer 21b by exposure, The pattern is formed by developing or the like to form a plurality of openings σ 24G to expose a portion of the surface of the second conductive layer, wherein a portion of the opening σ 2 4 Q is correspondingly formed at the position of the through hole 221.杈, as shown in FIG. 2K, the second conductive layer is used as a current conduction path of the electric ore to form an electric ore in the openings 24G—the second layer 22b' wherein the second metal layer is moved It can be used for such metals as Syria, Tin, Silver, Copper, Gold, Syria, Record, Zinc, Nickel, Wrong, Magnesium, Indium, Hoof and Marriage; The electroplating material of the crucible is lower in cost. Therefore, the second metal layer 22b is preferably composed of electro-mineral copper, but is not limited thereto; the second metal layer shift ==21b constitutes the first line The layer 25a is electrically connected to the first circuit layer 25a' of the upper surface and the lower surface of the core board 2 through the "money through hole 221". The first circuit layer 25a has the opening in the electric money conducting hole 221 The metal pad 251. As shown in FIG. 2L, the resist layer 24 and the second conductive layer covered thereon are removed by, for example, a stripping and rice etching process to expose the first line sound 25a and the metal pad 251.曰Liu Dioli, finally, 'forms the line buildup structure 26 on the surface of the core board 2〇 and the first circuit layer 25a, which The via build-up structure includes at least one dielectric layer 260, a second circuit layer 25b' stacked on the dielectric layer, and a conductive blind via formed in the dielectric layer and electrically connected to the second line sound 25b. 26 and part of the plurality of conductive blind holes 261 are electrically connected to the first circuit layer 25 & and the metal pad 25 and the line build-up structure 110418 15 200919675 • 26 surface has a plurality of electrical properties 车 兮 _ μ , (4) connected (4) - the electrical connection of the circuit layer 25b 塾 2 6 2 'Asian on the line increased reed broadcast · 97 ^ ridge θ layer, · Ό structure 26 surface formed an insulating protective layer 27 '戎纟巴缘The surface of the protective layer 27 has a plurality of openings 270 to correspondingly expose the electrical connection 塾2 6 2 . The present invention provides a circuit board comprising: a core plate 2 〇 having two surfaces, The via hole 1 of the core board 2 is electrically connected to the via hole 221, and the two surface electric level via holes 22 are formed in the through hole 2〇2, and the material 23 is filled in the plating via hole 221, And the end surface of the fL material 23 is not higher than the surface of the core plate 20; and the through hole 22 and the plug material 23 / 2 〇 two surfaces, electric money guide, a 〇 舳, the first circuit layer 25a is composed of "2b" and the second conductive layer 2lb, and the first circuit layer 25a has a metal pad 251 located in the mine ^ ' + & * 冤 plating through hole 221 opening to electrically connect the plating via 221 . 〃, ▲ according to the above structure, the complex-to-line build-up structure Μ) the core board 20 and the first circuit layer 25a /, including at least one dielectric layer 26 〇, stacked:, = 26 layers, And a conductive blind hole 26 formed in the second layer 25b of the electrical layer of the dielectric layer, and the portion I is connected to the second line, and the plurality of conductive blind holes 261 are electrically connected to the first one. Circuit layer 25a and metal pad? The present item n belongs to the 251, and has a plurality of electrical connection pads 262 electrically connected to the second circuit layer 25b on the surface of the line build-up structure 26, and is electrically connected to the circuit at the circuit. The surface of the insulating protective layer 27 has a plurality of turns, and the insulating protective layer is electrically connected to the crucible 262. ~ There are a plurality of openings 270 to expose the 110418 16 200919675 Please refer to Figures 3A to 3D' for a detailed cross-sectional view of a conventional embodiment of the circuit board of the present invention. As shown in FIG. 3A, a structure as shown in FIG. 2H is provided, and a second conductive layer is formed on the surface of the thinned metal layer 22a, the electric material through hole 221, and the plug material core plate 20. A resist layer 24 is formed on the second conductive layer 21b, and the resist layer 24 is formed with a plurality of openings 240 to expose a portion of the surface of the second conductive layer. As shown in FIG. 3B, 'the second conductive layer (10) is used as the current conducting path of the electric ore to enable the electric opening (four) to the second metal layer 22b' in the opening 24 of the resist layer 24. The via hole 221 is formed with a metal pad 251 such that the second metal layer 22b, the second conductive layer, the thinned metal layer 22a, and the first conductive layer 21a are formed into a first-line layer core, and the conductive hole is through the conductive hole Called = the first circuit layer 25a of the upper surface and the lower surface of the core board 20. Connect 5 Hai as shown in 3C ® 'Remove the resist layer 2 genus layer, the first conductive layer 21a and the metal thin layer: cover ... gold 2 2: 1 Figure 1 shows 'final' on the core board 2 Forming a line build-up structure 26, and comprising: at least a dielectric layer 260, stacked on the dielectric core 2 layer 25b, and formed in the dielectric layer and electrically - the conductive blind hole 261 of the line 2, and a part of the plurality of conductive blind; the layered edge - the circuit layer and the metal 塾 251 = the surface of the splicing has a plurality of electrical connections to the second, layer structure 塾 (10), and In the circuit build-up structure layer: b electrically connected to the clothing surface to form an insulating protective layer 17 110418 200919675 • 2 7 'the insulating protective layer 2 7 # a death> out of the electrical connection pad 262. And a plurality of openings 270 to correspond to the dew: and there is a circuit board provided by the system, comprising: the core board 2. The system 1 is formed in the core plate 20 at least through a hole 221 thereof, formed in the through hole 202, and the base hole material 23' is filled in the money guiding hole (2), and 6 The end face of the base material 2 3 is not ancient heat j·square 4 6 1 - the circuit layer 2 5 a, the suppression is 2: wide: the surface of the heart 9 plate 2 ;; and the second line formed by the first system on the core plate 20 a hole 221, and a plug hole material 23, a portion of the surface layer 25a of the circuit layer 25a, and a second conductive layer 21b, the first layer of the first layer 1 The first conductive layer 21a, the thin metal layer 20b, and a metal layer 22b are formed, and the metal pad 251 is located at the end surface of the through hole 221 to be electrically connected to the plating via 221'. According to the above structure, the core layer 20 and the first line #25a#fe +糸 are formed on the surface of the layer a. The line build-up structure 26 includes at least one dielectric layer 26 a layer 25b stacked on the dielectric layer, and a conductive blind via 261 formed in the dielectric layer and electrically connected to the layer, and a portion of the blind via = connected to the first line The layer 25 & and the metal 251, and the surface of the circuit structure 26 have a plurality of electrical connections to the second circuit layer (10), and an insulating protective layer on the surface of the circuit build-up structure 26, The surface of the insulating protective layer 27 has a plurality of openings 27 and electrical connection pads 262. Referring to Figures 4A through 4E, there is shown a cross-sectional view showing a third embodiment of the method of manufacturing the circuit board 110418 18 200919675 of the present invention. In the fourth picture of Figure 4A, firstly, a structure such as the structure shown in Fig. 21 is provided in the core plate 2 of the § * * / / / / / / / / 3 3 3 3 3 3 3 3 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及A second conductive layer is formed on the second end surface of the second conductive layer, and the second conductive layer is mainly used as a current conducting path required for the later-described electric ore metal material, which may be composed of gold, alloy or deposited metal layers, or the second The conductive layer 21b is a conductive polymer material such as polyacetylene, polyaniline or organic sulfur polymer, as shown in FIG. 4B, and then the second conductive layer is used as a current conduction path of the electric bond to the second conductive layer. The layered surface electrowinning forms a 'metal layer 2 2 b ' and the middle layer - a / 3⁄4 K? /, the material of the first metal layer 22b of the middle layer can be such as wrong, tin, silver, copper, present,朽, 拉., 一金铋, 锑, 锌, 锌, 锌, 锌, 锌, 蹄, and the JL in the metal of the special metal. Also ^ Yu Yu U, but based on the experience of practical operation in copper for maturity The electricity money material has a low cost. Therefore, the 22nd bd is preferably made up of electricity money, but is not limited thereto. For example, as shown in FIG. 4C, the upper layer is bonded to the upper layer 24 of the second metal layer 22b, and the resist layer 24 may be, for example, a dry film or a liquid photoresist (Ph〇t〇reSiSt). The surface of the second metal layer 22b is opened by printing, spin coating or lamination, and then patterned and patterned to form a complex opening σ 24 . Take part of the surface of the dew 2 . The genus layer 22b is as shown in FIG. 4D. The second metal layer in the opening 240 of the resist is removed by the etching process, for example, by etching the second conductive layer and removing the resist layer 24. '接耆木—¥电层21b Π0418 19 200919675 The first circuit layer 25a' and electrically connected to the first circuit layer 〇 of the upper surface and the lower surface by the electric ore via 221, the first layer 25a The metal having the opening on the opening of the electric mine conduction hole 221 is as shown in the figure 4E, and finally, in the figure, j. + take the 忒 core board 20 and the first circuit layer 2 5 a surface formation - line build-up structure 2 6, the line build-up structure 26 6 system Γ = at least one dielectric layer (10), stacked on the dielectric layer And a second conductive line b5b′ and a plurality of conductive blind holes 261 formed in the dielectric layer and electrically connected to the conductive blind hole 26 of the second line, and the first and fourth layers 25a and (4) pad 251, further having an electrical connection pad 262' electrically connected to the second circuit layer 25b on the line build-up structure surface and forming an I-side protection layer 27' on the surface of the line build-up structure % The surface of the insulating protective layer 27 has a plurality of (four) ports m to face the electrical connection pads 262. The present invention further provides a circuit board comprising: a core board 20 having two surfaces 'in the core board 2', at least one L hole 202 penetrating through the two surfaces thereof, and a plating via 221 formed in the core board a surface of the through hole 2〇2; a plug hole material 23 is filled in the key contact hole 221, and an end surface of the plug hole material 23 is not higher than a surface of the core plate 2〇; and the first circuit layer 25a ' is formed on both surfaces of the core plate 20, the plated via 221, and the end face of the plug material 23, the first circuit layer 25a is composed of the second metal layer 22b and the second conductive layer 2lb, and the first A wiring layer 25a has a metal pad 251 located at an end surface of the plating via 221 to be electrically connected to the plating via 221 . 110418 20 200919675 According to the above structure, the complex-line-adding structure 26 is formed on the core board 20 and the first grade change®. 々成方, #匙杯右5 surface, the line build-up structure% includes At least one dielectric layer 26〇, stacked + -^ 9r, ,, l 1 is on the second line of the 5th "electric layer
Hr:形成於該介電層中並電性連接該第二線路 : ¥電目孔26卜且部份之複數導電盲孔261電性 連接該第一線路層25a及金屬 M ofi * ^ . Μ又於该線路增層結 數電性連接該第二線路層挪之電性連 接墊262，並於該線路增層沾 1^連 〇Γ7 尽D構26表面具有絕緣保鳟岸 27 ’該絕緣保護層27表面且古、—去l / I曰 電性連接墊262。 以路出4 請參閱第5A至5D圖，係為詳細 之製法之第四實施例之剖面示意圖。 月之電路板 如第5A圖所示，提供—係 ^ ^ /L ^ 丁又乐圖所不之結構，於 5亥溥化金屬層2 2 a ’、電鍍導補a 0 0 、 令分、上 通孔22丨、以及塞孔材料23 之核心板20表面形成—第導 » 等免詹211);接著，拉 第一導電層21a作為雷供+中 错由5亥 电a Zia作為讀之電流傳導路徑，以於 电層灿表面電鍍形成—第二金屬層咖。 —導 如第_示，於該第二金屬層22b表面形 層2 4 ’且該阻層2 4中形忐古、-丰Δ .s a 〇 成有锼數開口 240以露出該第一 金屬層22b之部份表面。 弟一 如第5C圖所示，蝕刻銘a分打β ^ m 9〇u墙 移除該阻層24之開口 240中&Hr: formed in the dielectric layer and electrically connected to the second line: a plurality of conductive vias 261 electrically connected to the first circuit layer 25a and the metal M ofi * ^ . And electrically connecting the second connection layer of the electrical connection pad 262 to the circuit, and adding the layer to the connection layer on the line. The surface of the D structure 26 has an insulation protection bank 27 'the insulation The surface of the protective layer 27 and the ancient, - l / I 曰 electrical connection pads 262. Referring to Figures 5A through 5D, there is shown a cross-sectional view of a fourth embodiment of the detailed method. As shown in Figure 5A, the circuit board of the month provides the structure of the ^ ^ / L ^ Ding and Le Tu, and the metal layer 2 2 a ', the plating guide a 0 0 , the order, The upper through hole 22丨, and the surface of the core plate 20 of the plug material 23 are formed—the third guide is omitted (Jan 211); then, the first conductive layer 21a is pulled as the mine supply + the middle fault is read by the 5 The current conduction path is formed by electroplating on the surface of the electric layer - the second metal layer. a first surface of the second metal layer 22b, wherein the surface layer 24' is formed in the second metal layer 22b, and the resist layer 24 is formed with a plurality of openings 240 to expose the first metal layer. Part of the surface of 22b. As shown in Figure 5C, etch the inscription a β ^ m 9〇u wall to remove the opening of the resist layer 24 240 &
弟一金屬層2213、第二導雷恳011^ J 道干a 等電層21卜薄化金屬層22a，、第 一導電層21a及金屬薄層2〇1 第 22b、苐二導電層21b、薄化仝遥β 〇。 屬僧 匕金屬層22a，、第一導電層21 110418 21 200919675 .及金屬薄層洲構成第一線路層25a, 細之開孔形成有金屬塾25ί，且 鑛導通 電性連接該核心板2G上表面及下^〜通孔如 25a;最後並移除該阻層24。 艾弟—線路層 如第5D圖所示，最後’於該核心板 =面形成一線路增層結構26，該二 =至少-介電層⑽、疊置於該介電層上之第構： 層25b，以及形成於該介電層中並電性 卓:線路 25b之塞當^ —線路層 接#份之魏導電盲孔_電性連 26表面具有複數電性連接該第二線路層咖之電性遠^ 墊脱，並於該線路增層結構 ::該絕緣保護層27表面具有複數個上;：f 出该電性連接墊2 6 2。 、心路 且有设提供一種電路板’係包括：核心板20，係 於該核心板20中形成至少-貫穿其兩表面 =孔電鍍導通孔221 ’係形成於該通孔2〇2中之 ^ ’基孔材料23 ’係填充於該電鑛導通孔221中，且 孔材料23之端面不高於該核心板20之表面；以及第 一線路層❿’係形成於該核心板20之兩表面、電錢導 通孔22卜及窠：?丨锊抱〇〇 導 25a# 、首 弟一 V私層21b、溥化金屬層22a，、 弟一 ¥電層21a及金屬薄層2G1組成，且具有金屬塾25ι 位於4电鍍導通孔221端面以與該電鑛導通孔221電性連 110418 22 200919675 - 接。 又"、、，口構，说巴秸綠峪增層結構26，係 該核心板20及第一線路層25 ’、戍价 ^ ^ __ θ 表面，该線路增層結構26 係包括有至少-介電層26G、叠置於該介電層上 路層25b、以及形成於該介雷屎 —，’泉 層25b之,m 中亚電性連接該第二線路 電目孔261，且部份之複數導電盲孔261電性 連接該苐一線路層25a及金屬墊251，又於該 = f 構26表面具有複數電性連接該屉7 a曰、、Ό 牧邊弟一線路層25b之電性诖 妾墊⑽’並於該線路增層結構26表面具有絕緣保護層 ，该絕緣保護層27表面具有複數個開口 27〇 電性連接墊262。 亥 相較於習知技術，本發明之電路板及其製法，主要係 先於核心板中形成電鑛導通孔，之後於該導通孔中填入夷 孔材料，並使該塞孔材料之端面不高於該核心板之表面土， 以及於該核心板之二表面、電錢導通孔及塞孔材料之端面 υ形成線路層，且該線路層係電性連接該電鍍導通孔，由於 該塞孔材料之端面係不高於該核心板之表面，於該後續電 路板之熱循環製程中，避免因該塞孔材料與其周圍之金屬 材料熱膨脹係數不同所產生之熱應力及因結構上之弱點 應力集中，而導致脫層分離之缺失，且部份之複數導 電盲孔設置於該金屬墊上並對應於電鍍導通孔開口，而可 增加導電盲孔之佈線空間。 上述實施例僅例示性說明本發明之原理及其功效，而 非用於限制本發明。任何熟習此項技藝之人士均可在不違 110418 23 200919675 貫施例進行修飾與改 應如後述之申請專利 背本發明之精神及範疇下，對上述 變。因此’本發明之權利保護範圍， 範圍所列。 【圖式簡單說明】 第1A至1K圖係為習知封妒田+ T我用電路板之萝法. 第2Α至2Μ圖係為本發明之畲 & & ’ 兔塔板之製法夕笛 — 例之剖面示意圖；以及 *之弟—貫施 f 第3A至3D圖係為本發明 之剖面不意圖， 電路板之製法之第 一實施例 第4A至4E圖係為本發明電路板之製法—一 之剖面示意圖；以及 第二貫施例a metal layer 2213, a second lead Thunder 011 ^ J track dry a isoelectric layer 21 thin metal layer 22a, a first conductive layer 21a and a thin metal layer 2〇1 22b, a second conductive layer 21b, Thinning with the same β 〇. The bismuth metal layer 22a, the first conductive layer 21 110418 21 200919675 . and the thin metal layer form the first circuit layer 25a, the fine opening is formed with the metal 塾25ί, and the mineral conductive connection is connected to the core plate 2G. The surface and the underlying via are as 25a; finally, the resistive layer 24 is removed. The Adi-line layer, as shown in Fig. 5D, finally forms a line build-up structure 26 on the core plate=face, the second=at least-dielectric layer (10), the first structure superposed on the dielectric layer: a layer 25b, and is formed in the dielectric layer and electrically: the plug of the line 25b is connected to the surface of the layer, and the surface of the conductive layer 26 has a plurality of electrical connections. The electrical property is far away from the pad, and the layer is added to the circuit: the surface of the insulating protective layer 27 has a plurality of upper surfaces; the f is the electrical connecting pad 2 6 2 . The circuit board includes a core board 20, and the core board 20 is formed in the core board 20 at least - through the two surfaces = the hole plating via 221 ' is formed in the through hole 2 〇 2 'The base material 23' is filled in the electric conduction hole 221, and the end surface of the hole material 23 is not higher than the surface of the core plate 20; and the first circuit layer ❿' is formed on both surfaces of the core plate 20. , the electric money conduction hole 22 and the 窠:? 丨锊 〇〇 25 25a#, the first brother a V private layer 21b, the bismuth metal layer 22a, the brother and the electric layer 21a and the metal thin layer 2G1, and The metal 塾25ι is located on the end surface of the 4th plating via 221 to be electrically connected to the electric ore via 221 110418 22 200919675 -. And ",,, mouth structure, said the bar straw green layer structure 26, the core board 20 and the first circuit layer 25 ', the price of ^ ^ __ θ surface, the line build-up structure 26 includes at least a dielectric layer 26G, a layer 25b stacked on the dielectric layer, and a sub-layer 25b formed in the dielectric layer 25b, wherein the second line is electrically connected to the second line electric hole 261, and the portion is electrically connected The plurality of conductive blind vias 261 are electrically connected to the first circuit layer 25a and the metal pad 251, and have a plurality of electrical connections on the surface of the = f structure 26 to electrically connect the drawer 7 a 曰, Ό 牧 弟 弟 a line layer 25 b The mat (10)' has an insulating protective layer on the surface of the line build-up structure 26, and the surface of the insulating protective layer 27 has a plurality of openings 27 and electrical connection pads 262. Compared with the prior art, the circuit board of the present invention and the manufacturing method thereof mainly form an electric ore via hole in the core plate, and then fill the hole in the through hole and make the end face of the plug hole material No more than the surface soil of the core board, and a circuit layer formed on the two surfaces of the core board, the electric money conducting hole and the end surface of the plug hole material, and the circuit layer is electrically connected to the plating via hole, because the plug The end surface of the hole material is not higher than the surface of the core plate, and in the thermal cycle process of the subsequent circuit board, the thermal stress caused by the difference in thermal expansion coefficient between the plug material and the surrounding metal material and the structural weakness are avoided. The stress concentration causes the absence of delamination separation, and a part of the plurality of conductive blind holes are disposed on the metal pad and correspond to the plating via opening, thereby increasing the wiring space of the conductive blind holes. The above-described embodiments are merely illustrative of the principles of the invention and its effects, and are not intended to limit the invention. Anyone who is familiar with the art can modify and adapt to the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of the invention is set forth in the scope of the claims. [Simple description of the diagram] The 1A to 1K diagrams are the conventional method of sealing the field + T I use the circuit board. The 2nd to 2nd drawings are the invention of the invention && & The flute - a schematic cross-sectional view of the example; and the younger brother - the third embodiment of the present invention is not intended to be a cross-section of the present invention, and the fourth embodiment of the circuit board manufacturing method is the circuit board of the present invention. Systematic method - a schematic diagram of the section; and a second embodiment
第5A至5D圖係為本發明電路板之製法之第 之剖面不意圖。 【主要元件符號說明】 10、20 核心板 101 ' 201 金屬薄層 102 、 202 通孔 11a、21a 第一導電層 lib、21b 第二導電層 120 塞孔材料 12a、22a 苐一金屬層 121 ' 221 電鍍導通孔 12a， 、 22a， 薄化金屬層 13 電鍍金屬層 四實施例 Π0418 24 200919675 14、24 140 、 240 15a 、 25a 、 25a 151 ' 251 15b、25b 16、26 160 、 260 161 、 261 162 、 262 17、27 170 、 270 22b 23 阻層 開口 第一線路層 金屬墊 第二線路層 線路增層結構 介電層 導電盲孔 電性連接墊 絕緣保護層 開口 第二金屬層 塞孔材料5A to 5D are cross-sectional views of the first embodiment of the circuit board of the present invention. [Main component symbol description] 10, 20 core board 101' 201 metal thin layer 102, 202 through hole 11a, 21a first conductive layer lib, 21b second conductive layer 120 plug material 12a, 22a 苐 a metal layer 121 '221 Plating vias 12a, 22a, thinned metal layer 13 electroplated metal layer 4 Π 0418 24 200919675 14, 24 140, 240 15a, 25a, 25a 151 '251 15b, 25b 16, 26 160, 260 161, 261 162 262 17, 27 170 , 270 22b 23 Resistive layer opening first circuit layer metal pad second circuit layer line build-up structure dielectric layer conductive blind hole electrical connection pad insulation protection layer opening second metal layer plug material
C 25 110418C 25 110418