200939242 九、發明說明： 【發明所屬之技術領域】 尤指一種可以改善輸入訊號 時間的記憶體模組以及存取 本發明係有關一種記憶體模組， 之上升/下降時間以及增加建立/保持 該記憶體模組的方法。 【先前技術】 ❹ 請參考第1圖，第1圖為習知雙列接腳記憶體模組（Dual IMrneMe，Module，DlMMM⑻的示意圖如第！圖所示雙 列接腳記憶體模組漏包含有八個記憶體晶片⑽少训8，其卡 每-個記憶體晶片均包含有29個輸入接腳。在雙列接腳記憶體模 組1〇〇的操作上，如第1圖所示，29筆輸入訊號係由一控制器12〇 產生，並經由輸入接腳（未繪示）輸入至記憶體晶片n〇J，之後 再循序傳輸至記憶體晶片110一2、110—3、…、110一8，然而，後端 公的圮憶體晶片（例如110—7、11〇_8)會因為前端記憶體晶片的等 效RLC(電阻/電感/電容)訊號衰減效應而造成輸入訊號的上升時間 (rising time)以及下降時間（falling time)增加，並導致輸入訊 號的建立時間（setuptime)以及保持時間（holdtime)的降低。 請參考第2圖，第2圖為第1圖所示之記憶體晶片11〇_1〜11〇_8 之輸入訊號的眼圖（eye pattern )。如第2圖所示，越後端的記憶 體晶片，其眼寬（eyewidth) W也越小，尤其是最後一個記憶體 晶片110_8的眼寬為919皮秒（pico-second)，遠小於記憶體晶片 110_1的眼寬（1057皮秒），因此對於後端的記憶體晶片而言，在 5 200939242 可能不足而產生訊號不穩 誤。 錄高頻訊號的建立時間（setupt_) 疋的情況秘«料_上料產生錯 【發明内容】 因此本發明的目的之— 升/下降日在於M、—種可以改善輸人訊號之上 B 建立/保持時間的記憶體模組以及存取圮情體模 組的方法，以解決上述的問題。 佛此體模 ❹ ^本發月之冑施例，其揭露—種記憶體模組。該記憶體 模殂包3有複數個記憶體次池以及複數_人接腳，其中每一200939242 IX. Description of the invention: [Technical field of the invention] In particular, a memory module capable of improving the input signal time and accessing the memory module of the present invention, the rise/fall time and the increase/build time The method of the memory module. [Prior Art] ❹ Refer to Figure 1, which is a schematic diagram of a conventional dual-column memory module (Dual IMrneMe, Module, DlMMM (8). The double-column memory module is included in the figure! There are eight memory chips (10) less training 8, and each card contains 29 input pins per memory chip. In the operation of the dual-column memory module, as shown in Figure 1. The 29 input signals are generated by a controller 12A, input to the memory chip n〇J via an input pin (not shown), and then sequentially transferred to the memory chip 110-2, 110-3, ... 110-8, however, the back-end memory chip (such as 110-7, 11〇_8) will cause input signals due to the equivalent RLC (resistance/inductance/capacitance) signal attenuation effect of the front-end memory chip. The rising time and falling time increase, and the setup time (setuptime) and the hold time (holdtime) of the input signal are reduced. Please refer to Figure 2, Figure 2 is shown in Figure 1. The eye pattern of the input signal of the memory chip 11〇_1~11〇_8 (eye pattern) As shown in Fig. 2, the smaller the back end of the memory chip, the smaller the eye width W, especially the eye width of the last memory chip 110_8 is 919 pico-second, much smaller than the memory. The eye width of the bulk wafer 110_1 (1057 picoseconds), so for the memory chip at the back end, the signal instability may be insufficient at 5 200939242. The setup time of the high frequency signal (setupt_) 疋_Loading error [Invention] Therefore, the purpose of the present invention is that the rise/fall time is M, a memory module that can improve the B setup/hold time above the input signal, and access to the modal module. The method to solve the above problem. This physique ❹ ^ This month's 胄 胄 , 其 其 其 其 其 其 其 其 种 种 种 种 种 种 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆Pins, each of them
個记憶體次模_包含錢數個記㈣晶片且職數個記憶體晶 ’、串聯此外肖複數組輸入接腳分別搞接至該複數個記憶體 次模組，用以接收相同的複數個輸人訊號，每—組輸人接腳係用 以將該複數個輸入訊號傳送至相對應的記憶體次模組中，且每一 組輸入接腳包含有二十九個輸人接腳，該二十九個輸人接腳分別 用來接收兩辦脈域、十六個記憶體健輸人訊號、三個記憶 庫位址輸入訊號、一晶片選擇訊號、一列位址選通（r〇waddress str〇be)訊號、一行位址選通訊號（column address strobe)、一寫 入致能（writeenable)訊號、一内部中斷電阻（on_dieterminati〇n) 訊號、一時脈致能訊號（CKE)、一校準訊號(zq)以及一重置（reset) 訊號。 依據本發明之另一實施例，其揭露一種記憶體模組。該記憶 200939242 * 職組包含有複數個記顏次池以及複數崎人接腳’其中每 一個記憶體次模組係包含有複數個記憶體晶片且該複數個記憶體 晶片係串聯，此外’該複數組輸人接_分_接至顯數個輯 體次模組，用以接收相同的複數個輸入訊號，每一組輸入接腳^ 用以將該複數個輸入訊號傳送至相對應的記憶體次模組中，且每 一組輸入接腳包含有至少十九個輸入接腳，該至少十九個輸入接 腳分別用來接收至少六個列位址訊號、至少五個行位址訊號、一 ❹列位址晶片選擇罐、-行位址晶片選擇訊號、兩個時脈訊號、 一内部中斷電阻（on-dietermination)訊號、一時脈致能訊號 (CKE)、一校準訊號（ZQ)以及一重置訊號（reset)。 依據本發明之另一實施例，其揭露一種存取記憶體模組的方 法。該方法包含有··於該記憶體模組設置複數個記憶體次模組， 其中每一個記憶體次模組係包含有複數個記憶體晶片且該複數個 ❹記憶體晶片係串聯；於該記憶體模組設置複數組輸入接腳，用以 接收相同的複數個輸入訊號；以及傳送該複數個輸入訊號至相對 應的記憶體次模組中，其中該複數個輸入訊號包含有兩個時脈訊 號、十六個記憶體位址輸入訊號、三個記憶庫位址輸入訊號、一 晶片選擇訊號、一列位址選通訊號、一行位址選通訊號、一寫入 致能§孔號、一内部中斷電阻〇DT ( on-die termination )訊號、一時 脈致能訊號(CKE)、一校準訊號（ZQ)以及一重置訊號（reset)。 依據本發明之另一實施例，其揭露一種存取記憶體模組的方 7 200939242 .法。财法包含有：於就賴設置概地㈣次模組， 其中每-個記憶體次模組係包含有複數個記憶體晶以該複數個 記憶體晶片係串聯；於該記憶體模組設置複數組輸人接腳，用以 接收相同的複數個輸入滅；以及傳送該複數個輸入訊號至相對 應的記憶體次模組巾’其中該複數個輸人峨包含有至少六個列 位址訊號、至少五贿位址峨、—舰址晶片選擇訊號、、一行 位址晶片選擇訊號、兩個時脈訊號、一内部中斷電阻訊號、一時 ❹脈致能訊號(CKE)、一校準訊號以及一重置訊號。 依據本發明所提供之記憶體模組以及存取記憶體模組的方 法’可以改善輸入訊號之上升/下降時間以及建立准持時間，進而 增進資料判讀的正確性。 【實施方式】 ❹ 4參考帛3 ® ’帛3圖為本發明記憶H模組之—實施例的示 思圖°如第3圖所示’記憶體模組包含有（但不限於）兩個 記憶體次模組302J、302—2以及第-、二組輸入接腳304j、 304—2其中a己憶體次模組分別包含有複數個記憶 體晶片310—1〜31〇一4以及310一5〜310一8,其中每一個記憶體晶片均 包含有29個輸入接腳，且記憶體晶片310_1〜310_4以及記憶體晶 片310—5〜310—8係分別串聯，此外，第一、二組輸人接腳3〇4」、 304—2分別包含有29個輸入接腳，且第一、二組輸入接腳、 304—2分別連接至記憶體晶片31〇 *以及31〇 5。 200939242 在記憶麵、组300的操作上，如第3圖所示，第一組輸入訊 號係由-控制器320產生，並經由第一組輸入接腳3〇4ι輸入至 記憶體晶片31〇_〇，之後再循序傳輸至記憶體晶片31〇 3、 310—2、310J ;同樣地’第二組輪入訊號亦是由控制器32〇產生， 並經由第二組輸入接腳3〇4_2輸入至記憶體晶片31〇 5中，之後 再循序傳輸至記憶體晶片310〜6、31()_7、則』。第—組輸入訊號 〇 以及第二組輸入訊號係為相同的訊號，且第一、二組輸入訊號分 別包含有29筆輸入訊號，其中該29筆輸入訊號為兩個時脈訊號、 十六個記憶體位址輸入訊號、三個記憶庫位址輸入訊號、一晶片 選擇訊號、一列位址選通訊號、一行位址選通訊號、一寫入致能 訊號、一時脈致能訊號(CKE)、一内部中斷電阻〇dt (〇n-die termination)訊號、一校準訊號（ZQ)以及一重置訊號（reset)。 相較於習知雙列接腳記憶體模組1〇〇，於本發明之一實施例 ® 中’記憶體模組300中每一組輸入訊號只會傳送至四個記憶體晶 片’以第2圖所示之習知雙列接腳記憶體模組1〇〇的量測結果為 例’記憶體模組300中之最後端的記憶體晶片310_卜310_8，其 輸入訊號的眼寬W為1004皮秒，相較於眼寬W為919皮秒的習 知雙列接腳記憶體模組100之記憶體晶片11〇_8 ’本發明確實可以 改善記憶體晶片的輸入訊號品質，並減少資料判讀錯誤的機會。 需注意的是，上述記憶體次模組以及複數組輸入接腳的數量 200939242 .縣本發明之-實施例，在實作上，記憶體次模組以及複數組輸 入接腳的數量可以依據設計者的考量^有所魏，而這些設計上 的變化均隸屬於本發明的範疇。 然而’記憶體模組300雖然可以改善記憶體晶片所接收到輸 入訊號的品質，但是卻需要兩組輸入訊號接腳，亦即記憶體模組 300總共需要58個輸入接腳，如此一來會因記憶體模組 〇 電路板（pnntedcircuitboard，PCB)的高度限制而增加PCB接線 (Layout)的困難度。因此，本發明另提供了一種記憶體模組之改良 後的架構以解決上述的問題。請參考第4圖，第4圖為本發明記 憶體模組之另一實施例的示意圖。如第4圖所示，記憶體模組4〇〇 包含有兩個記憶體次模組402J、402_2以及第一、二組輸入接腳 404J、404一2，其中記憶體次模組402J、402_2分別包含有複數 個記憶體晶片410_1〜410_4以及410_5〜410_8，其中每一個記憶體 0 晶片均包含有19個輸入接腳，且記憶體晶片410_1〜410_4以及記 憶體晶片410一5〜410_8係分別串聯，此外，第一、二組輸入接腳 404J、404—2分別包含有19個輸入接腳，且第一、二組輸入接腳 404_卜404一2分別連接至記憶體晶片410_4以及410_5。在本發 明中’該19個輸入接腳分別為六個列位址訊號接腳、五個行位址 訊號接腳、一列位址晶片選擇訊號接腳、一行位址晶片選擇訊號 接腳、兩個時脈訊號接腳、一内部中斷電阻〇DT (on-die termination)訊號接腳、一時脈致能訊號(CKE)接腳、一校準訊號 (ZQ)接腳以及一重置訊號（reset)接腳。 200939242 在記憶體模組400的操作上，如第4圖所示，第一組輸入訊 號係由一控制器420產生，並經由第一組輸入接腳4〇4j輸入至 記憶體晶片410—4中，之後再循序傳輸至記憶體晶片41〇_3、 410-2、410—1 ;同樣地’第二組輸入訊號亦是由控制器42〇產生， 並經由第二組輸入接腳404—2輸入至記憶體晶片41〇_5中，之後 再循序傳輸至記憶體晶片410—6、41〇__7、410_8 ,其_第一組輸入 〇訊號以及第二組輸入訊號係為相同的訊號，且第一、二組輸入訊 號分別包含有19筆輸入訊號，其中該19筆輸入訊號為六個列位 址訊號、五個行位址訊號、一列位址晶片選擇訊號、一行位址晶 片選擇sfl號、兩個時脈訊號、一内部中斷電阻〇DT ( 〇n_die termination)訊號、一時脈致能訊號(CK£)、一校準訊號（Zq)以 及一重置訊號（reset)。 _ 赫考第5 ϋ，第5圖為本發明實施例之六個顺Qw)位址訊 號的示意圖。如第5圖所示，每一個列位址訊號 (RowAdrO〜R0wAdr5 )的一列位址命令封包（池職 command package)的長度為一時脈訊號CLK之四個時脈週期， 且列位址命令封包包含有四個列輸人命令，因此，六個列位址訊 號之六個顺址命令封包總共包含有二十_列輸人命令，本實 施例中，該二十四烟輪人命令係包含有四筆纖庫位址的設定 資訊BAG〜BA3、十六筆賴齡址的設㈣訊A(KAi5以及四筆 記憶體控制命令的設定資訊CMD〇〜CMm，其中四筆記憶庫位址 11 200939242 . 的設定資訊ΒΑ0〜BA3係等於習知雙倍資料率同步動態隨機存取 記憶體架構下之記憶庫位址輸入訊號BA0〜BA3，且十六筆記慎體 位址的設定資訊A 0〜A15係等於習知雙倍資料率同步動態隨機存 取記憶體架構下之記憶體位址輸入訊號A0〜A15。此外，四筆記憶 體控制命令的設定資訊CMD0〜CMD3係經由解碼以產生複數個記 憶體控制命令中之一控制命令，其中該複數個記憶體控制命令可 包3有啟動(Active)、預充電(Precharge)、更新(Refresh)、模式暫存 Ο 設定（mode register set) MRS、自我更新（self-refresh entry，SRE)、 進入低功耗（power down entry)、長校準/短校準（ZQcaUbrati〇n long/ZQ calibration short, ZQCL/ZQCS)…等等。 請參考第6圖，第6圖為本發明實施例之五個行(c〇lumn)位址 訊號的示意圖。如第6圖所示，每一個行位址訊號 (ColAdrO〜ColAdr4)的一行位址命令封包（c〇iumnaddress ◎ command package)的長度為一時脈訊號Clk之四個時脈週期， 且行位址命令封包包含有四個行輸入命令，因此，五個行位址訊 號之五個列位址命令封包總共包含有二十個行輸入命令，該二十 個行輸入命令係包含有四筆記憶庫位址的設定資訊、十三筆記情 體位址的設定資訊、一寫入致能（WriteEnable，WE)輸入命令二 一自動預充電（Auto Pre-charge，AP)輸入命令以及一突發中斷4/ 大發長度 8 ( Burst Chop 4/Burst Length 8, BC4/BL8 )輸入命令，其 中四筆記憶庫位址的設定資訊BA0〜BA3係等於習知雙倍資料率 同步動態隨機存取記憶體架構下之記憶庫位址輸入訊號 12 200939242 ’ BAG〜BA3 ’且十三筆記憶體他的設定資訊AG〜A12鱗於習知 雙倍貝料率同步動態隨機存取記憶體架構下之記憶體位址輸入訊 號A0〜A12。 需注意的是，第5 ®所示之六個列位址訊號之六個列位址命 令封包所分別包含之輸入命令僅作為範例說明之用，在實作上， 第5圖所示之二十四個列輸入命令可任意對調；同理，第6圖所 〇 示之二十個行輸入命令亦可任意對調且不影響本發明之記憶體操 作。此外，上述列位址訊號（RowAdrO〜R〇wAdr5)、行位址訊號 (ColAdrO〜ColAdr4 )以及記憶庫位址的設定資訊（b〜b) 的數量亦僅作為範例說明之用，在實作上，若是要擴充記憶體的 容量，亦即增加記憶體位址的設定資訊或是增加記憶庫數量，則 列位址訊號可以為七個或以上且行位址訊號可以為六個或以上， 舉例而言，第一、二組輸入訊號接腳可以增加一列位址訊號接腳 以及一行位址訊號接腳’其中列位址訊號接腳係用來接收一列位 址訊號RowAdr6 ’且列位址訊號RowAdr6的列位址命令封包係包 含有兩筆記憶庫位址的設定資訊BA4、BA5，以及兩筆記憶體位 址的設定資訊A16、A17，而行位址祝就接腳係用來接收一行位址 訊號ColAdr5，且行位址訊號ColAdr5的行位址命令封包係包含有 兩筆記憶庫位址的設定資訊BA4、BA5，以及兩筆記憶體位址的 設定資訊A13、A14。 此外，列位址晶片選擇訊號係用來選擇使用一記憶體晶片來 13 200939242 •接收該複數_位址滅，且行紐W選擇訊號侧來選擇使 用-記憶體晶片來接收該複數個行位址訊號，當列位址晶片選擇 訊號CSR或行位址晶片選擇訊號csc致能時，該記憶體晶片才可 以接收列位址訊號或行位址訊號。 如上所述，記憶體模組4〇〇中每一組輸入接腳僅包含有丨今個 輸入接腳，因此兩組輸入接腳總共包含了 38個輸入訊號接腳，相 ❹較於第3圖所示之記憶體模組3〇〇的58個輸入接腳，記憶體模組 400可以在需要較少輸入接腳下，同時改善記憶體晶片的輸入訊號 品質，且可以在記憶體模組(DIMM)電路板的高度限制下，提升接 線(Layout)的容易度。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範 圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 D 【圖式簡單說明】 第1圖為習知雙列接腳記憶體模組的示意圖。 第2圖為第1圖所示之記憶體晶片之輸入訊號的眼圖。 第3圖為本發明記憶體模組之一實施例的示意圖。 第4圖為本發明記憶體模組之另一實施例的示意圖。 第5圖為本發明實施例之六個列位址訊號的示意圖。 第6圖為本發明實施例之五個行位址訊號的示意圖。 200939242 Ο 【主要元件符號說明】 100 雙列接腳記憶體模、: 110一1 〜110_8、310_1 〜310—8、 記憶體晶片 410_1〜410_8 300、400 記憶體模組 302 卜 302 2、402 卜 402 2 ·—· · —— — 記憶體次模組 304J、304一2、404J、404一2 輪入接腳 120、320、420 控制器 RowAdrO、RowAdrl、 列位址til號 RowAdr2 ' RowAdr3 ' RowAdr4、RowAdr5、 A0 〜A15 BA0-BA3 CMD0 〜CMD3 記憶體位址的設定 址的設定資^-7隱、體控制命；的設The memory sub-mode _ contains a number of memory (four) wafers and the number of memory crystals, the series and the multiplex array input pins are respectively connected to the plurality of memory sub-modules for receiving the same complex number Each input signal is used to transmit the plurality of input signals to the corresponding memory sub-module, and each set of input pins includes twenty-nine input pins The twenty-nine input pins are used to receive two pulse fields, sixteen memory input signals, three memory address input signals, one chip selection signal, and one column address strobe (r 〇waddress str〇be) signal, a column address strobe, a writeenable signal, an internal interrupt resistor (on_dieterminati〇n) signal, a clock enable signal (CKE), A calibration signal (zq) and a reset signal. According to another embodiment of the present invention, a memory module is disclosed. The memory 200939242 * the job group includes a plurality of memory sub-pools and a plurality of memory terminals. Each of the memory sub-modules includes a plurality of memory chips and the plurality of memory chips are connected in series, and The multi-array input is connected to the plurality of sub-modules for receiving the same plurality of input signals, and each set of input pins is used to transmit the plurality of input signals to the corresponding memory. In the sub-module, each set of input pins includes at least nineteen input pins, and the at least nineteen input pins are respectively configured to receive at least six column address signals and at least five row address signals. A row address chip selection tank, a row address wafer selection signal, two clock signals, an internal on-die termination signal, a clock enable signal (CKE), and a calibration signal (ZQ) And a reset signal (reset). In accordance with another embodiment of the present invention, a method of accessing a memory module is disclosed. The method includes: setting a plurality of memory sub-modules in the memory module, wherein each of the memory sub-modules includes a plurality of memory chips and the plurality of memory chips are connected in series; The memory module is configured to receive a plurality of input signals for receiving the same plurality of input signals; and transmitting the plurality of input signals to the corresponding memory sub-module, wherein the plurality of input signals include two Pulse signal, sixteen memory address input signals, three memory address input signals, one chip selection signal, one column address selection communication number, one row address selection communication number, one write enable § hole number, one The internal interrupt resistor 〇 DT (on-die termination) signal, a clock enable signal (CKE), a calibration signal (ZQ), and a reset signal (reset). According to another embodiment of the present invention, a method for accessing a memory module is disclosed. The financial method includes: setting a general (four) sub-module, wherein each of the memory sub-modules includes a plurality of memory crystals, wherein the plurality of memory chips are connected in series; and the memory module is disposed in the memory module a plurality of input pins for receiving the same plurality of inputs; and transmitting the plurality of input signals to the corresponding memory sub-module towel, wherein the plurality of input ports includes at least six column addresses Signal, at least five bribe addresses, - address wafer selection signal, one row address chip selection signal, two clock signals, an internal interrupt resistance signal, a one-time pulse enable signal (CKE), a calibration signal, and A reset signal. According to the memory module and the method for accessing the memory module provided by the present invention, the rise/fall time of the input signal and the establishment of the quasi-hold time can be improved, thereby improving the correctness of the data interpretation. [Embodiment] ❹ 4 Reference 帛 3 ® '帛 3 is a schematic diagram of an embodiment of the memory H module of the present invention. As shown in FIG. 3, the memory module includes (but is not limited to) two The memory sub-modules 302J, 302-2 and the first and second sets of input pins 304j, 304-2, wherein the a plurality of memory sub-modules respectively comprise a plurality of memory chips 310-1~31〇4 and 310 a 5 to 310-8, wherein each of the memory chips includes 29 input pins, and the memory chips 310_1 to 310_4 and the memory chips 310-5 to 310-8 are respectively connected in series, and further, the first and second The group input pins 3〇4” and 304-2 respectively include 29 input pins, and the first and second sets of input pins and 304-2 are respectively connected to the memory chips 31〇* and 31〇5. 200939242 In the operation of the memory surface and the group 300, as shown in FIG. 3, the first group of input signals are generated by the controller 320 and input to the memory chip 31 via the first group of input pins 3〇4_ 〇, then sequentially transferred to the memory chips 31〇3, 310-2, 310J; similarly, the 'second group of round-in signals are also generated by the controller 32〇 and input through the second set of input pins 3〇4_2 It is transferred to the memory chip 31〇5, and then sequentially transferred to the memory chips 310 to 6, 31()_7, 』. The first group of input signals and the second group of input signals are the same signal, and the first and second groups of input signals respectively contain 29 input signals, wherein the 29 input signals are two clock signals, sixteen Memory address input signal, three memory address input signals, one chip selection signal, one column address selection communication number, one row address selection communication number, one write enable signal, one clock enable signal (CKE), An internal interrupt resistor 〇dt (〇n-die termination) signal, a calibration signal (ZQ), and a reset signal (reset). Compared with the conventional dual-column memory module 1 , in the embodiment of the present invention®, each set of input signals in the memory module 300 is only transferred to four memory chips. The measurement result of the conventional dual-column memory module 1 shown in FIG. 2 is an example of the memory chip 310_b 310_8 at the last end of the memory module 300, and the eye width W of the input signal is 1004 picoseconds, the memory chip of the conventional dual-column memory module 100 is 919 picoseconds compared to the eye width W of 919 picoseconds. The present invention can improve the input signal quality of the memory chip and reduce The opportunity to misread the data. It should be noted that the number of the memory sub-module and the multi-array input pin is 200939242. In the implementation of the present invention, the number of the memory sub-module and the complex array input pin can be designed according to the design. The considerations of the person are somewhat different, and these design changes are all within the scope of the present invention. However, the memory module 300 can improve the quality of the input signal received by the memory chip, but requires two sets of input signal pins, that is, the memory module 300 requires a total of 58 input pins, so that The difficulty of increasing PCB layout due to the height limitation of the memory module p pnned circuit board (PCB). Accordingly, the present invention further provides an improved architecture of a memory module to solve the above problems. Please refer to FIG. 4, which is a schematic diagram of another embodiment of the memory module of the present invention. As shown in FIG. 4, the memory module 4A includes two memory sub-modules 402J, 402_2 and first and second sets of input pins 404J, 404-2, wherein the memory sub-modules 402J, 402_2 Each of the memory 0 wafers includes 19 input pins, and the memory chips 410_1 41010_4 and the memory wafer 410 5 to 410_8 are respectively included in the memory chips 410_1~410_4 and 410_5~410_8 respectively. In series, the first and second sets of input pins 404J and 404-2 respectively include 19 input pins, and the first and second sets of input pins 404_404-2 are respectively connected to the memory chips 410_4 and 410_5. . In the present invention, the 19 input pins are respectively six column address signal pins, five row address signal pins, one column address chip selection signal pin, one row address chip selection signal pin, two Clock signal pin, an internal interrupt resistor 〇 DT (on-die termination) signal pin, a clock enable signal (CKE) pin, a calibration signal (ZQ) pin, and a reset signal (reset) Pin. 200939242 In operation of the memory module 400, as shown in FIG. 4, the first set of input signals are generated by a controller 420 and input to the memory chip 410-4 via the first set of input pins 4〇4j. And then sequentially transferred to the memory chips 41〇_3, 410-2, 410-1; likewise the 'second group input signals are also generated by the controller 42〇 and via the second set of input pins 404- 2 is input to the memory chip 41〇_5, and then sequentially transferred to the memory chips 410-6, 41〇__7, 410_8, wherein the first group input signal and the second group input signal are the same signal The first and second sets of input signals respectively include 19 input signals, wherein the 19 input signals are six column address signals, five row address signals, one column address chip selection signal, and one row address chip selection. Sfl number, two clock signals, an internal interrupt resistor 〇 DT (〇n_die termination) signal, a clock enable signal (CK £), a calibration signal (Zq), and a reset signal (reset). _ 赫考第5ϋ, Fig. 5 is a schematic diagram of six cis Qw address signals according to an embodiment of the present invention. As shown in FIG. 5, the length of a column address command packet (RowAdrO~R0wAdr5) of each column address signal is a clock period of one clock signal CLK, and the column address command packet is included. There are four columns of input commands, so the six-address command packets of the six column address signals contain a total of twenty_column input commands. In this embodiment, the twenty-four-wheeler command includes There are four sets of fiber library address setting information BAG~BA3, sixteen pens rying site setting (four) news A (KAi5 and four pen memory control command setting information CMD〇~CMm, of which four memory memory address 11 200939242 . The setting information ΒΑ0~BA3 is equal to the memory address input signal BA0~BA3 under the double data rate synchronous dynamic random access memory architecture, and the setting information of the 16-note caution address A 0~A15 It is equal to the memory address input signals A0~A15 under the conventional double data rate synchronous dynamic random access memory architecture. In addition, the setting information CMD0~CMD3 of the four-stroke memory control command is decoded to generate a plurality of memories. control commands One of the control commands, wherein the plurality of memory control commands can include Active, Precharge, Refresh, Mode register set MRS, Self-update (self- Refresh entry, SRE), enter power down entry, long calibration/short calibration (ZQcaUbrati〇n long/ZQ calibration short, ZQCL/ZQCS), etc. Please refer to Figure 6, Figure 6 A schematic diagram of five row (c〇lumn) address signals of the embodiment of the invention. As shown in FIG. 6, a row address command packet of each row address signal (ColAdrO~ColAdr4) (c〇iumnaddress ◎ command package) The length of the line clock signal Clk is four clock cycles, and the row address command packet contains four line input commands. Therefore, the five column address command packets of the five row address signals contain a total of twenty lines. Input command, the twenty line input command system includes four sets of memory address setting information, thirteen note body address setting information, a write enable (WriteEnable, WE) input command, and two automatic pre-charging (Auto Pre-charge , AP) input command and a burst interrupt 4 / Burst Chop 4/Burst Length 8, BC4/BL8 input command, wherein the setting information of the four memory memory addresses BA0~BA3 is equal to the conventional double Data rate synchronous dynamic random access memory architecture memory address input signal 12 200939242 'BAG~BA3' and thirteen memory his setting information AG~A12 scale in the traditional double material rate synchronization dynamic random memory Take the memory address input signals A0~A12 under the memory architecture. It should be noted that the input commands included in the six column address command packets of the six column address signals shown in the 5th ® are only used as examples. In practice, the two shown in Figure 5 The fourteen column input commands can be arbitrarily reversed; similarly, the twenty line input commands shown in FIG. 6 can also be arbitrarily reversed without affecting the memory operation of the present invention. In addition, the number of column address signals (RowAdrO~R〇wAdr5), row address signals (ColAdrO~ColAdr4), and memory address setting information (b~b) are also used as examples for implementation. If the capacity of the memory is to be expanded, that is, the setting information of the memory address is increased or the number of memory banks is increased, the column address signal may be seven or more and the row address signal may be six or more. For example, In other words, the first and second sets of input signal pins can add a column of address signal pins and a row of address signal pins. The column address signals are used to receive a column address signal RowAdr6 'and the column address signal RowAdr6. The column address command packet includes setting information BA4, BA5 of two memory addresses, and setting information A16, A17 of two memory addresses, and the row address is used to receive a row address. The signal address command ColAdr5, and the row address command stream of the line address signal ColAdr5 includes setting information BA4, BA5 of two memory addresses, and setting information A13, A14 of two memory addresses. In addition, the column address wafer selection signal is used to select a memory chip to be used. 13 200939242 • The complex _ address is received, and the row W selects the signal side to select a memory chip to receive the plurality of row addresses. The signal chip can receive the column address signal or the row address signal when the row address chip selection signal CSR or the row address chip selection signal csc is enabled. As described above, each of the input pins of the memory module 4A includes only one input pin, so the two input pins comprise a total of 38 input signal pins, which is comparable to the third. The 58 input pins of the memory module 3〇〇 shown in the figure, the memory module 400 can improve the input signal quality of the memory chip while requiring less input pins, and can be in the memory module ( DIMM) The height of the board is limited to ease the layout. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should fall within the scope of the present invention. D [Simple Description of the Drawings] Figure 1 is a schematic diagram of a conventional dual-column pin memory module. Figure 2 is an eye diagram of the input signal of the memory chip shown in Figure 1. FIG. 3 is a schematic diagram of an embodiment of a memory module of the present invention. 4 is a schematic view of another embodiment of a memory module of the present invention. FIG. 5 is a schematic diagram of six column address signals according to an embodiment of the present invention. FIG. 6 is a schematic diagram of five row address signals according to an embodiment of the present invention. 200939242 Ο [Main component symbol description] 100 dual-column memory module, 110-1~110_8, 310_1~310-8, memory chip 410_1~410_8 300, 400 memory module 302 Bu 302 2,402 402 2 ··· · —— — Memory submodule 304J, 304-2, 404J, 404-2 Insulation pin 120, 320, 420 Controller RowAdrO, RowAdrl, column address til number RowAdr2 ' RowAdr3 ' RowAdr4 , RowAdr5, A0 ~ A15 BA0-BA3 CMD0 ~ CMD3 Memory address setting address setting ^-7 hidden, body control life;
ColAdrO、ColAdrl、ColAdr2、列位址訊號ColAdrO, ColAdrl, ColAdr2, column address signals
ColAdr3、ColAdr4 WE AP" 寫入致能輸入 自動預充電 BC4/BL8 突發中斷/突 15ColAdr3, ColAdr4 WE AP" Write Enable Input Auto Precharge BC4/BL8 Burst Interrupt/Sud 15