201119035 六、發明說明： 【發明所屬之技術領域】 本發明係種電晶體結構，特別是關於—種功率電晶體結構。 【先前技術】 雙載子連接電晶體(BJT)為現今最重要的半導體元件之一，這種元件雖 然可作為高功率元件及高速雜電路之用，但是在操作騎程之中，其最 的缺點為會雜大1的Μ。目前，金氧半場效電晶體(M⑽印的發 展，已經逐漸取代了雙載子電晶體之應用。由於其能節省電能的緣故，金 氧半場效電晶體已成為積體電路中最常被使用的半導體元件。 在習知製作在半導體基板上_Μ_τ元件结構俯視圖與結構剖視 圖"刀別如第1圓與第2圖所示。此關〇隨元件結構包含—n型重摻 雜基板1G ’赠驗極，在N型重摻雜基板上設有—n麵推雜蟲晶 層12在]^型輕摻雜蟲晶層14中係有一 p型換雜N型摻雜區 與P型重捧雜區18，其中p型摻雜區M與p型重摻雜區ls係鄰接且環 繞里摻雜1 16，此外在P型重摻雜區is中更設有-作為源極之N型重 推雜區20，A Xf期丨4Δ 产 雜區16之表面上係依序設有一閘極絕緣層22與一閘 極電極層24。s al » 另外’在N型重摻雜區20之頂面與N型重摻雜基板1〇之底 面77 H源極電極層26與-汲極電極層28。 在此種習知功率電晶體結構中，其電流可從源極電極層26流入，依序 、主過N型重摻_2Q p型重雜區n型摻雜區Ν财捧雜基板 最後從>及極電極層28流出，此電晶體之電流處理能力僅達數毫安培， 及極與源極之㈣轉電壓僅數百伏特 ，此原因在於汲極與源極之間的 201119035 阻隔性不夠’若電麟續加大’則耕溫度會_升高，且纽極與源極 就會產生崩潰效應，以導致元件損壞。 因此，本發明係在針對上述之困擾，提出一種功率電晶體結構，以有 效克服習知所產生的問題。 【發明内容】 本發明之主要目的，在於提供—種辨電晶體結構，其係在源極與汲 極間多增設絕緣層’以利職緣層之特性，提高電晶體耐高壓的程度進 而使電晶體可以有極高功率的輸出效果。 為達上述目的，本發明提供一種功率電晶體結構，包含一第一型重捧 雜基板其上依序6又有-第一型遙晶層、一具有一開孔之絕緣層，更者， 在第-型遙晶層上設有n结構，以填滿上述之開孔，在蟲晶結構中係 有-第-、第二型摻縫’第二赫雜係作為源極，且位於第一型換雜 區之周圍⑽晶結構中，以鄕_型摻職、絕緣層鄰接，此外，在遙晶 結構上設有-_結構，且其位於第—型摻雜區之表面。 兹為使胃審查委員對本發明之結構特徵及所達成之功效更有進一步 之瞭解與認識，謹佐喻紅實施姻及配合物之說明，說明如後： 【實施方式】 本發明主要在電晶體中多增設絕緣層來提高元件之源極與沒極之間的 •阻隔性’進而提高電晶體耐高壓的程度，以下介紹本發明之第—實施例， 月參閱第3圖及第4圖’第4圖為第3圖沿Β·Β’切線之剖視圖。201119035 VI. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to a transistor structure, and more particularly to a power transistor structure. [Prior Art] Bi-carrier-connected transistor (BJT) is one of the most important semiconductor components today. Although it can be used as a high-power component and high-speed hybrid circuit, its most disadvantage in operating the ride is It will be a big one. At present, the development of metal oxide half-field effect transistor (M(10) printing has gradually replaced the application of double-carrier transistor. Because of its energy saving, gold-oxygen half-field effect transistor has become the most commonly used in integrated circuits. The semiconductor device is conventionally fabricated on a semiconductor substrate. The top view and the structural cross-sectional view of the device structure are as shown in the first circle and the second figure. This relationship includes the n-type heavily doped substrate 1G with the element structure. 'Feed the pole, the n-type heavily doped crystal layer 12 is provided on the N-type heavily doped substrate. In the lightly doped layer 14, a p-type N-doped region and a P-type are provided. The doped region 18 is lifted, wherein the p-type doped region M is adjacent to the p-type heavily doped region ls and is doped around the inside of the cell 1 16; furthermore, in the P-type heavily doped region is - as the source N The type of the heavily doped region 20, the A Xf period 丨 4 Δ, the surface of the impurity-producing region 16 is sequentially provided with a gate insulating layer 22 and a gate electrode layer 24. s al » additionally 'in the N-type heavily doped region 20 The top surface and the bottom surface 77 of the N-type heavily doped substrate 1H source electrode layer 26 and the - drain electrode layer 28. In this conventional power transistor structure, the current Flowing from the source electrode layer 26, sequentially, the main over-N-type heavily doped _2Q p-type heavily hetero-region n-doped region Ν 捧 holding the substrate finally flows out from the > and the electrode layer 28, the current of the transistor The processing capacity is only a few milliamps, and the voltage between the pole and the source (four) is only a few hundred volts. This is because the 201119035 barrier between the drain and the source is not enough. Raise, and the neopolar and source will have a collapse effect to cause component damage. Therefore, the present invention is directed to the above-mentioned problems, and proposes a power transistor structure to effectively overcome the problems caused by the conventional invention. The main purpose of the present invention is to provide a discriminating transistor structure, which is characterized in that an insulating layer is added between the source and the drain to improve the resistance of the transistor to the high voltage. In order to achieve the above object, the present invention provides a power transistor structure comprising a first type of heavy-duty hetero-substrate having a first-layer-first crystal layer and a Opening the insulation layer, more, The first-type telecrystal layer is provided with an n-structure to fill the above-mentioned opening, and the first- and second-type fused seams are used as the source in the crystal structure, and are located at the first In the surrounding (10) crystal structure of the type-replacement region, the 鄕_ type is incorporated, the insulating layer is adjacent, and further, the -_ structure is provided on the telecrystal structure, and it is located on the surface of the first-type doped region. The Stomach Review Committee has further understanding and understanding of the structural features and the effects achieved by the present invention. It is intended to describe the implementation of the marriage and the complexes, and the description is as follows: [Embodiment] The present invention mainly adds more in the transistor. The insulating layer is used to improve the barrier property between the source and the gate of the device, thereby increasing the degree of high voltage resistance of the transistor. The first embodiment of the present invention will be described below. See Figure 3 and Figure 4 for the month. A cross-sectional view of the tangent line along the Β·Β' in Fig. 3.
由於功率電Ba體可分為Ν通道金氧半場效電晶體⑼MC)SFET)電晶體 或P-MOSFET電晶體’但不管是哪種電晶體，其構造皆相同，僅材質有N 201119035 型或P型之二種差異，以下先介紹Ν-MOSFET電晶體。 本發明之功率電晶體包含一 N型重摻雜矽基板32，並以此作為没極， 在N型重摻雜基板32上依序設有一 N型磊晶層34與一 N型輕摻雜遙晶層 36，一第一 N型摻雜區38與一第一 P型摻雜區40係位於N型輕摻雜磊晶 層36中’此二摻雜區38、4〇皆與N型磊晶層34鄰接，且第_p型捧雜區 40環繞並鄰接第一 N型摻雜區38。在n型輕摻雜磊晶層36上設有一具有 一開孔之絕緣層42，此開孔係位於第一 N型摻雜區38與第一 p型摻雜區 4〇上方’以露出第一 N型掺雜區38與第一 P型掺雜區40，且絕緣層42 係鄰接且覆蓋部分之P型#祕⑽，其巾職層A的厚歧計在〇 ( 〜5微米，-如結構44係設於第—N型摻雜區货、第—p型摻雜區 之表面，轉滿開孔，並覆編_部分之絕緣層42<>在如結構糾中， 係有一與第-N型摻雜區38同型之第二N型摻雜區你，其與第一 N型播 雜區38鄰接，且除N雜 46之物總構財，係有一斑 第- P型摻雜區40同型且作為源極之第二p型換雜區48，以與第一^ =雜40、第二N型摻_你、絕緣層42鄰接^在“結構糾上係設 t閘極結㈣，梅帛：㈣她％咖肅料 型摻雜區48。 閑極結構50包含一閉極絕 界重播雜閘極層54，閘極絕緣層 第 _44上’並位—摻_6之表面，且覆蓋部分 =二P型掺舰48’上述之重換雜閘極層％之材質為多祕，且與第一 轉雜區38同型’並設於閘極絕緣層52上。 電晶體更包含了-第一重捧雜區5 矜笫一重摻雜區58,第一重摻雜 r 201119035 區56係與第一Μ别放私r~ 摻雜區38同型，並位於第二Ρ型摻雜區48中，且 :Μ重^緣層& ^圍、職42鄰接’第：Ρ型播雜區48 部权第-重與第二_摻雜區46之間，閘極絕緣層52係覆蓋 °、 區56。另外第二重換雜區58係與第二Ρ型摻雜區48同 型’並位於第一重摻雜區56卜且與第二Ρ型摻雜區48之周圍、絕緣層 42 ° 56'58 *電曰曰體進仃運作時’作為雜電極之第二重摻雜區58接地’且閘極 施加正電壓，則電流可從汲極流人，並依序經過Ν型遙晶層％、第_ _ 摻雜區38、第：.Ν型_區46型摻雜區48，從電阻較小的第一 重摻雜區56流心由於絕緣層42的電姐隔伽可以提高電晶體耐高 壓的程度’使沒極與源極間_隔電壓達到數千伏特，且電晶體之電流處 理能力亦可達醜安培之^因此，此種電晶體可財數千瓦之極高功 率輸出，且可應用在電動鐵Η驅動裝置與炸彈發射器等各種需高功率的產 品電路上。 上述電晶體可同時缺少作為源極電極之第一重摻雜區56與第二重摻雜 區58，讓第二Ρ型掺雜區48覆蓋開孔周圍之部分的絕緣層42，如第$圖 及第6圖之第二實施例所示’則此電晶體仍可以有極高功率輸出。 至此N-MOSFET電晶體的結構介紹完畢，若要參閱p_m〇sfet電晶體 之第一、第二實施例的結構，僅需要將上述之Ν型重摻雜矽基板32、Ns 磊晶層34、N塑輕摻雜磊晶層36、第一、第二N型摻雜區38、46與第一、 第二P型摻雜區40、48分別以P型重摻雜矽基板、P型磊晶層、P型輕摻 201119035 雜蟲晶層、第-、第二P型摻雜區與第一、第二N型摻雜區代替即可 當電晶體進行運作時，_職加負„，電流可從源極流入，並 N-MOSFET之電流流動方向之相反方向行進，從錄流出。 、 以下繼續介紹本發明之第三實施例，請參閱第7圖及_。同樣地， 先介紹N-MOSFET電晶體。 第三實施例包含一 N型重摻雜石夕基板&，並以此作為沒極，在N型重 摻雜基板32上設有_ N _層34，—第—p型摻__於n型蠢 晶層34中，以環繞作為中喊晶區_之部分㈣奴晶層料。在n型 磊晶層34上設有-具有一開孔之絕緣層42，此開孔係位於第一 n型推雜 區38與第-P型摻雜區4G上方，以露出中_區域41與第—p型換雜 區40，且絕緣層42係鄰接且覆蓋部分之第一 p型播雜區4〇，其中絕緣層 42的厚度設計在結構44健於中綠晶區域4卜第 Ρ型摻雜區4G之表面’以填滿開孔，並覆蓋開孔周圍部分之絕緣層犯。 在遙晶結構44中，係有一與_蟲晶層％同型之第二ν型推雜區你，其 與中心遙晶區域4i鄰接，且在第二Ν型播雜區你之周圍的遙晶結構44中， 係有-與第-Ρ型摻雜區40同型且作為源極之第二？型推雜區仙，以與第 - Ρ型摻雜區40、第二Ν型捧雜區奶、絕緣層42鄰接。另在遙晶結構糾 上係設有-閘滅構5G ’並位於第二Ν型摻雜區46之表面，且覆蓋部分 之第二Ρ型摻雜區48。 閘極，卞構50包3 一閘極絕緣層52與一重推雜閉極層％，間極絕緣層 52係設於減结構44上’並位於第型摻㈣46之表面，且覆蓋部分 之第- Ρ ^摻雜區48 ’上述之重摻雜閘極層54之材質為多晶梦，且與ν 201119035 型蟲晶層34同型，並設於閉極絕緣層％上。 電曰體更匕3 了一第一重摻雜區56與一第二重摻雜區58’第-重摻雜 區56係與N型蟲晶層34同型，並位於第二p型摻雜區財，且第一重接 雜區56與閘極絕緣層52之、絕緣層42鄰接，第二p型摻雜區仙係 :第重摻雜區56與第型摻雜區40之間，閘極絕緣層2係覆蓋部 分之第-重摻雜區56。另外第二重摻雜區58係與第二p型推雜區48同型， 並位於第—重摻雜區56中，且與第二P型摻雜區48之周圍、絕緣層42鄰 接，又覆蓋開孔周圍之絕緣層42。此二重摻雜區56、58係皆作為源極電極 之用》 當電晶體進行運作時，作為源極電極之第二重摻雜區58接地，且閘極 施加正電壓，則電流可败極流人，並依序闕N龄晶層％、第二N型 摻雜區46、第二p型摻雜區48，從電阻較小的第一重摻雜區兄流出。由 於絕緣層42的紐峨仙，與第-實關姻，可以提高電晶體对高壓 的程度。 上述第三實施例之電晶體可同時缺少作為源極電極之第一重摻雜區兄 與第-重雜d 58，讓第二p型摻籠48覆蓋開孔關之部分的絕緣層 42 ’如第9圖及第1G囷之苐三實施例所示，則此電晶體仍可以有極高功率 輸出。至此刪OSFET電晶_結構介紹完畢若要參閱ρ·Μ_τ電晶 體之第三、第四實施例的結構，僅f要將上述之Ν型重摻卿基板Κ、Ν 型蠢晶層34、第二Ν型摻雜區你與第—、第二ρ型摻雜區4㈣分別以 Ρ至重摻雜珍基板、ρ型如層、第二ρ型雜區與第—、第二Ν型摻雜區 代替ρ可ffib s Uit行運作時，閘極職加負電壓，電流可從源極流 201119035 入’並沿與在N_MOSFET之電流流動方向之相反方向行進，從汲極流出。 上述各種實施例之單一電晶體結構j^OSFET/PMOSFET)，可 複製成多數而成為一整體之大功率元件，如此更能達到高電流兼高耐壓效 ： 果之目的。 : 综上所述，本發明利用絕緣層之特性，以提高電晶體耐高壓的程度， 進而使電晶體可以有極高功率的輸出效果，是一相當實用的發明。 以上所述者’僅為本發明—較佳實施例而已，並非用來限定本發明實 鲁*之範圍，故舉凡依本發明申請專利範圍所述之形狀、構造、特徵及精神 所為之均等變赠修飾，均應包括於本發日把_料概圍内。 【圖式簡單說明】 第1圖為先前技術之神電晶體結構俯視圖。 第2圖為第i圖之功率電晶體中沿A A，切線之結構剖視圖。 第3圖為本發明之第—實施例結構俯視圖。 第4圖為第3圖沿B-B’切線之結構剖視圖。 • 第5圖為本發明之第二實施例結構俯視圖。 第6圖為第5圖沿C-C，切線之結構剖視圖。 第7圖為本發明之第三實施例結構俯視圖。 : 第8圖為第7圖沿D-D’切線之結構剖視圖。 第9圖為本發明之第四實施例結構俯視圖。 第1〇圖為第9圖沿E-E，切線之結構剖視圖。 【主要元件符號說明】 12 N型輕摻雜磊晶層 1〇 N型重摻雜基板 201119035 14 P型摻雜區 16 N型摻雜區 18 P型重摻雜區 20 N型重掺雜區 22 閘極絕緣層 24 閘極電極層 26 源極電極層 28 汲極電極層 32 N型重摻雜矽基板 34 N型磊晶層 36 N型輕摻雜磊晶層 38 第一N型摻雜區 40 第一P型摻雜區 42 絕緣層 41 中心蟲晶區域 44 遙晶結構 46 第二N型摻雜區 48 第二P型摻雜區 50 閘極結構 52 閘極絕緣層 54 重摻雜閘極層 56第一重摻雜區 58第二重摻雜區Since the power electric Ba body can be divided into a Ν channel gold oxide half field effect transistor (9) MC) SFET) transistor or P-MOSFET transistor 'but no matter which kind of transistor, the structure is the same, only the material has N 201119035 type or P The two types of differences, the following describes the Ν-MOSFET transistor. The power transistor of the present invention comprises an N-type heavily doped germanium substrate 32, and as the electrodeless electrode, an N-type epitaxial layer 34 and an N-type light doping are sequentially disposed on the N-type heavily doped substrate 32. The remote crystal layer 36, a first N-type doped region 38 and a first P-type doped region 40 are located in the N-type lightly doped epitaxial layer 36. The two doped regions 38, 4 are all N-type. The epitaxial layer 34 is adjacent, and the _p-type doping region 40 surrounds and abuts the first N-type doping region 38. An insulating layer 42 having an opening is disposed on the n-type lightly doped epitaxial layer 36, and the opening is located above the first N-type doping region 38 and the first p-type doping region 4' to expose the first An N-type doped region 38 is adjacent to the first P-type doped region 40, and the insulating layer 42 is adjacent to and covers a portion of the P-type #10 (10), and the thickness of the towel layer A is at 〇 (~5 μm, - For example, the structure 44 is disposed on the surface of the first-N-type doped region and the first-p-type doped region, and is filled with the opening, and the insulating layer 42 of the partial portion is <> A second N-type doped region of the same type as the -N-type doped region 38, which is adjacent to the first N-type doping region 38, and has a speckle-P-type in addition to the N-form 46 The doped region 40 is of the same type and serves as a second p-type impurity-exchanging region 48 of the source, so as to be adjacent to the first ^=hetero 40, the second N-type doping, and the insulating layer 42. Pole (4), Mei Long: (4) her% of the doped type doping zone 48. The idler structure 50 comprises a closed-pole extremity replay of the miscellaneous gate layer 54, the gate insulating layer _44 on the 'co-location _ 6 surface, and cover part = two P-type ship 48' above the heavy-duty gate The material of the layer % is multi-secret and is the same type as the first turning impurity region 38 and is disposed on the gate insulating layer 52. The transistor further includes a first heavily doped region 5 矜笫 a heavily doped region 58, A heavily doped r 201119035 area 56 series is the same type as the first screening smear r~ doped region 38, and is located in the second erbium type doped region 48, and: Μ ^ ^ 层 layer & ^ circumference, job 42 Adjacent to the 'th: Ρ type doping area 48 between the weight-weight and the second _ doping area 46, the gate insulating layer 52 covers the °, the area 56. In addition, the second heavy-changing area 58 and the second The germanium-type doped region 48 is of the same type and is located in the first heavily doped region 56 and around the second germanium-doped region 48, and the insulating layer 42 ° 56'58 * when the electrical body is in operation The second heavily doped region 58 of the electrode is grounded and the gate is applied with a positive voltage, and the current can flow from the drain, and sequentially passes through the 遥-type crystal layer, the __-doped region 38, and the first: Type_Zone 46-doped region 48, from the first heavily doped region 56 with less resistance, the core of the insulating layer 42 can increase the degree of resistance of the transistor to high voltage 'between the pole and the source _ The voltage across the board reaches several thousand volts, and the transistor The flow processing capability can also reach ugly amps. Therefore, the transistor can be used for a very high power output of several kilowatts, and can be applied to various high-power product circuits such as an electric shovel driving device and a bomb transmitter. The transistor can simultaneously lack the first heavily doped region 56 and the second heavily doped region 58 as source electrodes, and the second germanium doped region 48 covers portions of the insulating layer 42 around the opening, as shown in FIG. And the second embodiment of Fig. 6 shows that the transistor can still have a very high power output. So far, the structure of the N-MOSFET transistor has been introduced, and the first and second implementations of the p_m〇sfet transistor are referred to. For the structure of the example, only the above-mentioned 重-type heavily doped yttrium substrate 32, Ns epitaxial layer 34, N-type lightly doped epitaxial layer 36, first and second N-type doped regions 38, 46 and the first The second P-type doping regions 40 and 48 are respectively heavily doped with a P-type germanium substrate, a P-type epitaxial layer, a P-type lightly doped 201119035 impurity crystal layer, a first- and a second P-type doped region, and a first The second N-type doping region can be replaced when the transistor is operated, the _ job plus negative „, the current can flow from the source, and the power of the N-MOSFET Opposite direction of the flow direction of travel, the outflow from the record. The third embodiment of the present invention will be further described below, please refer to FIG. 7 and _. Similarly, the N-MOSFET transistor will be introduced first. The third embodiment comprises an N-type heavily doped slab substrate & and as a finite electrode, _N _ layer 34 is provided on the N-type heavily doped substrate 32, and the -p-type __ In the n-type stray layer 34, a portion of the n-type crystal layer is surrounded by (4) a slave layer. An insulating layer 42 having an opening is provided on the n-type epitaxial layer 34, and the opening is located above the first n-type doping region 38 and the first-P-type doping region 4G to expose the middle region 41 And the first p-type impurity-changing region 40, and the insulating layer 42 is adjacent to and covers a portion of the first p-type hybrid region 4, wherein the thickness of the insulating layer 42 is designed to be stronger in the medium-green region 4 The surface of the doped region 4G is filled with an opening and covers the insulating layer around the opening. In the remote crystal structure 44, there is a second ν-type erbium region of the same type as the _ worm layer, which is adjacent to the central smectic region 4i, and the remote crystal around you in the second sputum type impurity region The structure 44 is - is the same type as the first - germanium type doped region 40 and serves as the second source. The type of doping region is adjacent to the first - doped type doped region 40, the second doped type doped region milk, and the insulating layer 42. Further, the remote crystal structure is provided with a gate-offer 5G' and located on the surface of the second germanium-type doped region 46, and covers a portion of the second germanium-type doped region 48. The gate electrode, the structure 50 package 3, a gate insulating layer 52 and a heavily doped gate layer %, the interlayer insulating layer 52 is disposed on the subtracting structure 44 and located on the surface of the first type doping (four) 46, and covering the portion - Ρ ^ Doped region 48' The above-mentioned heavily doped gate layer 54 is made of polycrystalline dream and is of the same type as the ν 201119035 type worm layer 34 and is provided on the closed-pole insulating layer %. The first body heavily doped region 56 and the second heavily doped region 58' the first heavily doped region 56 are of the same type as the N type silicon layer 34 and are located in the second p type doping. The first re-bonding region 56 is adjacent to the insulating layer 42 of the gate insulating layer 52, and the second p-doping region is between the first heavily doped region 56 and the first doped region 40. The gate insulating layer 2 covers a portion of the first heavily doped region 56. In addition, the second heavily doped region 58 is of the same type as the second p-type doped region 48 and is located in the first heavily doped region 56, and is adjacent to the periphery of the second P-type doped region 48 and adjacent to the insulating layer 42. Covering the insulating layer 42 around the opening. The double-doped regions 56 and 58 are both used as source electrodes. When the transistor operates, the second heavily doped region 58 as the source electrode is grounded, and the gate applies a positive voltage, and the current is defeated. The electrode is flowed, and the N-type crystal layer %, the second N-type doping region 46, and the second p-type doping region 48 are sequentially discharged from the first heavily doped region brother having a small resistance. Due to the insulation of the insulating layer 42, it is possible to increase the degree of high voltage of the transistor. The transistor of the third embodiment described above may simultaneously lack the first heavily doped region brother as the source electrode and the first-fold impurity d 58, the second p-type doping cage 48 covering the portion of the insulating layer 42 ' As shown in the third embodiment of FIG. 9 and FIG. 1G, the transistor can still have a very high power output. So far, the OSFET transistor has been deleted. _Structure is introduced. To refer to the structure of the third and fourth embodiments of the ρ·Μ_τ transistor, only the above-mentioned Ν-type heavily doped Κ, Ν-type opaque layer 34, The doped-type doping region and the first and second p-doped regions 4 (4) are doped with a heavily doped substrate, a p-type layer, a second p-type hetero region, and a first and second doped region, respectively. When the region is operated instead of the ρ ffib s Uit row, the gate is applied with a negative voltage, and the current can flow from the source current 201119035 and travel in the opposite direction to the direction of current flow in the N_MOSFET, flowing from the drain. The single transistor structure j^OSFET/PMOSFET of the above various embodiments can be copied into a plurality of high-power components as a whole, so that the high current and high voltage resistance can be achieved. In summary, the present invention utilizes the characteristics of the insulating layer to increase the degree of resistance of the transistor to high voltage, thereby enabling the transistor to have an extremely high power output effect, which is a quite practical invention. The above description is only for the purpose of the present invention, and is not intended to limit the scope of the present invention. Therefore, the shapes, structures, features, and spirits described in the claims of the present invention are equally variable. Gifts should be included in the information on the date of this issue. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a plan view of a prior art crystal structure. Fig. 2 is a cross-sectional view showing the structure along the line A A in the power transistor of Fig. i. Figure 3 is a plan view showing the structure of the first embodiment of the present invention. Fig. 4 is a cross-sectional view showing the structure taken along line B-B' of Fig. 3; • Fig. 5 is a plan view showing the structure of a second embodiment of the present invention. Fig. 6 is a cross-sectional view showing the structure of a tangent line taken along line C-C in Fig. 5. Figure 7 is a plan view showing the structure of a third embodiment of the present invention. Fig. 8 is a cross-sectional view showing the structure taken along line D-D' of Fig. 7. Figure 9 is a plan view showing the structure of a fourth embodiment of the present invention. Figure 1 is a cross-sectional view of the tangential line taken along line E-E of Figure 9. [Main component symbol description] 12 N-type lightly doped epitaxial layer 1〇N-type heavily doped substrate 201119035 14 P-type doped region 16 N-type doped region 18 P-type heavily doped region 20 N-type heavily doped region 22 gate insulating layer 24 gate electrode layer 26 source electrode layer 28 drain electrode layer 32 N-type heavily doped germanium substrate 34 N-type epitaxial layer 36 N-type lightly doped epitaxial layer 38 first N-type doping Region 40 First P-doped region 42 Insulating layer 41 Central striated region 44 Telecrystalline structure 46 Second N-type doped region 48 Second P-type doped region 50 Gate structure 52 Gate insulating layer 54 Heavy doping Gate layer 56 first heavily doped region 58 second heavily doped region