TW201213571A - Preparation method of on-chip passive component - Google Patents

Preparation method of on-chip passive component Download PDF

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Publication number
TW201213571A
TW201213571A TW99131661A TW99131661A TW201213571A TW 201213571 A TW201213571 A TW 201213571A TW 99131661 A TW99131661 A TW 99131661A TW 99131661 A TW99131661 A TW 99131661A TW 201213571 A TW201213571 A TW 201213571A
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TW
Taiwan
Prior art keywords
masking film
film
wafer
conductive
passive component
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TW99131661A
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Chinese (zh)
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TWI391512B (en
Inventor
Tian-Jing Huang
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Beer Corp
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Priority to TW99131661A priority Critical patent/TW201213571A/en
Priority to CN2011101475292A priority patent/CN102412178A/en
Publication of TW201213571A publication Critical patent/TW201213571A/en
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Publication of TWI391512B publication Critical patent/TWI391512B/zh

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  • Powder Metallurgy (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)

Abstract

The present invention relates to a preparation method of an on-chip passive component, including the following process: using vacuum sputtering to form a conductive electrode of the on-chip passive component, covering spalling lines with a removable masking film before vacuum sputtering, and finally rapidly removing them after vacuum sputtering. Therefore, this invention has the advantages of reducing cost, promoting production rate and decreasing the thickness of products.

Description

201213571 六、發明說明: 【發明所屬之技術領域】 本發明係有關一種被動元件的製程,特別是關於一種晶片 被動元件的製程。 【先前技術】 近年來,由於表面黏著技^術的普及應用,促使被動元件加 # 速晶片化。晶片被動元件可為具有單一功能的裝置,例如電 阻、電谷、電感’亦可為複合式元件的裝置,例如阻容網路、 排阻等等。基於成本的考量,晶片被動元件的製造一向採用厚 膜製程,但目前也逐漸看到薄膜製程應用在晶片被動元件的製 造,而且越來越普遍。 厚膜製程係採用網印技術,藉刮刀擠壓的方式將膠體印刷 在晶片基板上,再經過乾燥及燒結等製程,其產品線寬在 ΙΟΟμπι以上,其厚度亦達5〜1〇μιη左右,在尺寸的微縮與產品 • 穩定度的提升有技術上的極限與困難度。而薄膜製程採用微影 蚀刻技術’在晶片基板上描繪電路,線寬可控制在1〇μιη以下, 產mi厚度可控制在(J O〗〜1μηι的範圍内。相較於厚膜製程,薄 膜製程對於產品體積微縮以及提升精密度的設計有更多可能 性。然而,即使晶片被動元件的主體結構使用薄臈製程製作, 卻依舊使用銀漿等貴金屬厚膜印刷的方式製作晶片被動元件 的導電電極,造成成本較高’且晶片被動元件的厚度較厚。 因此,一種降低成本、提升生產速率以及減少產品厚度的 晶片被動元件的製程,乃為所冀。 201213571 【發明内容】 本發明的目的之―,在於提出-種晶片被動元件的製程。 的製目的之―’在於提出—種低成本的晶片被動元件 元件=的目的之―’在於提出—種高生產速率的晶片被動 的製i發明的目的之―’在於提出—種低厚度的晶片被動元件 2據本發明’一種晶片被動元件的製程包含在晶片基板的 ^向_線上駿第—祕膜,崎真空賴電氣特性 覆蓋第二遮蔽膜且露出導電區,接著真空蘭導電層, ^及> 月除該第-鑛膜及該第二遮蔽膜。 ^佳者’該導電層係以較低成本的導電材料為乾材,以降 厚:而=導電層係以真空濺鍍形成,因此可以減少產品 而要乾燥及燒結等步驟,因此提升生產速率。 【實施方式】 的上在本發明的晶片被動元件的製程中,各主要步驟 視圖及相圖。在製作晶片被動元件時, 準備晶片基板10,' γ方有 方向的剝裂線12及多條 y方向的㈣線14,以定義出各單 夕惊 於製造一個W被較件。晶片、置;母卿元將用 石夕魏化叙,h *板0可以疋陶究、玻璃、 其材料須適於後續的真空濺_境。如圖2所 201213571201213571 VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to a process for a passive component, and more particularly to a process for a passive component of a wafer. [Prior Art] In recent years, due to the popular application of surface adhesion technology, passive components have been promoted to be wafer-driven. The passive component of the wafer can be a device having a single function, such as a resistor, a valley, an inductor, or a device of a composite component, such as a RC network, an exclusion resistor, and the like. Based on cost considerations, the fabrication of passive components for wafers has always been a thick film process, but it is now increasingly seen that thin film processes are used in the fabrication of passive components for wafers and are becoming more common. The thick film process adopts screen printing technology, and the colloid is printed on the wafer substrate by means of blade extrusion, and then dried and sintered, and the product line width is above ΙΟΟμπι, and the thickness thereof is also about 5~1 〇μιη. There are technical limits and difficulties in the size reduction and product stability. The thin film process uses a micro-etching technique to draw a circuit on a wafer substrate. The line width can be controlled below 1 〇μηη, and the thickness of the produced mi can be controlled within the range of (JO)~1μηι. Compared with the thick film process, the thin film process There are more possibilities for product volume miniaturization and improved precision design. However, even if the main structure of the passive component of the wafer is fabricated using a thin tantalum process, the conductive electrode of the passive component of the wafer is still printed by using a thick film of precious metal such as silver paste. Therefore, the cost is higher and the thickness of the passive component of the wafer is thicker. Therefore, a process for reducing the cost of the wafer, increasing the production rate, and reducing the thickness of the product is a process of the passive component of the wafer. 201213571 SUMMARY OF THE INVENTION ―, is to propose a process for the passive components of wafers. The purpose of the invention is to propose a low-cost passive component of the wafer = the purpose of the invention is to propose a high-production rate wafer passive system. The purpose of the 'is to propose a low-thickness wafer passive component 2 according to the invention' The process of the device is included in the ^ _ line of the wafer substrate - the secret film, the vacuum insulation properties cover the second mask film and expose the conductive region, and then the vacuum blue conductive layer, ^ and > monthly removal of the first - mineral film And the second masking film. The best conductive layer is made of a lower cost conductive material to reduce the thickness: and the conductive layer is formed by vacuum sputtering, thereby reducing the product and drying and sintering. Steps, thereby increasing the production rate. [Embodiment] In the process of the passive component of the wafer of the present invention, each main step view and phase diagram. When the passive component of the wafer is fabricated, the wafer substrate 10 is prepared, and the γ-direction is oriented. Stripping line 12 and a number of y-direction (four) lines 14 to define each one-day surprise to create a W-like piece. The wafer, set; mother Qing Yuan will use Shi Xiwei Huaxu, h * board 0 can be smashed , glass, and its materials shall be suitable for subsequent vacuum splashing. As shown in Figure 2, 201213571

不,以曝光或印刷的方式在晶絲板1G的_χ方向的剝裂 線12上覆蓋可清除式的遮蔽膜16。較佳者,遮賊μ的材 料為光阻、玻璃油墨或加熱後易於溶射清洗之環氧樹脂。缺 後如圖3所示,真空爽職氣特性層18。在此真空频的^ 驟中,根據晶片被動元件的功能及結構設計,施行一道或多道 蓋印與真空猶乾材以形成電氣特性層18,這是晶片被動^ 件的主體結構,且已經是熟知眺術。在完成晶服動元件的 主體結構後’如圖4所示,以曝光或印刷的方式覆蓋可清除式 的遮蔽膜20,在丫方向的㈣線14的_露出預設的導電區 22,然後如圖5所示,真空麵導電層24。較佳者,形成導 電層24的乾材選用包含鋼基合金等具良好導電性的材料。較 =者V電層24的厚度在015〜1μηι之間。接著如圖6所示, 清=遮_ 16及2G ’其上的電氣特性層18及導電層24亦一 月除較佳者’採用超音波振盤清洗或以毛刷或海棉於水或 〉谷劑之中刷洗遮蔽膜16及2〇。在清除遮蔽膜16及20後,導 ,層^成為分離的區塊,形成晶片被動元件的導電電極。接 f 、驾♦之封裝方式對晶片基板10進行剝條、錢侧導、折 粒、水電鍍...等步驟,以完成晶片被動元件的製作。 如以上實施例所述,本發明使用銅基合金等材料為乾材, 外空減Γ形成導電層24,與習知技術相比,除了降低成本以 也月b省去厚膜印刷的乾燥及燒結等步驟,並且能減少導電 電極的厚度’進而縮小晶片被動元件的產品厚度。 【圖式簡單說明】 201213571 圖1〜6係晶片被動元件製程的各主要步驟的示意圖。 【主要元件符號說明】 10 晶片基板 12 剝裂線 14 剝裂線 16 遮蔽膜No, the erasable masking film 16 is covered on the peeling line 12 in the _ χ direction of the crystal plate 1G by exposure or printing. Preferably, the material of the thief μ is a photoresist, a glass ink or an epoxy resin which is easily spray-cleaned after heating. After the absence, as shown in Fig. 3, the vacuum is characterized by a layer 18. In the vacuum frequency process, one or more stamps and vacuum materials are applied to form the electrical property layer 18 according to the function and structural design of the passive components of the wafer, which is the main structure of the passive component of the wafer, and Is familiar with 眺. After completing the main structure of the crystal device, as shown in FIG. 4, the erasable shielding film 20 is covered by exposure or printing, and the predetermined conductive region 22 is exposed in the (four) line 14 of the 丫 direction, and then As shown in FIG. 5, the vacuum surface conductive layer 24 is provided. Preferably, the dry material forming the conductive layer 24 is made of a material having good electrical conductivity such as a steel-based alloy. The thickness of the V-electrode layer 24 is between 015 and 1 μm. Then, as shown in FIG. 6, the electrical property layer 18 and the conductive layer 24 on the screen are also cleaned by an ultrasonic disk or brushed or sponged in water or 〉 Wash the masking film 16 and 2〇 in the granules. After the masking films 16 and 20 are removed, the vias become separate blocks forming the conductive electrodes of the passive components of the wafer. The wafer substrate 10 is subjected to stripping, money side guiding, dicing, water plating, etc., to complete the fabrication of passive components of the wafer. As described in the above embodiments, the present invention uses a copper-based alloy or the like as a dry material, and the outer space is reduced to form a conductive layer 24. Compared with the prior art, in addition to reducing the cost, the thick film printing is dried and removed. The steps of sintering and the like, and the thickness of the conductive electrode can be reduced, thereby reducing the product thickness of the passive component of the wafer. [Simple description of the drawing] 201213571 Fig. 1 to 6 are schematic diagrams showing the main steps of the passive component process of the wafer. [Main component symbol description] 10 wafer substrate 12 stripping line 14 stripping line 16 masking film

18 電氣特性層 20 遮蔽膜 22 導電區 24 導電層18 Electrical property layer 20 Masking film 22 Conductive zone 24 Conductive layer

Claims (1)

201213571 七 申請專利範圍: 1. -種晶片被動元件的製程,包括下列步驟: 第-方__二方向剝裂線的晶片基板; 覆盍第一遮蔽膜在該第一方向剝裂線上; 真空;賤鑛電氣特性層; 覆盘第一遮蔽膜且露出導電區; 真空濺鍍導電層;以及 清除該第-遮蔽膜及該第二遮蔽膜。 程,其中該覆蓋第-遮蔽膜在該第-方向剝裂 墨或加熱後易於溶劑中清洗之環氧ς膜的材料為光阻、玻璃油 4. 如請求項1之製程,農φ 印與真线練材/、 频魏紐層的步驟包含蓋 6 5. 如請求項1之製程,复中 物方式形成該第二膜且露出導電區的步 .如明求項1之製程,发 一 墨或加熱後易於溶劑# ^遮蔽膜的材料為光阻、玻璃油 7.如請求項心 合金為乾材的真空濺錢、。/ i濺鍍導電層的步驟包含以銅基 9 : 項1之製程’其中該導電層的厚度在0 15 9.如凊求項1之製程 &在⑽〜1帅之間。 側。. ^树電區位於該第二方向制裂線之兩 如請求項1 ♦,射棘_—卿蝴二遮蔽膜 10. 7 201213571 的步驟包含以超音波振盪清洗或以毛刷或海棉於水或溶劑之中 刷洗該第一遮蔽膜及該第二遮蔽膜。201213571 Seven patent application scope: 1. The process of passive components of a wafer, comprising the following steps: a wafer substrate of a first-side __ two-direction stripping line; covering the first masking film in the first direction stripping line; vacuum a conductive property layer; covering the first masking film and exposing the conductive region; vacuum sputtering the conductive layer; and removing the first-masking film and the second masking film. The material of the epoxy ruthenium film covering the first-masking film in which the first-direction peeling ink or the solvent is easily washed in the solvent is a photoresist or a glass oil. 4. The process of claim 1 is The step of the true line material /, the frequency Wei layer includes the cover 6 5. According to the process of claim 1, the method of forming the second film and exposing the conductive area by the method of the intermediate medium, such as the process of the item 1 Easily solvent after ink or heating # ^ The material of the masking film is photoresist, glass oil 7. If the request is made of a heart-shaped alloy, it is a vacuum splash. / i The step of sputtering the conductive layer comprises a process of copper base 9: item 1 wherein the thickness of the conductive layer is 0 15 9. The process of claim 1 is between (10) and 1 handsome. side. The tree electrical area is located in the second direction of the splitting line as claimed in claim 1 ♦, the shooting _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The first masking film and the second masking film are brushed in water or solvent.
TW99131661A 2010-09-17 2010-09-17 Preparation method of on-chip passive component TW201213571A (en)

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TW99131661A TW201213571A (en) 2010-09-17 2010-09-17 Preparation method of on-chip passive component
CN2011101475292A CN102412178A (en) 2010-09-17 2011-06-02 Manufacturing process of chip passive element

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TW99131661A TW201213571A (en) 2010-09-17 2010-09-17 Preparation method of on-chip passive component

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TWI391512B TWI391512B (en) 2013-04-01

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TWI683383B (en) * 2018-10-23 2020-01-21 萬潤科技股份有限公司 Pushing method and mechanism of wafer stripping process and equipment using the mechanism

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