TW201214627A - Methods of forming through wafer interconnects in semiconductor structures using sacrificial material and semiconductor structures formes by such methods - Google Patents

Abstract

Methods of fabricating semiconductor structures include providing a sacrificial material within a via recess, forming a first portion of a through wafer interconnect in the semiconductor structure, and replacing the sacrificial material with conductive material to form a second portion of the through wafer interconnect. Semiconductor structures are formed by such methods. For example, a semiconductor structure may include a sacrificial material within a via recess, and a first portion of a through wafer interconnect that is aligned with the via recess. Semiconductor structures include through wafer interconnects comprising two or more portions having a boundary therebetween.

Description

201214627 VI. Description of the Invention: [Technical Field of the Invention] In general, the present invention relates to a method of forming a cast structure including a crystal-transparent joint, and a semiconductor structure formed by applying the same. [Prior Art] Semiconductor construction package secrets and fines (suppressed (four) Wei set) and is used in the production of semiconductor devices, such as electronic records, memory devices, optoelectronic devices (such as light-emitting diodes) _, laser diode 'solar battery, etc.', rear electromechanical device and nano-electric green material. In the scale-turn structure, it is often necessary or best to - semiconductor construction in electrical and / or occupation Age to another device or construction (10) such as another semiconductor construction. This material semiconductor structure and the other structure or structure are often referred to as the 3D + integration process. The three-dimensional spatial accumulation of two or more semiconductor constructions can bring many benefits to microelectronic applications. In other words, the three-dimensional space of microelectronic components can improve electrical performance and power consumption while reducing the bottom area of the device. See, for example, {The Handb〇〇k of 3D Integration, edited by P. Ga et al. (Wiley-VCH Publishing, 2008). The second spatial accumulation of the semiconductor structure can be performed in the following manner, or a combination of the modes: attaching the rotating body grains to an additional body grain (10) 卩 grain to grain (D2D)) 'attach the semiconductor die to one or more semiconductor crystals (ie, die to day (D2W)) and attach the semiconductor wafer to one or more additional semiconductor wafers (also Wafer to wafer (W2W). 201214627 Typically, individual semiconductor dies or wafers may be relatively thin and processed more difficult to process the die or wafer. Thus, the "carrier" grains or crystals can be placed onto the actual die or wafer. The actual die or wafer contains active and passive 7L devices of the semiconductor device in operation. The carrier crystals (four) crystal rides contain any active or passive components of the desired slave. The material carrier crystal grain wafer is referred to as a "heavy substrate" in this document. The carrier substrates increase the overall thickness of the dies or wafers and assist the processing device in processing the wafers, and the surface coatings are subsequently applied to the grains or crystals. Active and / or passive components of the gj towel. It is known to establish a new connection between the active element in the "crystal-transparent connection" or "the semiconductor structure" and the additional conductivity characteristic of the semiconductor structure. The through-connection is a through-semiconductor 3 = a portion of the conductive via. [Summary of the invention] The method includes a method of fabricating a semiconductor structure. The sacrificial material can be provided at least partially through the semiconductor structure. Within the through-hole groove, at least one of the inter-wafer-transparent joints is closely related to the axis. (4) - the first portion of the gap-through connection between the pastes may be inconsistent with the at least one through-hole. The sacrificial material in the through-hole recesses may be exchanged for a conductive material to form a second portion of the at least one inter-wafer via connection, which is electrically connected to the at least one of the at least one transparent connection Sexual contact. The invention also relates to the material of the object. In this method, a material is provided in at least one through hole groove N, and the at least one through hole groove extends into a surface of a semiconductor structure. - Casting material touch can be provided in the conductor structure On the silk surface, and at least 4 201214627 7 material is removed. Μ - is formed from the first part, and penetrates the layer of semiconductor material. The _ structure can be thinned from the opposite side of the semiconductor material layer. The sacrificial material The at least one via hole may be removed from the semiconductor structure, and the at least one of the at least one through-contact portion may be exposed in the through-groove; the conductive material may be provided in the through-hole recess The second portion of the in-slot is formed to form the at least one inter-wafer through-connection. In other embodiments, the present invention includes a semiconductor structure that is disclosed by the present invention. For example, in some implementations In the example, the semiconductor structure includes at least one of the sacrificial materials in the through-hole recesses. The at least one of the semiconductor structures has a surface through which the semiconductor structure is partially disposed. (10) at least one device configuration comprising at least a portion of a cast material disposed on a surface of the conductor structure. At least a portion of the crystal-through connection is disposed through the surface of the semiconductor structure Half Face, job remuneration Lai Xiao H-shirt less than one through-hole groove alignment. In the fine section, this hair day · half (10) view, the material conductor construction package: moving surface, - back surface, at least one transistor Between the semiconductor structure between the pair and the at least one round-door read, / poor record, yj@aaB1 open-through connection from the active surface - at least partially through the semiconductor structure. A wafer print, a wide 3 - part 'the second part, and - an identifiable boundary between the 1 - part - the micro-structure and one of the second part of the micro-structure. ' Modes The following description provides specific details, examples and implementations provide detailed descriptions of materials and miscellaneous items, such as the invention of the county. However, 'in this judgment, the singer has the usual 201214627 knowledge, all know, do not adopt Embodiments of the invention may also be practiced in the specific details or in combination with conventional fabrication techniques. Moreover, the statements provided herein do not constitute a complete process for fabricating a semiconductor device or system. Only process behaviors and configurations necessary to understand embodiments of the invention are detailed herein. The materials described herein can be formed using any suitable technique (eg, deposition or growth), and any suitable technique includes, but is not limited to, spin coating, coating (coating), cloth Bridgeman processes and Cz〇chralski pr〇cesses, chemical vapor deposition ("CVD"), plasma enhanced chemical vapor deposition ("pECVD"), atomic layer deposition (ALD), electricity Augmented atomic layer deposition (peald) or physical vapor deposition ("pvd"). While the materials described herein and formed are layered, the materials are not limited to lamellar, but may be formed into other three dimensional spatial configurations. As used herein, terms such as "horizontal" and "vertical" define the relative position of a component or structure relative to a major plane or surface of a semiconductor structure (eg, wafer, die, substrate, etc.), no, the semiconductor The orientation of the construction, and the terms are the orthogonality (orthog(10)! dimensi〇ns) in terms of the orientation of the described and constructed. As used herein, "vertical" refers to and includes a dimension that is substantially perpendicular to the major surface of the semiconductor structure, and "horizontal" - the word refers to the substantially flat surface of the semi-conductive structure. degree. In this context, "transformation" refers to any configuration of a semiconductor device. The semi-conducting structure includes a combination of a stacking method and a combination of a die and a wafer and/or a wafer. The semiconductor structure also includes a fully fabricated semiconductor device and an intermediate structure formed during fabrication of the semiconductor device.

The dry conductor structure may comprise a conductive material, a conductive Lei wire and/or a non-conductive material. T 201214627 The term "processed semiconductor construction" is used herein to refer to and encompass any semiconductor construction that includes one or more devices constructed to $f%. The processed semiconductor is constructed as a semiconductor constellation and all of the semiconductor structures are semiconductor structures. As used herein, the term 'bonded semiconductor construction' refers to and includes any possession of two or more assets that are attached to the property. The lion has been replaced by a material-guided sub-set and all #-bonded semiconductor structures are of semiconductor construction. In addition, those who have bonded semiconductor structures or three processed semiconductor structures also belong to processed semiconductor structures. As used herein, the term "device construction" means and includes any knives of a processed semiconductor construction that contain, or define, at least a portion of an active or passive component that is to be formed. On the semiconductor structure or in the case of a semi-guided weave, the device consists of four active and passive components of a three-sided circuit, such as a transistor, a brain, a capacitor, a resistor, a conductive wire, a conductive via, and Conductive contact pads. As used herein, the term "through-wafer via" or "TWI" refers to and includes any conductive via that passes through at least a portion of a first semiconductor structure for crossing the first semiconductor. The interface between the construction and the second rotor structure provides a constructive and/or electrical interconnection between the first semiconductor structure and the second semiconductor structure. In the technical towel of the art, the inter-wafer transparent connection is also private, such as "矽 sil sil sil sil sil sil via via via via 」 」 」 」 」 」 」 」 」 」 」 」 」 」 」 」 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及"through wafer vias" or "TWV". The TWI typically passes through the semiconductor structure in a direction substantially perpendicular to one of the substantially planar major surfaces in a semiconductor structure (i.e., parallel to one of the "Z" axes). As used herein, the term "active surface" is used in the context of a processed semiconductor construction to refer to and include one of the processed semiconductor constructions that exposes the major surface 'which has been processed or will be processed by 201214627' to enable - A Swim (4) can be formed in and/or on the main surface of the rotator configuration. As used herein, the term "back surface" - used in connection with a processed semiconductor construction, refers to and includes one of the processed semiconductor structures that exposes a major surface that is the opposite of the active surface of the processed semiconductor. Face β In this paper, the term “three-five semiconductor materials” means and includes, mainly consists of one or more elements of the periodic table (^^ and called one or more (four) elements (Ν, P, As). Any material of Sb and Bi). In this paper, the term 'thermal expansion coefficient' is used in the case of a material or construction, and the average linear coefficient of thermal expansion of the material or structure at the temperature is as follows. - In detail, in some embodiments: the invention includes a method of forming a semiconductor structure each of which includes one or more inter-wafer via connections. The inter-wafer via connections can be included in each Two or more portions formed in another process. Figure 1 is a simplified side cross-sectional view of a portion of a first semiconductor structure 1 . The first semiconductor structure 100 may include a layer of material 102 For example, the material 1 〇 2 may include - ceramics such as oxides (such as dioxide dream (Si02) or oxidation (A1203)) or nitrides (such as tantalum nitride (Si #4) or Boron Nitride (BN)). As another example, the first semiconductor material 100 may include a semiconductor material such as a Si, a Ge, a Group 3 or 5 semiconductor material, etc. The material 102 may comprise a single crystal of a semiconductor material or a silicon oxide layer of a semiconductor material. As an example of a non-limiting property, the first semiconductor structure material 102 may comprise a single crystal of one of the host germanium materials. 8 201214627 Another "semiconductor 11G, which can be formed by providing via recesses m in the semiconductor structure 100 of the ® 1. These via recesses 112 can be used to form a portion of the inter-wafer via junction, as follows The method is discussed in detail. As shown in FIG. 2, the via recesses 12 may extend from the -th main surface 104 of the semiconductor structure 110 and at least partially pass through the material of the semiconductor structure 110. In some examples, the through-hole recesses 112 may include blind via-holes (cell d via Ses), the blind via holes only partially pass through the material 1 〇 2 of the semiconductor structure ι. 违 通 通 哺 哺 112 可以 可以 可以 112 112 112 112 112 112 112 112 112 112 112 112 112 112 112 112 112 112 112 112 112 112 112 112 112 112 112 112 112 112 The grooves 112 may have an average cross-sectional dimension (e.g., an average diameter) that is approximately - microns (1 (four) or less, or approximately ten microns (10) (four) or less, or even fifty microns (50 μη〇 or less). In addition, the through-hole grooves ι2 may have an average aspect ratio (the average of the foot and the average cross-sectional dimension), which is from about 0.5 to about 10.0. Figure 3 shows another semiconductor structure 12G, which may be via A dielectric material 122 is formed on the surface of the material 102 in the via recesses 112. As an example of non-limiting properties, the dielectric material 122 may comprise a ceramic such as an oxide (e.g., SiO 2 or alumina (2 〇 3)) nitride (e.g., nitrid幻凡) or nitride (scratch) or nitrogen oxides (such as nitrous oxide eve). The dielectric material 122 can be formed in situ on or in the exposed surface of the material 102 within the via recesses 112. In an additional embodiment, the dielectric material can be deposited over the exposed surface of the material (10) within the via recesses 112. As an example of a particular non-limiting property, the material 102 can include a host material, which can include a oxidized stone, and the dielectric material 122 can pass through the via ι 2 (10) material 丨〇 2 The exposure 9 201214627 surface is oxidized and the dielectric material 122 can also be deposited on the first major surface 104 (FIG. 2) of the semiconductor structure 110, as shown in FIG. Referring to Figure 4, the via recesses 112 (Fig. 3) may be filled with a sacrificial material 132. The sacrificial material 132 includes one material that will eventually be removed and replaced by another material, as discussed below. The sacrificial material 132 can include, for example, polycrystalline material. In other words, the sacrificial _ can include a 构造 having a micro-structure comprising a plurality of mutually bonded ruthenium particles randomly distributed within the microstructure. Such materials are commonly referred to as "polycrystalline stone" materials in the art. In the case of additional implementation, relative to the material 1〇2 (and, alternatively, dielectric material _)” the sacrificial material m may include any other material that can be selected by the lion, such as – shouting the conductor material (eg In the example of e), - (4) win - gold + difference, the sacrifice is simply attached to the coffee - fine, fine, salt, nitride or nitrogen oxides (such as two chest). The sacrificial material 132 can have a selected composition, == 彻 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ In the rectification and transfer wheel net hiding example, the sacrificial material 132 can exhibit a thermal expansion film a two real face swelling 禆 I 百 八 八 ', about the material 102 appears,,,, the side coefficient of the hundred ... ten (4G%) _, 20% (Cong) Lang, or even about 5% (10%) of the current thermal expansion service. In addition, in the case of the thermal expansion film coefficient (4), the material of the sacrificial material 132 may include a material having a coefficient of thermal expansion of 201214627, and the coefficient of thermal expansion is about 5〇xi〇_6〇ci. Or smaller, or about 3.0 X ΙΟ·6 π1 or less 'or even about 〇χ妒i or smaller. After the sacrificial material 132 is provided in the through-hole recesses 112 (FIG. 3), the surface of the semiconductor structure 13 is flattened, and the surface of the material is also exposed to the surface of the material and the material is removed. Tank 13 (4) 峨 _ _ _ _ ^ In more detail, the CVD method can be utilized, for example, to form the sacrificial view 132 uniformly over the desired surface 104 (and the optional 'dielectric material 122'). The sacrificial material m formed may be up to a thickness such that the via recesses 112 at least substantially completely fill the sacrificial material 132. Any excess sacrificial material 132 (and, optionally, the dielectric material) can then be removed to planarize the semiconductor structured surface 134. For example, the surface U4 of the semiconductor structure 13 can be planarized by a chemical process (eg, wet or dry chemical process), a mechanical process (eg, side gamma, _-side side grinding (CMP) process). As mentioned above, after she applied (10) 112 ( _ 3) _ Nana 132, the semiconductor material _ 俺 俺 ( (10) was one. Example of nature, - a thin layer of semiconductor material can be provided as described in _ 5 and 6 below. Figure 5 presents a bonded semiconductor construction that can be formed by bonding another semiconductor construction comprising a substrate (4) to the surface 134 of the semiconductor structure 13A of Figure 4. The material 142 can be a clathrate material, such as Miao (5), Ge (Ge), - San 5 semiconductor materials, etc. 2 The i-layer of the side of the butterfly. As a side, the system can be easily shunned - single crystal .

11 201214627 Substrate 142 T is bonded to surface 134 by a direct-bonding process in which, via the along-bonding interface, it is interposed between the rotating structure 13-side and the substrate. Between one of the M2 bonding surfaces, a direct or molecular bond is provided and the substrate 142 is directly bonded to the semiconductor structure 130 (Fig. 4). In other words, the substrate 142 can be bonded directly to the semiconductor construction 13 without the use of an adhesive or any other intervening bonding material between the substrate 142 and the conductor structure 130. The nature of the atomic or molecular bonding of the substrate M2 to the semiconductor structure 13A depends on the material composition of the substrate (4) and the semiconductor structure 130. Thus, in accordance with some embodiments, a direct atomic or molecular bond can be provided between: oxidized Wei cerium oxide, at least its sputum, and sputum, sputum, oxidized stone, cerium oxide At least one of them. - As an example of non-restrictive properties, the bonding table φ of the substrate 142 may include an oxidized material (e.g., ##(Si〇2))' and the semi-conductive layer (9) may substantially comprise the same Oxidizing material (eg, dioxo (Si〇2)). In such embodiments, the bond surface of the substrate 142 can be bonded to the bonding surface of the semiconductor structure 130 by a direct bonding process of the oxide 11 surface with yttrium oxide. In such embodiments, as shown in FIG. 5, a bonding material 148 (such as s-oxide oxide) may be disposed between the substrate (4) and the semiconductor structure 13 (FIG. 4). Bonding interface. The bond material 148 can have an average thickness of, for example, 1,000 angstroms. In an alternative embodiment, the bonding surface of the substrate 142 can comprise a semiconductor material (for example) and the bonding surface of the semiconductor structure can be at least physically comprised of the same conductor material (e.g., shredded). In such embodiments, the bonding surface of the bottom chair 142 can be bonded to the bonding surface of the semiconductor structure S 13G in a manner that facilitates direct bonding of the silk surface. 8 12 201214627 In the example, the bonding surface of the substrate 142 and the semiconductor structure (10): r = rm marriage, please face and half = sin in - and keep the key bindings in the 1 fire compartment contact. The surface of the bonded surface of the substrate (4) and the bonded surface of the semiconductor structure 13G may be formed to have a surface roughness (RRMS) of about two nanometers (2) (10) or more. Small, or approximately - nano (10 nm) or less, or even about a quarter nanometer - brain) or smaller. In some embodiments, the bonding surface of the substrate 142 and the secondary surface of the rich conductor structure BG are tilted to have a uniform surface roughness (Rrms), the root mean square surface roughness being about four Between one nanometer (〇25) and about two meters (2), or even between about two-meters - nanometer (a5nm) and about one nanometer (l. Onm). The tempering process can include, at a temperature between about 2,000 c) and about 400 degrees C (400 Torr), and between about 2 minutes (2 -) and about u hours During the period of (15 hrs.), the substrate 142 and the semiconductor structure (10) are heated in a furnace. The bonding surface of the substrate 142 and the bonding surface of the semiconductor structure 13 can be subjected to a mechanical polishing process and - The chemical process is at least as described above and is relatively flat/month. For example, a chemical mechanical polishing (CMP) process can be used to bond the key surface of the substrate 142 to the semiconductor structure. The bonding surface is planarized and/or its surface roughness is reduced. One of the first portions 144 of the substrate 142 can be removed from the semiconductor construction 140 of FIG. 5, leaving a second portion 146 of the substrate 142 above the surface 134. Thus, the bonded semiconductor structure 150 of Figure 6 is formed. In other words, the first portion 144 of the substrate 142 can be separated from the second portion 13 201214627 146 of the substrate 142. The semiconductor structure 150 of Figure 6 is included above the surface % Thin layer 152 of semiconductor material. Thin layer of semiconductor material 15 2 is provided by the second portion 144 of the substrate 142 (Fig. 5). Referring again to Fig. 5, as an example of a non-limiting nature, the smart cut 8 process well known in the art can be used to apply the first portion 144 of the substrate 142 with The second portion 146 of the substrate 142 is separated. These processes are detailed in the 'for example, U.S. Patent No. 9,484 (issued on February 6

Bruel) 'US Patent 6,303,468 (issued to Aspar et al. on January 16th, 2001), US Patent 6,335,258 (issued by Aspar et al. on January 1, 2GG2), US Patent 6,756,286 (June 29, 2004) Nissin issued to Hall Warm et al.), US Patent 68〇9, 〇44 (issued to Aspar et al. on January 26, 2004), and US Patent 6,946, secret number (issued to Aspai on September 20, the following year) • et al., the complete disclosure of each patent is hereby incorporated by reference. A plurality of ions (such as hydrogen ions, helium ions or inert gas ions) can be implanted into the substrate (4). The ions may be implanted into the substrate 142 before or after the substrate 142 is attached to the semiconductor of Figure 4 in the manner described above. For example, the ions may be implanted 142 from an ion source (not shown) disposed on one side of the substrate 142. The ions can be implanted 142 along the direction of the main table perpendicular to the reservoir 142. If the technique of the immersion technique is known, the depth of the ion implanted substrate is at least partly the energy of the ion-presenting substrate—in general, the lower energy ion has a relatively shallow implant depth. 'Ion implanted at higher energy, the depth of implantation is relatively deep. The ions can be implanted into the substrate 142 at a predetermined energy for selecting the ions to be implanted into the substrate 142 - the desired depth. As an example of a non-limiting property, the ions may be disposed within the selected depth of the 142 such that the second portion 146 of the substrate 142 has an average thickness of 201214627 degrees T of about 300 nanometers (3 Å) or Thinner, or even about ι〇〇奈(10) coffee). Or thin. As is well known in the art, at least some of the ions may be unintentionally implanted at an undesired depth and as a function of the depth from the surface of the substrate 142 to the substrate 142, the ion concentration The ® table may show a curve that is shaped like a bell (asymmetry of the intercept), which has a maximum at the ideal implant depth. Once the substrate 142 is implanted, the ions can define a fracture plane 143 (shown in phantom in Figure 5) within the substrate 142. The rupture plane 143 can include a layer or region within the substrate 142 that is aligned with the plane having the highest ion concentration within the substrate 142 (4) as centered thereon. The rupture plane 143 can define a weakened region within the substrate 142, and the substrate 142 can be peeled or ruptured along the weakened region during subsequent processing. By applying a mechanical force to the substrate 142 via heated substrate (4), or otherwise applying energy to the substrate 142, the substrate 142 can be peeled or cracked along the rupture plane 143. In an additional embodiment 'a relatively thick layer of material (e.g., a layer having an average thickness greater than about 300 microns) such as substrate 142' is then thinned from the side 149 opposite the surface 134. The substrate 142' can provide a second portion 146 of the substrate 142 over the surface 134 of the semiconductor structure 13() of FIG. For example, the substrate 142 can be processed using a chemical process (eg, a wet or dry chemical etch process), a mechanical process (eg, a grinding or paper milling process), or via a chemical mechanical polishing (CMP) process. Thinning. In other embodiments, a relatively thin layer of semiconductor material (the composition and composition of which may be similar to the second portion 146 of the substrate 142) may be formed in situ in the semiconductor structure of FIG. On surface 134 (eg, above it). For example, a relatively thin layer of material can be formed by depositing material, such as tantalum to fork thickness, on surface 134 of semiconductor construction 130 of FIG. After the thin layer (5) of semiconductor material is provided on the surface 134 of the semiconductor structure 13A of FIG. 3, one or more device structures can be formed over the thin layer 152 of the semiconductor material and/or bite, in other words, one or more The device configuration can be formed using a thin layer 152 of semiconductor material. As an example of non-limiting properties, a plurality of transistors can be fabricated using a thin layer 152 of semiconductor material. Figure 7 shows the bonded semiconductor device 150 of Figure 6 with a dashed line 158 followed by a portion that is processed in the semiconductor structure 150 to form the semiconductor structure 160. Or a plurality of transistors 162. For the sake of clarity, Figure 7 shows only one transistor 162. For example, each of the transistors 162 may include a source, a immersion, and a idler structure 165', wherein the source includes a source region 163A and a source contact 16; Bungee zone 164A and - bungee contact _. The source pure 16 and the secret region 16 may each comprise a region of the thin layer of semiconductor material 52, which has been doped with one or more dopants to enable the regions to conduct the conductive region 163A and the non-polar region. 164A may be separated by a channel region 166, which may include an undoped region of thin layer 152 of semiconductor material. The gate structure 165 can be disposed laterally above the channel region 166' between the and the secret of the transistor 162. The source contact 163B, the gate contact 164B, and the gate structure 165 may each comprise a conductive material such as a metal or a plurality of metal or a doped polycrystalline material. The conductive material of the structure 165 can be electrically isolated from the thin layer 152 of semiconductor material by one or more dielectric materials (e.g., oxide, nitride, oxynitride). As shown in FIG. 7, one or more shallow trench isolation structures 168 may be formed in a thin layer 152 of semiconductor material adjacent to the transistor 162 and through a thin layer 152 of semiconductor material. The shallow trench isolation 16 201214627 168 may include a dielectric material and may be used to electrically isolate each transistor IQ from other transistors or other device configurations of the semiconductor structure 16G. As an example of a non-limiting nature, the shallow trench isolation structures 168 can include dielectric materials such as find compounds, nitrides, gas oxides, and the like. The money groove (10) can be (4) straight fresh (clear to the semiconductor structure, such as the main surface, such as the surface 134, one direction aligned) the through hole groove mountain and the sacrificial material 132 contained therein. In other words, the positions of the through-hole grooves ι 2 and the sacrificial material may be related to each other, such that when the line is drawn, the line is at least substantially perpendicular to the main surfaces of the semiconductor structure, such as the surface m. And passing through the shallow trench isolation structure and one of the via recesses 112 includes a quantity of sacrificial material 132. .  Referring to Figure 8 - the bonded structure of the swivel structure 17 can be over the exposed surface 169 of the semiconductor structure of Figure 7 (one or more of the transistors 162 and the shallow trench isolation structures (10) have been formed A dielectric material layer 172 (eg, an interlayer dielectric material) is provided in and/or on the semiconductor structure, and the first portion 174 of the crystalline via-through junction is formed therein to form a dielectric material layer 172 may be formed or deposited on surface 169 and may have an average thickness sufficient to cover the body! Gate structure 165 of 62, as shown in FIG. The dielectric material layer π may comprise a dielectric material such as an oxide, a nitride, an oxynitride or the like. Continuing to refer to FIG. 8, the first portions 174 of the inter-wafer via connections may be formed in a semiconductor structure it no. The portions 174 of the crystal-transparent connections may include a conductive material such as H, a metal, and a doping. The portions-portion m of the crystal-transparent via connections may be formed by forming pass-through trenches 176 such that the vias, and any bonding material 148, reach the recesses through the dielectric material layer 172 Shallow trench isolation construction 168 17 201214627 Material 102 towel sacrificial material 132 within the through hole recess 112. In some embodiments, the shallow trench isolation features 168 may not necessarily pass completely through the thin layer 152 of semiconductor material, and the via recesses π may also pass through at least a portion of the thin layer 152 of semiconductor material. The through-hole grooves Μ can be formed, for example, by a mask and a meal process. A mask layer can be provided on the exposed main surface of the dielectric material layer 178. The fresh curtain layer can be imparted with ugliness so as to form a hole through the mask layer where the through-hole grooves I76 are to be formed or Opening. The openings in the mask layer can have a cross-sectional dimension and a microscopic desired cross-sectional dimension and shape for the surface galvanic grooves 176 to be formed. The semiconductor construction 17Q can then be exposed to one or more pastes which will pass through the plurality of through-holes 176 through the various (four) but rides (and to a significant extent) the engraved layer. For example, 'wet utilisation-wet chemistry _ process or dry reactive ionic side process through the nucleus 172, the cryptic structure 168, and any bonding material m, to the sacrificial material 132 to form the These through hole grooves 176. In some embodiments, the through holes 176 may have an average aspect ratio (i.e., an average height and an average face size), which is about 5 to about . After the via recesses 176 are formed, a conductive material may be provided in the via recesses (7). For example, one or more metal materials may be deposited in the through-hole recesses 176 by a paste-free process and/or an electrolytic listening process. The wafers_joining the first-parts m are as if they are crossed to find some shallow braided structures and 'scales' (the 主要 卩 胁 转 _ difficult main surface such as surface 134, - square _ solution) The face feeds ΐ 2 and its love contains the sacrificial material 132. In other words, the positions of the first portion 174 and the sacrificial material (four) that are transparently connected between the wafers may be such that when the _ is a straight line, the straight _ substantially sag 18 201214627 is straight to the semiconductor construction no The major surfaces, such as surface 134, and through-the-part portion 174, and one of the via recesses 112, comprise a portion of sacrificial material 132. After forming the first portions 174 of the inter-wafer through-connections, additional processing can be performed to form the conductive vias, the conductive lines, the conductive lines, and the conductive electrodes in the 178-story structure. . Such processes may include a process known in the art as "Back End Process (BEOL)". By way of example, Figure 9 presents a bonded semiconductor structure 18 that can be bonded via a material 働__嫩_fiber 182峨. The device structure 182 can include one or more of conductive vias, conductive lines, conductive traces, and conductive germanium. « Conductive vias, conductive traces, conductive traces, and conductive pads comprise - a conductive material, such as an A variety of metals, or doping (four). The bar-wound dielectric material (8) may include an oxide 'rat compound, a chemical term.鄕 峨 182 and contact details 2 are formed on the major surface 178 of the dielectric material layer 172 by processes well known in the art, in a manner (i.e., layer by layer). As discussed above with respect to Figure 9, 'the device configuration P is formed over the dielectric material layer m, a portion of the material 1〇2 can be removed from the semiconductor structure (10) to expose the sacrificial thin 2' The bonded semiconductor structure (10) has been bonded. The material ^ ^ 撕 半 half face made (10) towel her Q2 surgery Na face job 9) pick, that is, the opposite side of the active surface 186, ^ miscellaneous as an example of non-limiting nature, ^ which can be used, for example , - Chemical _ Process, - Dip Grinding Process Mechanical Grinding ((10)) of the process - one to remove. If - dielectric 19 201214627 material finely broken between the sacrificial material 132 and the material 1 〇 2, as shown in Figure 9, it is said to tear, _ Na _ 132, as shown in Figure 1 。. The semiconductor material 1 〇 2 exposes the sacrificial material 132 to process the (iv) 'side 9 pin 嶋 (10) 槪 (4) bonded to a carrier substrate 192 ′ as shown in FIG. After the sacrificial material 132, such as the circle 1G, is outside the semi-finished, the bonded semiconductor structure 200 shown by the U is removed from the A recess 112. As an example of a non-limiting nature, a through-hole recess m can be removed using a wet process. The velocity of the sacrificial material m, which is greater than the speed at which the dielectric material 122 and any of the bonded materials are removed, is greater than that of the removal of the dielectric material 122 and any of the bonded materials.敝,_娜132 (And, er, ΓΓΓ (4) 122) 机 lion 148 is mixed - _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 2 Oxygen dicing, in the embodiment, the sacrificial material 132 can be selectively side-treated, including a solution of fluoric acid or a plasma side (for example, using six gasification sulphur). The material 132=12 is 7", and the fourth space is provided in the L_112 (the space vacated after the sacrificial material is removed) to form the second portion 212 of the inter-wafer via joints 214. The inter-wafer through-connections 214 include the first portion 174 and the second portions. Direct physical and electrical contacts can be established between the inter-wafer vias called the first portion (10) of the second portions 212. 8 20 201214627 The conductive material of the second portions 212 of the inter-wafer via junctions 214 may comprise a conductive material such as - or a plurality of metals, doped with a crystal. In some embodiments, the conductive material of the second portions 212 of the inter-wafer via 214 may be at least substantially the same as the conductive material of the first portions 174 of the inter-wafer via 214. A conductive material may be provided in the through hole grooves m, m. For example, one or more metallic materials may be deposited in the via recesses 176 by an amount-no-charge process and/or an electrolytic plating process. The inter-wafer via junctions 214 include the first portions 174 and the second portions 2n. Since the first portion η4 and the second portions 212 are formed in separate processes in different time sequences during fabrication of the semiconductor structure, in some embodiments of the invention, - discontinuous, identifiable The edge may be present between the first portion 174 of the inter-wafer via 214 and the microstructure + between the second portions 212. The location of the identifiable boundary 216 can be adjacent to a major surface of the thin layer 152 of semiconductor material. For example, the identifiable boundary 216 can be coplanar with the bonding material 148 disposed on the major surface of the thin layer (5) of the semiconductor material. Further, the semiconductor structure 21 can be oriented parallel to the active surface, as shown in FIG. . In some embodiments, the inter-wafer via junctions 214 may have an average aspect ratio (i.e., a ratio of average magnetic to average cross-sectional dimensions) ranging from about 〇·5 to about _. After the inter-wafer via junctions 214 are formed in the above manner, the carrier substrate 192 can be removed from the bonded processed semiconductor structure 21 of FIG. 12 to form the bonded processed = conductor structure of FIG. 22G. As shown in FIG. 13, the conductive bumps 222 can be structurally and electrically coupled to the second portions 212 of the inter-wafer vias 214 in the semiconductor structure 22 and the active table 21 201214627 face 186 The opposite back surface 224. The conductive bumps 222 may comprise a conductive material such as a conductive solder alloy. The semiconductor structure 220 shown in Figure 13 can optionally be further processed and packaged if desired. The conductive bumps 222 can then be used to structurally and electrically couple the semiconductor structure 220 to another configuration, such as a printed circuit board, another semiconductor structure (eg, another die or wafer), and the like. . In additional embodiments, other configurations and techniques well known in the art, such as conductive leads, anisotropic conductive films, and the like, can be used to electrically and electrically couple the semiconductor structure 22 to another A construction. Referring again to FIG. 10, in some embodiments of the present invention, it may be relatively difficult to selectively engrave the sacrificial material 132 in the via recesses II2 without engraving other materials of the semiconductor structure 19〇. . In such embodiments, it may be appropriate to first protect the other materials of the semiconductor structure 190 and then etch the sacrificial material 132 in the manner described above. For example, Figure 14 presents a semiconductor construction 230 that can deposit a mask layer 232' via the surface of the semiconductor structure & 190 of Figure 1 to make it possible to remove some surface from the carrier substrate to v. Formed substantially covering all of the exposed surface of the semiconductor structure 23 . The mask layer 232 may comprise a ceramic material such as an oxide (for example, sulphur dioxide (SiO 2 ) or oxidized (A1203)), or a nitride (for example, nitrogen (& 眞) money side (4)). Things. The π' mask layer 232 can be patterned as shown in Fig. 15 to form an opening 42 through the mask layer and to produce the bonded processed semiconductor structure (10) of Fig. 15. - lithographic masking and stenciling processes, such as those well known in the art, can be used to form the dimensions, shapes, and locations of the openings 242 through the mask layer. In order to expose the sacrificial material I32 in the through-hole recesses I2 through the openings 。2, a button engraving can be used to form a conductor-like structure or a dry side process. The material of the mask layer 232 is selective. The sacrificial material 132 is selective. This sacrificial process will cause the sacrificial material 132 to be removed from the via-holes 112 to produce the semiconductor structure 25 of FIG. The mask layer attack can then be removed from the semiconductor structure 25A of Figure 16 to form a semiconductor structure that is at least substantially identical to the material structure of Figure u. In an additional method, prior to Figures 9 and 1薄In the manner discussed, after thinning the material, the material axis can be recessed for the sacrificial material 132 and/or, optionally, the dielectric material 122 to form a semiconductor structure of the figure. As an example, Material (10) relative to sacrificial material 132 and/or, selectable The dielectric material 122 is recessed. After forming the semiconductor structure 260 of FIG. π, a mask layer 272 may be deposited on the semiconductor structure 2 (9) to form the semiconductor structure 27G of (4). The mask layer 272 may include - Material, such as oxide (such as dioxide (Si〇2) or oxygen (Al2〇3)), nitride (such as nitriding (talking) or nitriding butterfly (10)) or nitrogen oxides. As shown at 18, the semiconductor structure 27() can include a major surface 274 on one side opposite the carrier substrate 192. The major surface 274 of the semiconductor structure 270 of Figure 18 can be subjected to a planarization process, such as - chemical mechanical polishing ( a CMP) process to remove the mask layer 272 (and any dielectric material called portions above the sacrificial material 132 in the via recesses 112) to form the bonded semiconductor structure of FIG. As shown in Fig. 19, after the main surface 274 is planarized (10) (8), the sacrificial material 132 can be exposed through the mask layer m. After exposing the sacrificial material 132, the semiconductor structure 28 can then be wetted using an engraving agent. Or dry _ process, relative to the mask layer 2V2 The material and the side agent are selective to the sacrificial material 132. This sacrificial process will cause the sacrificial material 132 to be removed from the via recesses 112, resulting in the bonded bonded half 23 201214627 conductor of Figure 2 Constituting k 290. Then, the armor layer π can be removed from the semiconductor structure of Fig. 2 to form at least one semiconductor structure at least substantially identical to the semiconductor structure 2〇〇 of the figure, and then the semiconductor structure can be added as described above Simplified-step processing. In the process of the eve step (for example, a two-step process), an inter-wafer via connection is formed. As described above, the inter-wafer transparent connection can improve normal operation during manufacturing. ... The production & ® is the aspect ratio of the through-hole connection of the whole crystal, and the wafer gates are connected to each other. The width and height of different parts are relatively small. Therefore, the sides of the through-hole grooves are easier (the different portions of the through-wafer vias are formed in the order), and the insulating dielectric material is in the ... The coverage of the exposed surface of the trench will increase, and the fabrication of the conductive material in the via recesses (the fabrication of the transistors 162 as described herein) may result in semiconductor construction. Withstanding a temperature higher than Jochen C. If a conductive metal is disposed in the via recess at such high temperatures during processing of the semiconductor structure, the metal atoms may diffuse to other regions of the semiconductor structure. This diffusion may have an unfavorable shirting effect on the semi-conducting operation. In addition, the thermal expansion coefficient of the metal material and the surrounding dielectric material = the semiconductor side are not difficult, and the wire structure destruction can be created. The material 3 峨 嶋 轴 轴 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Additional miscellaneous f As described below: Embodiment 1 · A method of making a half-guide k" includes: forming a cross-wafer-through-part-partial portion in a partial through-half to f(four) supply-difficult tree surface. And aligning the first portion of the at least one fiber through connection 8 24 201214627 with the at least one through hole groove; and replacing the sacrificial material in the at least one through hole groove with a conductive material, and forming the at least one crystal A second portion of the inter-round connection is electrically connected to the first portion of the at least one inter-via via-connected. Embodiment 2: The method of Embodiment 1, wherein at least the semiconductor structure is formed The first portion of the inter-wafer via connection further includes a first portion of the at least one inter-via via-through via a dielectric material. Embodiment 3: The method of Embodiment 1, wherein the at least one Providing the sacrificial material in the through-hole recess partially through the semiconductor structure includes: forming at least one blind via recess from which the surface of the semiconductor structure passes partially through the semiconductor structure; and in the resident-bribery via recess Provided - At least one of a polycrystalline tree material, a tri-five semiconductor material, and a dielectric material. Embodiment 4: The method of the method of claim 3, wherein the towel provides a plurality of grooves in the at least one hole At least one of a crystalline 7 material, a tri-five semiconductor material, and a dielectric material includes providing a polysilicon material in the at least one blind via recess. Embodiment 5: The method of Embodiment 3 The method further comprises: between the main financial material and the polycrystalline germanium material in the at least one blind via recess. A method of providing a dielectric material. Embodiment 7: The method of Embodiment 3, further comprising: providing the polycrystalline tree material in the at least one blind via hole and providing a half on the surface of the conductor structure A thin layer of a conductive material. Embodiment L is the method of Embodiment 7 wherein providing a thin layer of semiconductor material on the surface of the rotating structure comprises implanting ions in a substrate comprising a semiconductor material to facilitate the bottom 25 201214627 The plane is formed in the material; riding the key to the face of the bet And breaking the substrate along a plane side, and the casting material of the substrate layer and the profile - the remaining part of the separation, the thin layer of semiconductor material remains bonded to the surface of the semiconductor structure. The method of embodiment 9, wherein the substrate is bonded to the surface of the conductor structure comprises directly bonding the substrate to the surface of the semiconductor structure. Embodiment 10: The method of Embodiment 7, the complex clause, further comprising forming at least a portion of a device configuration using the thin layer of + conductor material. Embodiment 11: The method of Embodiment 10, wherein at least a portion of the thin layer forming device structure of the semiconductor material is utilized in the bean, wherein at least a portion of the thin layer of the semiconductor material is formed using the thin layer of the semiconductor material. Embodiment i2: The method of Embodiment 7, wherein providing a thin layer of semiconductor material on the surface of the semiconductor structure comprises forming the thin layer to have a thickness of about 3 nanometers (3 Å) or less An average thickness. Embodiment 13: The method of Embodiment 12 wherein providing a thin layer of semiconductor material on the surface of the semiconductor structure comprises forming the thin layer to have a thickness of about 10 nanometers (1 〇〇 η ' nm ) or less An average thickness. Embodiment 14: The method of any of embodiments 1 to 13, further comprising, after forming the at least one pass-through via, and replacing the sacrificial material with a conductive material and forming the at least one inter-wafer The semiconductor structure is thinned prior to the second portion of the via. Embodiment 15: The method of Embodiment 14 wherein thinning the semiconductor structure comprises exposing the sacrificial material to an exterior of the semiconductor structure. Embodiment I6: The method of Embodiment 14 further comprising: thinning the Before the semiconductor construction / ^v 26 201214627 will identify the conductor structure _ to - face button; and in the thinning of the words, the carrier substrate is removed from the semiconductor structure. Embodiment 17: A method of fabricating a semiconductor structure, comprising: providing an i-material in at least one via recess extending into a surface of a semiconductor structure; providing a layer of semiconductor material on a surface of the semiconductor structure Making at least one device structure using the semiconductor material layer: forming at least one inter-wafer via-connected portion of the semiconductor material layer; thinning the semiconductor structure from a side opposite to the semiconductor material layer Removing the sacrificial material from at least one via recess in the semiconductor structure and exposing a first portion of the via interconnect between the at least one via in the via recess; and in the via recess A conductive material is provided and a second portion of the at least one inter-wafer via connection is formed. Embodiment 18: The method of Embodiment 17, wherein providing the sacrificial material within the at least one via recess comprises providing a polysilicon material within the at least one via recess. The method of embodiment 17 or embodiment 18, further comprising providing a dielectric material between the sacrificial material and the semiconductor structure in the at least one via recess. The method of any one of embodiments 17 to 19, wherein providing the layer of semiconductor material on the semiconductor 'red-framed red surface comprises transferring the layer of conductive material from the substrate to the semiconductor construction. The method of embodiment 20, wherein the transferring the layer of material material from the substrate to the semiconductor structure comprises: in the riding field; the bonding semiconductor structure; and causing the substrate to follow the substrate One of the planes defined by the ions therein is split and the semiconductor material layer is separated from the remaining portion of the substrate. Example 22 . The method of any one of embodiments 17 to 21, wherein providing a layer of semiconductor material on the surface of the semiconductor 27 201214627 configuration comprises selecting the layer of semiconductor material to have a thickness of about 100 nm (100 nm) or less. The average thickness. The method of any one of embodiments 17 to 22, further comprising: attaching the semiconductor structure to a carrier substrate prior to thinning the semiconductor structure; and after thinning the semiconductor structure, The carrier substrate is removed from the semiconductor construction. The method of any one of embodiments 17 to 23, further comprising forming a conductive bump on the at least one inter-wafer via joint. Embodiment 25: a semiconductor construction comprising: a sacrificial material in at least one via recess, the at least one via recess partially passing through the semiconductor structure from a surface of the semiconductor structure, the se* being disposed a semiconductor material on the surface of the semiconductor structure; at least one device configuration comprising at least a portion of the semiconductor material disposed on the surface of the semiconductor structure; at least one wafer-perforated connection-partial portion, The at least one pass-through is coupled through the semiconductor material disposed on the surface of the semiconductor structure, and the at least one first portion of the through-wafer via is aligned with the at least one via recess. Embodiment 26: The semiconductor construction of embodiment 25, further comprising a portion of a dielectric material, at least a portion of the casting material on the surface of the semiconductor structure, the at least one crystal clear The first portion of the joint passes through and directly contacts the portion of the dielectric material. Embodiment 27: The semiconductor construction of Embodiment 26, wherein the portion of the dielectric material comprises a shallow trench isolation configuration. The semiconductor construction of any one of embodiments 25 to 27, wherein the sacrificial material comprises a polycrystalline germanium material. Embodiment 29 The material construction of any of embodiments 25 to 28, wherein the cap is at least 28 201214627 a device configuration comprising at least one transistor. Embodiment 30: The materials of Embodiments 25 to 29 are exposed to the ^Dunnufeng conductor structure, wherein the sacrificial + path is outside one of the abundance conductor structures, and the outer layer is opposite to the semiconductor conductor structure One side. Embodiment 31: The semiconductor structure according to any one of Embodiments 25 to 30 is located at the bottom of the semiconductor.  The semiconductor structure of any one of embodiments 25 to 31, wherein the semiconductor material disposed on the surface of the filament of the semiconductor layer comprises a layer of a semiconductor material, the layer of semiconductor material having approximately One of the average thickness of 300 nm (300 nm) or thinner. Embodiment 33: The semiconductor construction of Embodiment 32, wherein the layer of semiconductor material has an average thickness of about 100 nanometers (1 nm) or less. Embodiment 34: a semiconductor structure comprising: an active surface; a back surface; at least one transistor positioned within the semiconductor structure between the active surface and the back surface; at least one inter-wafer interconnective connection At least partially passing through the semiconductor structure from at least one of the active surface and the back surface, the at least one inter-wafer through-bonding comprising: a first portion; a second portion; and an identifiable boundary between One of the first part is between the microstructure and one of the second part of the microstructure. Embodiment 35: The semiconductor construction of Embodiment 34, wherein the at least one transistor comprises at least a portion of a thin layer of semiconductor material. Embodiment 36: The semiconductor construction of Embodiment 35, wherein the thin layer of semiconductor material has an average thickness of about 100 nanometers (100 nm) or less. The semiconductor construction of embodiment 35 or embodiment 36, wherein the identifiable boundary is adjacent to a major surface of the thin layer of semiconductor material. The semiconductor construction of any one of embodiments 34 to 37, wherein the identifiable boundary is parallel to at least one of the active surface and the back surface. While the embodiments of the present invention have been described herein by way of example, those skilled in the art will recognize and understand that the invention is not limited to the exemplary embodiments. On the contrary, the exemplary embodiments may be varied and modified without departing from the scope of the invention as set forth below. The features of the embodiments can be combined with the features of other embodiments, but still fall within the scope of the invention as set forth by the inventors of the present invention. [Simple description of the drawings] Although this manual uses the special fiber to make a knot, it specifically points out that the detailed record is regarded as the real domain of this month, and when Bao He’s touch-forward transfer is implemented, some fine ships are used. The advantages of the embodiments of the invention are more apparent from the drawings, in which: FIG. 1 is a simplified side cross-sectional view of a semiconductor structure-part; and FIG. 2 is a simplified side cross-sectional view of another semiconductor structure. The other semiconductor construction may be formed by providing a via recess partially through the semiconductor configuration of FIG. 1; FIG. 3 is a simplified side cross-sectional view of a portion of another semiconductor structure, which may be, a semiconductor material is formed by providing a dielectric material in the surface of the surface of the trench; 201214627, for example, polycrystalline stone A material is provided in the recess and formed; FIG. 5 is a simplified side cross-sectional view of a portion of a bonded semiconductor structure. The semiconductor structure can be formed by bonding another semiconductor structure to the swivel configuration of FIG. ; Figure 6 Simplifying a side cross-sectional view of one of the other semiconductor constructions, which may be formed by thinning another semiconductor configuration in the bonded semiconductor construction of FIG. 5; FIG. 7 is an enlarged view of a portion of another semiconductor construction The other semiconductor structure can be formed by fabricating a transistor and a shallow trench isolation structure in and/or on the bonded semiconductor structure of FIG. 6; FIG. 8 is an enlarged view of a portion of another semiconductor structure, the other The semiconductor structure can be formed by providing a layer of dielectric material over the semi-conductive H structure of FIG. 7 and providing a portion of the inter-wafer via junction between the inter-wafer structures; FIG. 9 is a portion of another semiconductor structure - magnification The alternative semiconductor structure can be formed by forming a layer comprising a conductive structure or multi-grinding on the surface of the semiconductor structure of the figure; FIG. 10 is an enlarged view of a portion of the other semiconductor structure, which can be via 9 is formed by bonding a semiconductor structure to a carrier substrate; FIG. 11 is an enlarged view of another semiconductor structure - the other semiconductor structure can be The material is removed from the through-hole recesses of the semiconductor structure of the drawing; FIG. 12 is an enlarged view of another semiconductor structure-part, which may be via FIG. The conductive material is provided in the through-hole recesses of the semiconductor structure to form an additional portion of the transparent connection of the germanium in the semiconductor structure; \ 31 201214627 ϋ η is a p-semiconductor structure - part of the enlarged view The semiconductor-structure can be formed by removing the carrier substrate from the semiconductor construction of FIG. 12 and providing conductive bumps on the exposed ends of the inter-wafer via connections; FIGS. 14-16 present additional methods. It can be used to process the __ semiconductor as shown in FIG. 1A as one of the semiconductor structures as shown in FIG. 11; and FIGS. 17 to 20 present more other methods, which can be used for one of FIG. The semiconductor process is a semiconductor structure as shown in FIG. [Main Element Symbol Description] 100 First Semiconductor Structure 102 Materials 104, 134, 149, 169, 178, 186, 274 Surfaces 110, 120, 130, 140, 150, 160, 170, 180, 190, 200, 210, 220 230, 240, 250, 260, 270, 280, 290 semiconductor construction 112, 176 via recess 122 dielectric material 132 sacrificial material 142, 144, 146, 192 substrate 143 rupture plane 148 bonding material 152 semiconductor material thin Layer 158 dashed line 162 transistor 163 Α, 164 区 163 164, 164 Β汲 165 contact 165 gate structure 166 channel region 32 8 201214627 168 shallow trench isolation structure 172 dielectric material layer 174 first portion ' 182 device configuration 184 dielectric material 212 Second portion 214 through junction 216 boundary 222 conductive bump 224 back surface 232, 272 mask layer 242 opening 33

Claims (1)

201214627 VII. Patent application scope: 1. A method for fabricating a semiconductor structure, the method comprising: providing a sacrificial material in at least one via hole of a partial through-semiconductor structure, forming at least a semiconductor material in the semiconductor structure a __th portion of the transparent connection, and aligning the at least one inter-wafer via-bonded first portion with the at least one via-hole and replacing the at least one via with a conductive material The sacrificial material in the groove forms a through-opening connection between the at least one corona circle. The - part is electrically contacted with the first portion of the at least one wafer that is electrically connected. 2. The method of claim 1, wherein forming at least one inter-wafer via-connected portion in the semiconductor structure further comprises passing the at least one first pass-through first portion through the first portion Dielectric material. 3. The method of claim 1, wherein providing the sacrificial material in the at least one through-via recess of the semiconductor structure comprises: forming at least one blind via recess 'from the semiconductor construction One surface is partially passed through the semiconductor structure; and at least one of the polycrystalline transfer material, the one-three-five semiconductor material, and one dielectric material is provided at the y blind pass. 4. If the patent application method is omitted, it further includes forming the at least one through hole groove. 5. The method of claim 4, wherein the method further comprises: providing a "intermediate frequency between the material" and the at least one blind pass gamma trough. The method of claim 3, further comprising providing a thin layer of semiconductor material on a surface of the semiconductor structure after providing the polycrystalline material in the at least one blind via recess. The method of claim 6 wherein providing a thin layer of semiconductor material on the surface of the semiconductor structure comprises: implanting a substrate in a substrate comprising a semiconductor material to facilitate formation of the substrate into a rupture plane; Bonding to the surface of the semiconductor structure; and cracking the substrate along the rupture plane and separating the thin layer of semiconductor material from the remaining portion of the substrate. The thin layer of semiconductor material remains bonded to the conductor structure 8. The method of claim 6, further comprising the step of forming a thin layer of semiconductor material forming at least a portion of the device structure. 9. The method of claim 8 wherein the semiconductor material is thin. Layer shape At least a portion of the device structure includes at least a portion of the semiconductor material (four) layer forming a crystal. 10. The method of claim 1, further comprising, after forming the at least one inter-wafer connection The semiconductor structure is thinned prior to replacing the sacrificial material with a material of f and a second portion of the inter-wafer via connection. 35 201214627 A semiconductor construction comprising: at least one via hole a sacrificial material, the at least one via recess partially passing through the semiconductor structure from a surface of a semiconductor structure; and one half of the surface disposed on the surface of the semiconductor structure: a conductor material; 12_ as claimed in the U The semiconductor construction of the present invention, further comprising: at least one device configuration comprising at least a portion of a semiconductor material disposed on the surface of the semiconductor structure; and at least one wafer-perforated connection - a portion, the at least - The inter-wafer is transparently connected through the casting material disposed on the surface of the de-conductor structure, and the first inter-wafer-through connection is eliminated. The semiconductor structure of claim 12, further comprising a portion of the dielectric material 其 at least partially disposed on the surface of the semiconductor structure Surrounded by semiconductor materials, ^ ^ 崎通 connects U to a direct contact with a portion of the dielectric material. μ · The semiconductor structure of claim 13 of the patent 'where the amount of dielectric material includes - shallow trench isolation structure. The semiconductor construction of claim 11, wherein the sacrificial material comprises a polycrystalline stone material. 16. The semiconductor construction of claim 12, wherein the at least one device configuration comprises at least one transistor. The semiconductor construction of claim 11, wherein the sacrificial material is exposed to the outside of the semiconductor structure, the outer portion being located on a side opposite to the semiconductor material disposed on the surface of the semiconductor structure. 18. The semiconductor construction of claim 17 of the patent application, further comprising a carrier substrate attached to the semiconductor construction. 19. The semiconductor construction of claim 11, wherein the semiconductor material disposed on the surface of the semiconductor structure comprises a layer of semiconductor material having one of about 300 nm (300 nm) or less. The average thickness. 20. The semiconductor construction of claim 19, wherein the semiconductor material has an average thickness of about 100 nanometers (100 nm) or less. Increase, have 37