201225532 六、發明說明： 【發明所屬之技術領域】 本發明係有關於-種移位暫存n電路，尤指—種具低功率 消耗/低電壓應力/高訊號傳輸能力之移位暫存器電路。 【先前技術】 液晶顯示裝置(Liquid CryStalDisplay ; LCD)是目前廣泛使用的 -種平面顯4，其具㈣型輕薄、省f以及減射紐點。液晶 顯示裝置的功原理係利用改變液晶層兩端的電壓差來改變液晶層 内之液晶分子的排列狀態，用以改變液晶層的透紐，再配合背光 換組所提供的光源以顯示影像…般而言，液晶顯示裝置包含複數 畫素單元、源極驅動H錢移位暫存器電路。雜驅動⑽用來提 供複數㈣訊號至複數晝素單元。移㈣存器€路包含複數級移位 暫存器以產生複數閘極机號饋入複數晝素單元，據以控制複數資料 訊號的寫人運作。因此，雜暫存料路即為控制龍訊號寫入操 作的關鍵性元件。 在液晶顯示裝置設計中為了降低製造成本，通常會將移位暫存 器電路整合於包含晝素陣列之顯示面板上，亦即基於g〇a (Gate-driver 〇n Array)架構，但若無法降低移位暫存器電路 的功率消耗，則顯示面板的操作溫度會隨之上昇，從而降低顯 示品質’並會降低面板使用壽命。此外，基於G〇a架構的 201225532 移位暫存n電路之紐級移㈣翻魏合複制極線而依序設置 於顯示面板之相當狹長的邊框區域，亦即並非積集於很小的晶片面 積内所以右在移位暫存器電路的運作中，高頻訊號、低頻訊號及 直流訊號均胁_之高準絲顯低準位麵财但功率消耗 、降低纟級移位暫存器間的訊號傳輸能力亦難以提昇，尤其在 低溫開機時’低訊號傳輸能力更難以達舯速啟動的目的。’、 【發明内容】 、—依據本發明之實施例，其揭露一種移位暫存器電路，用以提供 複數閘極峨至複數閘極線。此種移位暫存器電路包含複數級移位 暫，器’該些級移位暫存器之第N料多位暫存器包含輸入單元、上 拉早7G、^位單元、第—下拉單元、第二下拉單元、及第三下拉單 儿。輸入單凡侧來根據至少_輸人喊以細驅動控制電壓。電 連接於輸人單元與第N _線之上拉單元_來根據驅動控制電壓 與上拉時脈以上拉第N _訊號。電連接於輸人單元之進位單元係 用來根據爾控制電壓與進位雜喃出第N啟始脈波訊號。電連 接於輸入單it之第—下拉單^係用來根據第—下拉時脈將驅動控制 電壓下拉至第-低電源。電連接於進位單元之第二下拉單元係 用來根據第二下拉時脈將第N啟始脈波峨下拉至第三低電源電 壓:電連接於第N閘極線之第三下拉單元_來根據第三下拉時脈 將第N閘極訊號下拉至第三低電源電壓。 【實施方式】 201225532 下文依本發明移㈣存器電路，特舉實施例配合所附圖式作詳 細說明’但所提供之實施例並賴以限制本發明所涵蓋的範圍。 第1圖為本發明第—實施例之移位暫存器電路的示意圖。如第 1圖所示’移位暫存器電路100包含複數級移位暫存器，為方便說 明’移位暫存器電路100只顯示第(N_2)級移位暫存器、第叫1) 級移位暫存器112、Μ級移位暫存器113、第_)級移位暫存器 1Μ以及第(Ν+2)級移位暫存器i 15，其中只有第Ν級移位暫存器⑴ 顯:内部功能單搞構，其餘級移位暫存器係類同於第㈣移位暫 存器113 ’不另贅述。在移位暫存H電路1GG的運作巾，第Ν級移 位暫存器113係用來根據第一輸入訊?虎如卜第二輸入訊號㈤、 第-上拉雜CKPUJ、帛—雜雜CKeaJ、帛―下拉時脈 CKpd_l、第二下拉時脈CKpd_2、第三下拉時脈cKpd_3、第一低 電源電壓Vssl、第二低電源電壓Vss2及第三低電源電壓μ以產 生驅動控制電壓VQn、閘極訊號SGn與啟始脈波訊號他，其中第 -輸入訊號Sinl可為高電源·或為其他級移位暫存器所產生 之驅動控制賴、閘極訊號或啟始脈波訊號，第二輸人訊號_可 為其他級移㈣存輯產生之驅動控織壓、_峨或啟始脈波 訊號’第二輸入訊號Sin2可相同或相異於第一輸入訊號_，其餘 級移位暫存11可_類推。請注意，第丨_示之第—上拉時脈 CKpu—1、第二上拉時脈CKpu—2、第三上拉時脈cKpu」及第四上 拉時脈CKPU—4可具有週期性依序錯開或部分重疊之脈波，第一進 位時脈CKca—1、第二進位時脈CKca—2、第三進位時脈CKca—3及 201225532 第四進位時脈CKea_4何相對應地具有週·依序錯開或部分重 疊之脈波。在另-實施例中，移位暫存器電路1〇〇之複數級移201225532 VI. Description of the Invention: [Technical Field] The present invention relates to a type of shift temporary storage n circuit, and more particularly to a shift register having low power consumption/low voltage stress/high signal transmission capability Circuit. [Prior Art] A liquid crystal display device (Liquid CryStalDisplay; LCD) is widely used at present - a type of flat display 4, which has a (four) type of light and thin, saves f and a subtraction point. The working principle of the liquid crystal display device is to change the arrangement state of the liquid crystal molecules in the liquid crystal layer by changing the voltage difference between the two ends of the liquid crystal layer, to change the transparent layer of the liquid crystal layer, and to match the light source provided by the backlight group to display the image. In other words, the liquid crystal display device includes a plurality of pixel units and a source drive H money shift register circuit. The miscellaneous drive (10) is used to provide a complex (four) signal to a complex pixel unit. The shift (four) register includes a plurality of shift registers to generate a plurality of gate numbers to feed the plurality of pixel units, thereby controlling the writing operation of the plurality of data signals. Therefore, the miscellaneous storage path is the key component for controlling the write operation of the Dragon signal. In order to reduce the manufacturing cost in the design of the liquid crystal display device, the shift register circuit is usually integrated on the display panel including the pixel array, that is, based on the g〇a (Gate-driver 〇n Array) architecture, but if By reducing the power consumption of the shift register circuit, the operating temperature of the display panel will rise, which will reduce the display quality' and reduce the panel life. In addition, the 201225532 shift temporary storage n-circuit based on the G〇a architecture is sequentially placed on the relatively narrow frame area of the display panel, that is, not accumulated in a small wafer. Within the area, so in the operation of the shift register circuit, the high-frequency signal, the low-frequency signal and the DC signal are both threatened. The high-order wire has a low level, but the power consumption is reduced, and the level shift register is lowered. The signal transmission capability is also difficult to improve, especially when the low-temperature boot is enabled, the low-signal transmission capability is more difficult to achieve the purpose of idle start. In accordance with an embodiment of the present invention, a shift register circuit is disclosed for providing a plurality of gate turns to a plurality of gate lines. The shift register circuit includes a plurality of shift stages, and the Nth material multi-bit register of the stage shift register includes an input unit, a pull-up 7G, a bit unit, and a pull-down Unit, second pulldown unit, and third pulldown. Enter the single side to drive the control voltage according to at least _ input shouting. Electrically connected to the input unit and the N-th line upper pull unit_ to pull the Nth_signal according to the drive control voltage and the pull-up clock. The carry unit electrically connected to the input unit is used to illuminate the Nth start pulse signal according to the control voltage and the carry. The first connection to the input unit it is used to pull down the drive control voltage to the first low supply according to the first pull down clock. The second pull-down unit electrically connected to the carry unit is configured to pull the Nth start pulse wave 峨 to the third low power supply voltage according to the second pull-down clock: the third pull-down unit _ electrically connected to the Nth gate line Pulling the Nth gate signal to the third low supply voltage according to the third pulldown clock. [Embodiment] 201225532 Hereinafter, the present invention is described in detail with reference to the accompanying drawings, but the embodiments are provided to limit the scope of the invention. Figure 1 is a schematic diagram of a shift register circuit of the first embodiment of the present invention. As shown in FIG. 1 , the shift register circuit 100 includes a plurality of shift register registers. For convenience of explanation, the shift register circuit 100 only displays the (N_2)th shift register, and the first call a stage shift register 112, a stage shift register 113, a stage _) shift register 1 Μ, and a (Ν + 2) stage shift register i 15, wherein only the third stage shift Bit register (1) display: internal function single construction, the remaining stage shift register is similar to the fourth (four) shift register 113 'will not be described. In the operation wiper of the shift temporary storage H circuit 1GG, the first stage shift register 113 is used for the second input signal (5), the first-up pull CKPUJ, the 帛-hetery CKeaJ according to the first input signal. , 帛 - pull-down clock CKpd_l, second pull-down clock CKpd_2, third pull-down clock cKpd_3, first low power supply voltage Vssl, second low power supply voltage Vss2 and third low power supply voltage μ to generate drive control voltage VQn, gate The pole signal SGn and the start pulse wave signal, wherein the first input signal Sinl can be a high power supply or a drive control, a gate signal or a start pulse signal generated by another stage shift register, and a second The input signal _ can be used for other levels of shifting (4) memory generated by the control of the weaving pressure, _ 峨 or start pulse signal 'the second input signal Sin2 can be the same or different from the first input signal _, the rest of the shift temporarily Save 11 can be _ analogy. Please note that the first __the first-pull clock CKpu-1, the second pull-up clock CKpu-2, the third pull-up clock cKpu" and the fourth pull-up clock CKPU-4 may have periodicity Sequentially staggered or partially overlapping pulse waves, first carry clock CKca-1, second carry clock CKca-2, third carry clock CKca-3 and 201225532 fourth carry clock CKea_4 have corresponding weeks • Pulses that are staggered or partially overlapping in sequence. In another embodiment, the shift register circuit 1 has a complex level shift
存器可基於互為反相之二上拉時脈與互為反相之二進位時脈 閘極訊號掃描運作。 T 第Ν級移位暫存器113包含輸入單元12〇、進位單元⑵、上 拉單元130、第一下拉單元14〇、第二下拉單元15〇、以及第三下拉 單元160。輸入單元120係用來根據第一輸入職咖盘第二輸入 訊號Sin2以輸出驅動控制電壓VQn。電連接於輸入單元⑽與問極 f GLn之上拉單元130係、用來根據驅動控制電壓與第一上拉 時脈CKpu—1以上拉閘極訊號SGn，其中間極線—係用以傳輸問 $訊號咖。電連接於輸人單元12G之進位單元125係时 動控制電壓VQ續第-進位時脈以輸出啟始脈波訊號 STn。第-雜時脈CKea」之讀週麟糊或相異於第一上拉時 脈CKPUJ之工作週期。電連接於輸入單元120之第一下拉單元14〇 係用來根據第-下㈣脈CKpd—!將驅動控制電壓心下拉至第一 低電源電壓Vss卜第一下拉時脈CKp(U之頻率係相同或相異於第 :上拉時脈CKpuJ之頻率。電連胁進位單元125之第二下拉單 凡150係用來根據第二下拉時脈CKpd—2將啟始脈波訊號抓下拉 至第二低電源電壓Vss2。第二下拉時脈CKpd_2之鮮仙同或相 異於第-上拉時脈CKPUJ之頻率。電連接於閘極線❿之第三下 拉單=160係用來根據第三下拉時脈叫―3將間極訊號㈣下拉 第-低電源電壓Vss3。第三下拉時紅㈣―3之頻率係相同或相 201225532 異於第一上拉時脈CKpu_l之頻率。 第2圖為第1圖之第N級移位暫存器的—電路實施例之示意 圖。在第2圖所示的電路實施例中，輸入單元m包含第一電晶體 121進位單兀125包含第二電晶體126，上拉單元⑽&含第三電 晶體131 ’第-下拉單^ 14G包含第四電晶體141、第五電晶體142、 第六電晶體143、第七電晶體144與第八電晶體145，第二下拉單元 鲁150包含第九電晶體⑸、第十電晶體152、第十一電晶體153、第 十二電晶體154與第十三電晶體155，第三下拉單元包含第十 四電晶體16卜第十五電晶體162、第十六電晶體163、第十七電晶 體164與第十八電晶體165 ^ 入第一電晶體121包含第一端、第二端與閑極端，其中第-端用 來接收第-輸入訊號Sinl，閘極端用來接收第二輸入訊號，第 二端用來輸出驅動控制電壓VQn。第二電晶體126包含第一端、第 •二端與閘極端，其中第一端用來接收第-進位時脈CKca_l，第二端 用來輸出啟始脈波訊號STn，閘極端電連接於第一電晶體121之第 二端。第三電晶體131包含第-端、第二端與閘極端，其中第一端 用來接收第一上拉時脈CKPU」，第二端電連接於閘極線GLn，閘 極端電連接於第一電晶體121之第二端。 第四電晶體141包含第一端、第二端與閘極端，其中第一端電 連接於第電晶體121之第二端，閘極端用來接收控制訊號， 9 201225532 第-端用來接收第—低電源電壓Vss卜第五電晶體⑷包含第— 端、第二端與閘極端，其中第一端用來接收第-下拉時脈CKpd i， ^端電連接於第四電晶體141之閘極端。第六電晶體i43包含第 :端 ' 第二端與閘極端’其中第一端電連接於第五電晶體⑷之第 :端，閘極端電連接於第—電晶體121之第二端，第二端用來接收 第一低電源電壓Vssl。第七電晶體144包含第—端、第二端與閉極 端，其中第—端與閉極端用來接收第—下拉時脈CKpcU，第二端 電連接於第五電晶體142之閘極端。第人電晶體⑷包含第一端、 第二端與閘極端，其中第—端電連接於第七電晶體M4之第二端， =極端電連接於第―電晶體121 m瓣接收 電源電壓Vssl。 · 第九電晶體151包含第一端、第二端與閘極端，其中第一端電 連接於第二電晶體126之第二端，閘極端用來接收控制訊號m， 第-知用來接收第二低電源電壓㈣。第十電晶體⑸包含第一 端=二端與閘極端，其中第—端用來接收第二下拉時脈CKpG， ^-=電連接於第九電晶體151之閘極端。第十—電晶體⑸包含 端、第二端與閘極端，其中第—端電連接於第十電晶體⑸之 第二端’閘極端電連接於第1晶體121之第二端，第二端用來接 收第二低電源電壓Vss2。第十二電晶體154包含第一端、第二端與 閘極端’其中第一端與閘極端用來接收第二下拉時脈CK_ 2，第 二端電連接於第十電晶體152之·端。第十三電晶體155包含第 -端、第二端與閘極端，其中第一端電連接於第十二電晶體⑼之 201225532 之第一端’第一蠕用來接 第f端’触端電連接於第-電晶體121 收第二低電源電壓Vss2。 雷遠接;^電日日體161包含第—端、第二端與閘極端，其中第—端 =於閉極線GLn ’閉極端用來接收控制訊號奶，第二端二 斑門減低電源錢細。第十五電晶體162包含第―端、第-端 ==’其中第-端用來接收第三下拉時脈CKpd 3，第二第-:The memory can be operated based on the two-stage pull-up clocks that are mutually inverted and the two-in-one clock gate signal scans that are mutually inverted. The T-stage shift register 113 includes an input unit 12A, a carry unit (2), a pull-up unit 130, a first pull-down unit 14A, a second pull-down unit 15A, and a third pull-down unit 160. The input unit 120 is configured to output a drive control voltage VQn according to the first input service second input signal Sin2. Electrically connected to the input unit (10) and the questioner f GLn upper pull unit 130 for pulling the gate signal SGn according to the driving control voltage and the first pull-up clock CKpu-1, wherein the intermediate line is used for transmission Ask $signal coffee. The carry unit 125 electrically connected to the input unit 12G controls the voltage VQ to continue the first-carry clock to output the start pulse signal STn. The reading of the first-missing pulse CKea is different from the working cycle of the first pull-up pulse CKPUJ. The first pull-down unit 14 electrically connected to the input unit 120 is configured to pull the driving control voltage core to the first low power supply voltage Vss according to the first-low (four) pulse CKpd-!, the first pull-down clock CKp (U The frequency is the same or different from the frequency of the first pull-up clock CKpuJ. The second pull-down of the electrical connection threshold unit 125 is used to capture the initial pulse signal according to the second pull-down clock CKpd-2. To the second low power supply voltage Vss2. The second pull-down clock CKpd_2 is different or different from the frequency of the first-up pull-up clock CKPUJ. The third pull-down single=160 system electrically connected to the gate line is used according to The third pull-down clock is called “3” to pull down the first-low power supply voltage Vss3. The third pull-down red (four) “3” is the same frequency or the phase 201225532 is different from the frequency of the first pull-up clock CKpu_l. 1 is a schematic diagram of a circuit embodiment of an Nth stage shift register of FIG. 1. In the circuit embodiment shown in FIG. 2, the input unit m includes a first transistor 121, a carry unit 125, and a second The transistor 126, the pull-up unit (10) & the third transistor 131'-the pull-down unit 14G includes the fourth transistor 141 a fifth transistor 142, a sixth transistor 143, a seventh transistor 144, and an eighth transistor 145. The second pull-down unit 150 includes a ninth transistor (5), a tenth transistor 152, and an eleventh transistor 153. a twelfth transistor 154 and a thirteenth transistor 155, the third pull-down unit comprising a fourteenth transistor 16 fifteenth transistor 162, a sixteenth transistor 163, a seventeenth transistor 164 and a tenth The first transistor 121 includes a first end, a second end and a free terminal, wherein the first end is for receiving the first input signal Sinl, the gate end is for receiving the second input signal, and the second end is for receiving the second input signal, The driving control voltage VQn is outputted. The second transistor 126 includes a first end, a second end and a gate terminal, wherein the first end is used to receive the first-carry clock CKca_l, and the second end is used to output the start pulse signal STn, the gate is electrically connected to the second end of the first transistor 121. The third transistor 131 includes a first end, a second end and a gate terminal, wherein the first end is configured to receive the first pull-up clock CKPU", The second end is electrically connected to the gate line GLn, and the gate terminal is electrically connected to the second end of the first transistor 121 The fourth transistor 141 includes a first end, a second end and a gate terminal, wherein the first end is electrically connected to the second end of the first transistor 121, and the gate terminal is used for receiving the control signal, 9 201225532 is used to receive the first end - a low supply voltage Vss, a fifth transistor (4) comprising a first end, a second end and a gate terminal, wherein the first end is for receiving the first-pull-down clock CKpd i, and the second end is electrically connected to the gate of the fourth transistor 141 The sixth transistor i43 includes a first end, a second end and a gate terminal, wherein the first end is electrically connected to the first end of the fifth transistor (4), and the gate terminal is electrically connected to the second end of the first transistor 121 The second end is configured to receive the first low power voltage Vssl. The seventh transistor 144 includes a first end, a second end, and a closed end, wherein the first end and the closed end are used to receive the first pull-down clock CKpcU, and the second end is electrically connected to the gate end of the fifth transistor 142. The first transistor (4) comprises a first end, a second end and a gate terminal, wherein the first end is electrically connected to the second end of the seventh transistor M4, and the terminal is electrically connected to the first transistor 121 m. The receiving power supply voltage Vssl . The ninth transistor 151 includes a first end, a second end, and a gate terminal, wherein the first end is electrically connected to the second end of the second transistor 126, and the gate terminal is configured to receive the control signal m. The second low supply voltage (four). The tenth transistor (5) includes a first end = two ends and a gate terminal, wherein the first end is for receiving the second pull-down clock CKpG, and the ^-= is electrically connected to the gate terminal of the ninth transistor 151. The tenth-electrode (5) includes a terminal, a second end and a gate terminal, wherein the first end is electrically connected to the second end of the tenth transistor (5), and the gate terminal is electrically connected to the second end of the first crystal 121, and the second end It is used to receive the second low power voltage Vss2. The twelfth transistor 154 includes a first end, a second end and a gate terminal 'where the first end and the gate terminal are used to receive the second pull-down clock CK_ 2, and the second end is electrically connected to the end of the tenth transistor 152 . The thirteenth transistor 155 includes a first end, a second end and a gate terminal, wherein the first end is electrically connected to the first end of the 201225532 of the twelfth transistor (9), the first creep is used to connect the fth end Electrically connected to the first transistor 121 to receive the second low power voltage Vss2. The remote day body 161 includes a first end, a second end and a gate extreme, wherein the first end = the closed end line GLn 'closed extreme for receiving the control signal milk, and the second end two spot reducing the power supply Money is fine. The fifteenth transistor 162 includes a first end, a first end ==' where the first end is used to receive the third pulldown clock CKpd 3, and the second first::
1 ^輯啊塌_包含第一端、 端門梅15端’其中第—端電連接於第十五電晶體162之苐二 二=連接於第-電晶艘12丨之第二端’第二端用來接收第 二低電源電壓Vss3。第十七電晶體164包含第—端、第 =中第一端與閉極端用來接收第三下拉時脈CKPd 3-，第二 料=於第十五電晶體162之閘極端。第十八電晶體165包含第一 知端與閘極端’其中第—端電連接於第十七電晶體164之第 二：=於第，體121之第二端’第二端用來接收 〜在第N級移位暫存器113騎作中，第一進位時脈心―】之 =準位電壓解於或較佳地高於第-上㈣脈CKpuj之高準位電 壓，第-進位雜CKea—!之鮮位賴係等於龜佳地低於第一 上拉時脈ckpuJ之鲜位龍，帛二低獅賴μ係等於或較 佳地低於第三低電源賴Vss3，第二低電源電壓㈣係等於或較 佳地低於第-上拉時脈CKpuJ之鮮位賴，_增大啟始脈波 201225532 訊號STn之高低準位壓差而提高其訊號傳輸能力。若第一電晶體121 之第一端所接收之第一輸入訊號Sinl為高電源電壓Vdd，則高電源 電壓Vdd係等於或較佳地高於第一上拉時脈QCpu_l之高準位電 壓’據以使第一電晶體121可輕易地根據高電源電壓Vdd以上拉驅 動控制電壓VQn ’如此亦可提高訊號傳輸能力。 第一上拉時脈CKpu一 1之低準位電壓係等於或較佳地高於第一 低電源電壓Vssl，據以抑制第三電晶體131之漏電流。第三低電源 電壓Vss3係等於或較佳地高於第一低電源電壓Vssl，據以抑制第 三電晶體131之漏電流。第三低電源電壓Vss3係低於或較佳地等於 第一上拉時脈ckPu_i之低準位電壓，據以抑制第三電晶體131之 漏電流’若第三低電職壓Vss3絲佳地特第—上拉_ CKpu—1之低準位電壓，則可據以降低第三電晶體⑶承受之電壓 應力。 第一進位時脈CKca」之鮮位電壓係等於或較佳地高於第一 低電源電壓Vssl，據以抑制第二電晶體126之漏電流。第二 電^ss2係等於或較佳地高於第—低電源翅㈣，據以抑制第、 -電b日體126之漏電流。第二低電源電壓 第一進位時脈―之鮮帽，細卩 漏電流，若第二低電源電壓㈣係較佳地等於第—進位時脈6之 之低準位賴，則可據以降低第二電晶體丨26承受之電壓應 201225532 在第電曰曰體121之第一端所接收之第-輸入訊號Sinl為高 電源電壓Vdd的實施例中，為達到開機快速啟動的目的(尤其在低溫 開機時)，高電源電壓·可於開機後之起始時段内先維持在第一高 電壓以執行㈤速啟動運作，於起始時段後，高電源賴vdd從第一 高電壓降綠低之$二高賴㈣省功率消耗。 以上所述各電壓大小關係主要是用來使移位暫存器電路100具 有低功率雜、低電壓應力及高峨傳輸能力W驗速啟動)等運 作特性。除上述電壓大小關係外，在第一輸入訊號Sinl與第二輸入 訊號Sin2#各種可能設定中，為使第—τ拉單元14G、第二下拉單 凡150與第二下拉單元16〇可較有效率或正常地執行電壓下拉運 作第N級移位暫存器出可較佳地基於下述各訊號間電壓大小關 係以進行電路運作，下述各頓大小_為所屬技藝領域中具有通 系知識者所習知，不再贅述其相關之電路運作效能。 第-上拉時脈CKpuj之高準位電壓係高於或等於第一下拉時 ，CKpdJ之轉位電壓。第-上拉時脈CKpu_l之高準位電壓係 高於或等於第二下拉時脈CKpd_2之高準位電壓。第—上拉時脈 CKPUJ之高準位電壓係高於或等於第三下拉時脈CKpd—3之高準 位電壓。 ~ 第進位時脈CKca—Ι之高準位電壓係高於或等於第一下拉時 201225532 脈CKpdJ之高準位·第一進位時脈⑽―工之高準位物系 高於或等7二下拉時脈CKPd_2之高準絲[第—進位時脈、 CKc a_ 1之间準㈣壓係高於或等料三下拉雜3之高準位 電麼。 .第下㈣脈CKpcLl之鮮位電祕低於解科—低電源 糕Vssl。帛二下拉時紅KPO德雜龍制或等於第1、 低電源電C Vssi。第三下拉時脈CKpd—3之低準位電壓 於第一低電源電壓Vssl。 _、次寺 第一下拉_吻（1之鮮位電_低於鱗於第二低 電愿Vss2。f —下拉時脈CKpd—2之低雜電壓係低於或等於第二、 低電源電壓Vss2。第三下拉時脈CKpd」之低準位電 ” 於第二低電源電壓Vss2。 _、次4 第-下拉日恤CKpdJ之鮮位賴係倾鱗於帛三 電堡Vss3。第二下树脈CKpd_2之鱗位龍係低於或等於^ 低電源電龄ss3。第三下拉雜CKpdJ之鮮域壓係低於鱗 於第三低電源電壓Vss3。 第一下拉時脈CKpdJ之低準位電壓係低於或等於第一上拉時 脈CKpuJ之低準位電壓。第二下树脈CKpcL2之低準位電壓係 低於或等於第-絲_CKpu」之鮮位賴。第三下拉時脈 201225532 之低準位電壓係低於或等於第—上拉時脈CKpu-1之低準 下拉時脈CKPdJ之低準位電壓係低於或等於第一進位時 脈ca—i之低準位電壓。第二下拉時脈CKPd—2之低準位電壓係 低於或雜帛-触日梅CKeaJ之鮮位賴。第三下拉時脈 CKpd—3之低準位電壓係低於或等於第一進位時脈心k低準位 第圖為本發明第二實施例之移位暫存器電路的示意圖。如第 3圖所不’移位暫存料路·包含概級移位暫存器，為方便說 明，移位暫存器電路3〇〇只顯示第㈣)級移位暫存器州、第(則) 級移位暫存器312、第N級移位暫存器313、第阶丨)級移位暫存器 314一以及第_)級移位暫存器31S，其中只有第雜移位暫存器犯 顯不内部魏單凡架構，紐級移崎存祕朗於第N級移位暫 存益313 ’不另贅述。在移位暫存器電路300的運作中，第N級移 位暫存器3】3係用來根據第一輸入訊號編、第二輸入訊號sin2、 第-上拉報〇_卜帛―進位喊CKeaJ、帛―下拉時脈 CKpd_l、第一下拉互補時脈CKpd—lc、第二下拉時脈cKpd_2、第 二下拉互補時脈CKpd_2c、第三下拉時脈CKpd_3、第三下拉互補 時脈CKpd一3c、第一低電源電壓vss卜第二低電源電壓Vss2及第 二低電源電壓Vss3以產生驅動控制電壓VQn、閘極訊號SGn與啟 始脈波訊號STn ’其中第一輸入訊號Sinl可為高電源電壓V(Jd或為 15 201225532 其他級移简存器職生之驅動㈣電壓、閘極則^或啟始脈波訊 號’第二輸人訊號Sin2可為其他級移位暫存騎產生之驅動控制電 壓、閘極訊號或啟始脈波訊號，第二輸入訊號Sin2可相同或相異於 第一輸入訊號Sinl，其餘級移位暫存器可同理類推。請注意，第3 圖所示之帛—上拉雜CKPuJ、帛二上拉雜CKPU_2、第三上拉 時脈CKPU—3、及細上拉雜CKpu_4可具有週雛依序錯開或部 分重疊之脈n驗雜CKea」n辦脈心―2、第 三進位時脈CKea_3、及第四進_脈心」亦可姆應地具有週 期性依序錯開或部分重4之脈波。在另—實施例中，移位暫存器電 路3⑻之複數級移位暫存器可基於互為反相之二上拉時脈與互為反 相之一進位時脈以執行閘極訊號掃描運作。 第N級移位暫存器313包含輸入單元32〇、進位單元奶、上 拉單兀330、第一下拉單元34〇、第二下拉單元35〇、以及第三下拉 举元36G。輸人單元汹係用來根據第—輸人訊號咖與第二輸入 =Sin2以輸出驅動控制電壓VQn。電連接於輸入單元別與間極 a夺Π之上1 拉早兀330係用來根據驅動控制電壓VQn與第一上拉 峨^，其恤觀η制以傳輸閘 極甙唬SGn。電連接於輸入單元 _ 動控制電壓VQn與第一進位咖進位早凡325細來根據驅 ST 士倾 纽時脈CKea」讀出啟始脈波訊號 下拉時ΓοΓ輸入單元32G之第—τ拉單元撕制來根據第一 VQn下拉至與第一下拉互補時脈CKpd一1C將驅動控制碰 第—低電源賴㈣。第—下拉互補時脈CKpd_lc係 201225532 ^目於第-下拉時脈CKpd」。電連接於進位單元奶之第二下拉 單元35〇係用來根據第二下拉時脈CKpd—2與第二下拉互補時脈 CKpdJe將啟始脈波訊號STn下拉至第二低電源㈣加。第二下 拉互補時脈CXpdJe献祕第二下㈣脈CKpd—2。電連接於開 極線❿之第三下拉單元制來根據第三下拉時脈CKpd 3與 第三下拉互補時脈CKpd_3c將閘極訊號SGn下拉至第三低電源電 壓Vss3。第二下拉互補時脈CKp(J一乂係反相於第三下拉時脈 CKpd一3 ° 請注意，第—下拉互補時脈CKpd—lc與第一下拉時脈CKpd—j 可具有烟之冑/鮮位賴’帛二下拉互補時紅邮―&與第二 下拉時脈CKpd—2可具有相同之高/低準位電壓，第三下拉互補時脈 CKPd_3c與第三下拉時脈CKpd_3亦可具有相同之高/低準位電壓。 第4圖為第3圖之第>^級移位暫存器的一電路實施例之示意 圖。在第4圖所示的電路實施例中，輸入單元320包含第一電晶體 321，進位單元325包含第二電晶體326，上拉單元330包含第三電 晶體331 ’第一下拉單元34〇包含第四電晶體341、第五電晶體342、 第六電晶體343、第七電晶體344、第八電晶體345與第九電晶體 346 ’第二下拉單元350包含第十電晶體351、第十一電晶體352、 第十二電晶體353、第十三電晶體354、第十四電晶體355與第十五 電晶體356’第三下拉單元36〇包含第十六電晶體36卜第十七電晶 體362、第十八電晶體363、第十九電晶體364、第二十電晶體365 17 201225532 與第二十一電晶體366。 第一電晶體321包含第-端、第二端與閘極端，其中第一端用 來接收第-輸人訊號Sin卜閘極端用來接收第二輸人訊號㈣，第 二端用來輸出驅動控制電壓VQn。第二電晶體326包含第一端、第 二端與閘極端，其中第-賴來接收第—進位時脈CKea」，第二端 用來輸出啟始脈波訊號STn ’閘極端電連接於第—電晶體321之第 二端。第三電晶體331包含第-端、第二端與閘極端，其中第—端 用來接收第—上拉義ckpu-1，第二端電連接闕㈣GLn，間 極端電連接於第一電晶體321之第二端。 第四電晶體341包含第-端、第二端與閘極端，其中第一端電 笛-t第一電晶體321之第二端，閘極端用來接收控制訊號 SC11 ^-端用來接收第-低電源電壓細。第五電晶體342包含第一 第端與閘極端’其中第一端與閘極端用來接收第一下拉時郝 34二第二端電連接於第四電晶體341之閘極端。第六電晶體 體34^一端、第二端與閉極端’其中第一端電連接於第五電晶 端用纽 閘極端電連接於第一電晶體321之第二端，第二 二=一低電源電壓加。第七電晶體344包含第一端、第 '、閘極端，其中第一端電連接 極端用來接收控制鮮sri) # 电曰曰體il之弟間 與閘極端用來接收m-二 端與閘極端，其中第一端 互補時脈CKpd一lc，第二端電連接於第 201225532 七電晶體344之閘極端。第九電晶體346包含第-端、第二端與閘 極端，其中第-端電連接於第八電晶體345之第二端，間極端電連 接於第-電晶體321之第二端’第二端用來接收第—低電源電壓 Vssl。 第十電晶體351包含第一端、第二端與閉極端，其中第一端電 連接於第二電晶體326之第二端，閘極端用來接收控制訊號s⑶， 第二端用來接收第二低電源電壓Vss2。第十一電晶體352包含第一 端、第二端與閘極端，其中第一端與閘極端用來接收第二下拉時脈 CKpd_2第一端電連接於第十電晶體351之間極端。第十二電晶體 353包含第-端、第二端與閘極端，其中第一端電連接於第十一電 晶體352之第二端，閘極端電連接於第一電晶體321之第二端，第 二端用來接收第二低電源電壓Vss2。第十三電晶體包含第一 端、第二端與閘極端，其中第一端電連接於第二電晶體似之第二 端，閘極端用來接收㈣訊號SC22，第二端用來接收第二低電源電 壓Vss2。第十四電晶體355包含第一端、第二端與間極端，其中第 一端與閘極來接收第二下拉互補時脈CKpd &，第二端電連接 於第十三電晶體354之閘極端。第十五電晶體356包含第一端、第 -端與閘極端，其中第-端電連接於第十四電晶體扮之第二端， 間極端電連接於第-電晶體321之第二端，第二端用來接收第二低 電源電壓Vss2。 .端 第十六電晶體361包含第-端、第二端與閘極端，其中第 201225532 電連接於閘極線GLn，閘極端用來接收控制訊號SC31，第二端用來 接收第三低電源電壓Vss3。第十七電晶體362包含第一端、第二端 與開極端’其中第一端與閘極端用來接收第三下拉時脈CKpd_3， 第二端電連接於第十六電晶體361之閘極端。第十八電晶體363包 含第一端、第二端與閘極端，其中第一端電連接於第十七電晶體362 之第二端，閘極端電連接於第一電晶體321之第二端，第二端用來 接收第二低電源電壓Vss3。第十九電晶體364包含第一端、第二端 與閘極端，其中第—端電連接於閘極線GLn，閘極_來接收控制 錢SC32 ’第二端絲接收第三低電源電壓Vss3。第二十電晶體 365一包含第-端、第二端與閘極端，其中第一端與閘極端用來接收 第二下拉互補時脈CKpd_3e，第二端電連接於第十九電晶體3料之 閘極端帛—十一電晶體366包含第一端、第二端與間極端，其中 第^電連接於第二十電晶體365之第二端，閘極端電連接於第一 電曰曰體321之第二端’第二端用來接收第三低電源電壓加。 凊注意’上述關於第i圖與第2圖之移位暫存器電路⑽ 運作的訊號間電獻小關係均可翻於移位暫 ==:=級移位暫存器313’_使移位暫存器電路細 較有麟或正㈣執行魏運作，並具有低功㈣耗 力及南訊號傳輸能力（開機快速啟動)等運作特性。 -^ 綜上所述，藉由本發明可提供具低功 訊號傳輸能力__晴運輪之移位暫存== 201225532 不但可符合節㈣求，亦可提高運作效能。此外，若為降低製1 成本而將移位暫存器電路整合於包含晝素陣列之顯示面板上^ 亦即基於GOA架構’則上述低功率絲、低糕應力及高訊於 傳輸能力雜可賴㈣板簡在低操作溫度以延長面板使" 用壽命，並可進一步提昇顯示品質。 雖然本發明已以實施例揭露如上，然其並非用以限定本發明， 鲁任何具有本發明所屬技術領域之通常知識者，在不脫離本發明X之精 神和範圍内，當可作各種更動與潤飾，因此本發明之保護範圍當^ 後附之申請專利範圍所界定者為準。 田 【圖式簡單說明】 第1圖為本發明第一實施例之移位暫存器電路的示意圖。 第2圖為第1圖之第N級移位暫存器的—電路實施例之示意圖。 第3圖為本發明第二實施例之移位暫存器電路的示意圖。 籲 第4圖為第3圖之第N級移位暫存器的-電路實施例之示意圖。 【主要元件符號說明】 100、300 移位暫存器電路 111 、 311 第(N-2)級移位暫存器 112 、 312 第(N-1)級移位暫存器 113 、 313 第N級移位暫存器 114 、 314 第(N+1)級移位暫存器 21 201225532 115 120 121 125 126 130 131 140 141 142 143 144 145 150 151 152 153 154 155 160 161 162 315 第(N+2)級移位暫存器 320 輸入單元 321 第一電晶體 325 進位單元 326 第二電晶體 330 上拉單元 331 第三電晶體 340 第一下拉單元 341 第四電晶體 342 第五電晶體 343 第六電晶體 344 第七電晶體 345 第八電晶體 350 第二下拉單元 346 第九電晶體 351 第十電晶體 352 第十一電晶體 353 第十二電晶體 354 第十三電晶體 360 第三下拉單元 355 第十四電晶體 356 第十五電晶體1 ^ 啊 塌 _ contains the first end, the end door Mei 15 end 'where the first end is electrically connected to the fifteenth transistor 162 苐 22 = connected to the second end of the first - electric crystal boat 12 ' ' The two ends are used to receive the second low power voltage Vss3. The seventeenth transistor 164 includes a first end, a first intermediate end and a closed end for receiving the third pull-down clock CKPd 3-, and the second material is at the gate end of the fifteenth transistor 162. The eighteenth transistor 165 includes a first known end and a gate terminal 'where the first end is electrically connected to the second of the seventeenth transistor 164: = at the second end of the body 121, the second end is used to receive ~ In the riding of the Nth stage shift register 113, the level voltage of the first carry clock is solved or preferably higher than the high level voltage of the first-fourth (four) pulse CKpuj, the first-carry Miscellaneous CKea-! The fresh position is equal to the turtle's land is lower than the first pull-up clock ckpuJ's fresh dragon, the second low-low lion is equal to or better than the third low power supply Vss3, the second The low power supply voltage (4) is equal to or better than the fresh position of the first-up pull-up clock CKpuJ, and _ increases the high-low level differential pressure of the start pulse 201225532 signal STn to improve its signal transmission capability. If the first input signal Sin1 received by the first end of the first transistor 121 is the high power supply voltage Vdd, the high power supply voltage Vdd is equal to or preferably higher than the high level voltage of the first pull-up clock QCpu_1. Therefore, the first transistor 121 can be easily driven to drive the control voltage VQn' according to the high power supply voltage Vdd. This can also improve the signal transmission capability. The low level voltage of the first pull-up clock CKpu-1 is equal to or preferably higher than the first low power supply voltage Vss1, thereby suppressing the leakage current of the third transistor 131. The third low power supply voltage Vss3 is equal to or preferably higher than the first low power supply voltage Vss1, thereby suppressing the leakage current of the third transistor 131. The third low power supply voltage Vss3 is lower than or preferably equal to the low level voltage of the first pull-up clock ckPu_i, thereby suppressing the leakage current of the third transistor 131, if the third low-voltage voltage Vss3 is good The low-level voltage of the CKpu-1 can reduce the voltage stress on the third transistor (3). The fresh bit voltage of the first carry clock CKca" is equal to or preferably higher than the first low power supply voltage Vssl, thereby suppressing the leakage current of the second transistor 126. The second electric ^ss2 is equal to or preferably higher than the first low power supply fin (four), thereby suppressing the leakage current of the first, electric b body 126. The second low power supply voltage first carry clock - the fresh cap, fine leakage current, if the second low power supply voltage (four) is preferably equal to the low level of the first carry clock 6, then it can be reduced The voltage that the second transistor 承受26 is subjected to should be 201225532. In the embodiment where the first input signal Sinl received at the first end of the first body 121 is the high power supply voltage Vdd, the purpose of fast start-up is achieved (especially When the temperature is low, the high power supply voltage can be maintained at the first high voltage to start the (five) speed start operation during the initial period after the power is turned on. After the initial period, the high power supply depends on the vdd from the first high voltage to fall green. The $2 high (four) provincial power consumption. The above-mentioned voltage magnitude relationships are mainly used to make the shift register circuit 100 have low power mismatch, low voltage stress, and high transmission capability. In addition to the above voltage magnitude relationship, in the various possible settings of the first input signal Sin1 and the second input signal Sin2#, in order to make the first-th pull unit 14G, the second pull-down unit 150 and the second pull-down unit 16 Efficient or Normally Performing Voltage Pull-Down Operation The N-th stage shift register can be preferably based on the following voltage-to-signal relationship for circuit operation. The following sizes are common knowledge in the art. As is known, the relevant circuit operation efficiency will not be described. The high-level voltage of the first-up pull-up clock CKpuj is higher than or equal to the index voltage of CKpdJ when the first pull-down is performed. The high level voltage of the first pull-up clock CKpu_l is higher than or equal to the high level voltage of the second pull-down clock CKpd_2. The first-up pull-up clock CKPUJ's high-level voltage is higher than or equal to the high-level voltage of the third pull-down clock CKpd-3. ~ The high-level voltage of the first carry clock CKca-Ι is higher than or equal to the first pull-down 201225532 The high level of the pulse CKpdJ · The first carry clock (10) - the high level of the work is higher than or equal to 7 The high-level wire of the second pull-down clock CKPd_2 [the first-carry clock, the quaternary (four) pressure system between CKc a_ 1 is higher than the high-level electricity of the three pull-downs. The second (four) pulse CKpcLl fresh bit secret is lower than the solution - low power cake Vssl. When the second pull-down, the red KPO de Zalong system is equal to the first and low power supply C Vssi. The low level voltage of the third pull-down clock CKpd-3 is at the first low power supply voltage Vssl. _, the first drop of the temple _ kiss (1 fresh bit _ below the scale in the second low power will Vss2. f - pull down clock CKpd-2 low voltage is lower than or equal to the second, low power The voltage Vss2. The low level of the third pull-down clock CKpd" is at the second low power supply voltage Vss2. _, the second 4th-down pull-down shirt CKpdJ is fascinated by the squad in the third electric castle Vss3. The scaly dragon of the lower tree vein CKpd_2 is lower than or equal to ^ low power supply age ss3. The third domain of the CKpdJ is lower than the scale of the third low power supply voltage Vss3. The first pulldown clock CKpdJ is low The level voltage is lower than or equal to the low level voltage of the first pull-up clock CKpuJ. The low level voltage of the second lower tree CKpcL2 is lower than or equal to the first position of the first-wire _CKpu. The low level voltage of the pulldown clock 201225532 is lower than or equal to the low level of the first pull-up clock CKpu-1. The low level voltage of the CKPdJ is lower than or equal to the low of the first carry clock ca-i. Level voltage. The low level voltage of the second pull-down clock CKPd-2 is lower than that of the 帛 帛 触 梅 CK 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 The lower limit of the pulse center k is lower than or equal to the first carry. The figure is a schematic diagram of the shift register circuit of the second embodiment of the present invention. As shown in FIG. 3, the shift storage path includes the outline. Shift register, for convenience of explanation, the shift register circuit 3 only displays the fourth (fourth) stage shift register state, the (th) level shift register 312, the Nth shift The memory 313, the first stage shift register 314 and the _th stage shift register 31S, wherein only the first shift register is invisible to the internal Wei Shanfan architecture, The N-level shift temporary storage benefit 313 ' is not described again. In the operation of the shift register circuit 300, the Nth stage shift register 3 is used to encode according to the first input signal, the second input signal sin2, the first pull-up _ _ 帛 帛Shout CKeaJ, 帛-downward clock CKpd_l, first pull-down complementary clock CKpd-lc, second pull-down clock cKpd_2, second pull-down complementary clock CKpd_2c, third pull-down clock CKpd_3, third pull-down complementary clock CKpd a 3c, a first low power supply voltage vss, a second low power supply voltage Vss2, and a second low power supply voltage Vss3 to generate a driving control voltage VQn, a gate signal SGn and a start pulse signal STn', wherein the first input signal Sin1 can be High power supply voltage V (Jd or 15 201225532 other level shift register drive (4) voltage, gate ^ or start pulse signal 'second input signal Sin2 can be generated for other shifts temporary riding The driving control voltage, the gate signal or the start pulse signal, the second input signal Sin2 can be the same or different from the first input signal Sinl, and the remaining shift register can be analogized analogously. Please note that the third figure所示 所示 帛 帛 上 上 CK CK CK CK CK CK CK CK CK CK CK CK CK CK CK CK CK CK CK The clock CKPU-3 and the fine pull-up CKpu_4 may have the pulse of the chronologically staggered or partially overlapping CKea"n", the third carry clock CKea_3, and the fourth progressive_heart" Alternatively, the pulse may be periodically shifted or partially shifted by 4. In another embodiment, the plurality of shift registers of the shift register circuit 3 (8) may be based on each other. Pulling the clock and reciprocating one of the clocks to perform the gate signal scanning operation. The Nth stage shift register 313 includes the input unit 32A, the carry unit milk, the pull-up unit 330, and the first pull-down The unit 34〇, the second pull-down unit 35〇, and the third pull-down unit 36G. The input unit is configured to output the driving control voltage VQn according to the first input signal and the second input=Sin2. The unit is connected to the interpole and the first pole. The 330 is used to transmit the gate 甙唬SGn according to the driving control voltage VQn and the first pull-up 。, and is electrically connected to the input unit _ The dynamic control voltage VQn and the first carry coffee carry the 325 fine to read the start pulse according to the drive ST 倾 CLK CKea" When the signal is pulled down, the first-traw unit of the input unit 32G is torn according to the first VQn to the first pull-down complementary clock CKpd-1C to drive the control to the first-low power supply (4). The first-down complementary clock CKpd_lc is 201225532 ^the first pulldown clock CKpd". The second pulldown unit 35 electrically connected to the carry unit milk is used to start according to the second pulldown clock CKpd-2 and the second pulldown complementary clock CKpdJe The pulse signal STn is pulled down to the second low power supply (four) plus. The second pull-down complementary clock CXpdJe secrets the second (four) pulse CKpd-2. The third pull-down unit electrically connected to the open drain line is configured to pull the gate signal SGn to the third low power supply voltage Vss3 according to the third pull-down clock CKpd 3 and the third pull-down complementary clock CKpd_3c. The second pull-down complementary clock CKp (J-乂 is inverted to the third pull-down clock CKpd - 3 ° Please note that the first-down complementary clock CKpd-lc and the first pull-down clock CKpd-j may have smoke胄/鲜位赖'帛's two pull-down complementary red mail-& and the second pull-down clock CKpd-2 can have the same high/low level voltage, the third pull-down complementary clock CKPd_3c and the third pull-down clock CKpd_3 It can also have the same high/low level voltage. Fig. 4 is a schematic diagram of a circuit embodiment of the stage shift register of Fig. 3. In the circuit embodiment shown in Fig. 4, The input unit 320 includes a first transistor 321 , the carry unit 325 includes a second transistor 326 , and the pull-up unit 330 includes a third transistor 331 ′. The first pull-down unit 34 〇 includes a fourth transistor 341 and a fifth transistor 342 . The sixth transistor 343, the seventh transistor 344, the eighth transistor 345, and the ninth transistor 346' the second pull-down unit 350 includes a tenth transistor 351, an eleventh transistor 352, and a twelfth transistor 353. a thirteenth transistor 354, a fourteenth transistor 355, and a fifteenth transistor 356' third pull down unit 36 The sixteenth transistor 36, the seventeenth transistor 362, the eighteenth transistor 363, the nineteenth transistor 364, the twentieth transistor 365 17 201225532 and the twenty-first transistor 366. The first transistor 321 The first end, the second end and the gate terminal are included, wherein the first end is configured to receive the first input signal Sin, the second end is used to receive the second input signal (4), and the second end is used to output the driving control voltage VQn. The second transistor 326 includes a first end, a second end and a gate terminal, wherein the first-to-receive receives the first-carry clock CKea, and the second end is used to output the initial pulse signal STn 'the gate is electrically connected to the first- The second end of the transistor 321 . The third transistor 331 includes a first end, a second end and a gate terminal, wherein the first end is used to receive the first-up pull-up ckpu-1, and the second end is electrically connected to the 四 (four) GLn, The terminal is electrically connected to the second end of the first transistor 321 . The fourth transistor 341 includes a first end, a second end and a gate terminal, wherein the first end of the electric whistle -t the second end of the first transistor 321 The terminal is used to receive the control signal SC11 ^- terminal for receiving the first-low power supply voltage. The fifth transistor 342 includes the first The terminal and the gate terminal 'the first end and the gate terminal are used to receive the first pull-down when the second end of the battery 34 is electrically connected to the gate terminal of the fourth transistor 341. The sixth transistor body 34 has one end and the second end And the closed terminal ′, wherein the first end is electrically connected to the fifth terminal, and the second terminal is electrically connected to the second end of the first transistor 321 , and the second two is a low power supply voltage. The seventh transistor 344 includes One end, the first ', the gate extreme, wherein the first end of the electrical connection is used to receive the control fresh sri) # 电曰曰 il between the brother and the gate is used to receive the m-two end and the gate extreme, wherein the first end The complementary clock is CKpd-lc, and the second end is electrically connected to the gate terminal of the seventh transistor 344 of 201225532. The ninth transistor 346 includes a first end, a second end and a gate terminal, wherein the first end is electrically connected to the second end of the eighth transistor 345, and the first end is electrically connected to the second end of the first transistor 321 The two terminals are used to receive the first low supply voltage Vssl. The tenth transistor 351 includes a first end, a second end and a closed end, wherein the first end is electrically connected to the second end of the second transistor 326, the gate end is for receiving the control signal s(3), and the second end is for receiving the first Two low supply voltages Vss2. The eleventh transistor 352 includes a first end, a second end, and a gate terminal, wherein the first end and the gate terminal are configured to receive a terminal between the first pull-down clock CKpd_2 and the first end electrically connected to the tenth transistor 351. The twelfth transistor 353 includes a first end, a second end and a gate terminal, wherein the first end is electrically connected to the second end of the eleventh transistor 352, and the gate terminal is electrically connected to the second end of the first transistor 321 The second end is configured to receive the second low power voltage Vss2. The thirteenth transistor comprises a first end, a second end and a gate terminal, wherein the first end is electrically connected to the second end of the second transistor, the gate end is for receiving the (four) signal SC22, and the second end is for receiving the Two low supply voltages Vss2. The fourteenth transistor 355 includes a first end, a second end and an intermediate end, wherein the first end and the gate receive the second pull-down complementary clock CKpd & the second end is electrically connected to the thirteenth transistor 354 The gate is extreme. The fifteenth transistor 356 includes a first end, a first end, and a gate terminal, wherein the first end is electrically connected to the second end of the fourteenth transistor, and the first end is electrically connected to the second end of the first transistor 321 The second end is configured to receive the second low power voltage Vss2. The sixteenth transistor 361 includes a first end, a second end and a gate terminal, wherein the 201225532 is electrically connected to the gate line GLn, the gate terminal is for receiving the control signal SC31, and the second end is for receiving the third low power source. Voltage Vss3. The seventeenth transistor 362 includes a first end, a second end and an open end 'where the first end and the gate end are for receiving the third pull-down clock CKpd_3, and the second end is electrically connected to the gate end of the sixteenth transistor 361 . The eighteenth transistor 363 includes a first end, a second end and a gate terminal, wherein the first end is electrically connected to the second end of the seventeenth transistor 362, and the gate terminal is electrically connected to the second end of the first transistor 321 The second end is configured to receive the second low power voltage Vss3. The nineteenth transistor 364 includes a first end, a second end and a gate terminal, wherein the first end is electrically connected to the gate line GLn, and the gate _ is received to control the money SC32 'the second end wire receives the third low power voltage Vss3 . The twentieth transistor 365 includes a first end, a second end and a gate terminal, wherein the first end and the gate terminal are used to receive the second pull-down complementary clock CKpd_3e, and the second end is electrically connected to the nineteenth transistor The gate electrode 366 includes a first end, a second end and an intermediate terminal, wherein the first electrode is electrically connected to the second end of the twentieth transistor 365, and the gate terminal is electrically connected to the first electrode body The second end of 321 'the second end is used to receive the third low supply voltage plus.凊Note that the above-mentioned signal-to-signal relationship between the operation of the shift register circuit (10) of the i-th and the second figure can be turned over to the shift temporarily ==:=-stage shift register 313'_ The bit register circuit is more versatile or positive (four) to perform Wei operation, and has low power (four) power consumption and south signal transmission capability (boot fast start) and other operational characteristics. -^ In summary, the present invention can provide low-power signal transmission capability __The shift register of the fine transport wheel == 201225532 can not only meet the requirements of the section (4), but also improve the operational efficiency. In addition, if the shift register circuit is integrated on the display panel including the pixel array to reduce the cost of the system, that is, based on the GOA architecture, the low power wire, the low cake stress and the high signal can be mixed in the transmission capability. Lai (4) board is used at a low operating temperature to extend the panel's life and further improve display quality. The present invention has been disclosed in the above embodiments, and is not intended to limit the invention. Any of the ordinary skill in the art to which the invention pertains can be made without departing from the spirit and scope of the invention. The scope of protection of the present invention is therefore defined by the scope of the appended claims. Field [Simplified Description of the Drawings] Fig. 1 is a schematic diagram of a shift register circuit according to a first embodiment of the present invention. Figure 2 is a schematic diagram of a circuit embodiment of the Nth stage shift register of Figure 1. Figure 3 is a schematic diagram of a shift register circuit in accordance with a second embodiment of the present invention. 4 is a schematic diagram of a circuit embodiment of the Nth stage shift register of FIG. [Main component symbol description] 100, 300 shift register circuit 111, 311 (N-2)-stage shift register 112, 312 (N-1)-stage shift register 113, 313 N Stage shift register 114, 314 (N+1) stage shift register 21 201225532 115 120 121 125 126 130 131 140 141 142 143 144 145 150 151 152 153 154 155 160 161 162 315 (N+ 2) Stage shift register 320 Input unit 321 First transistor 325 Carry unit 326 Second transistor 330 Pull-up unit 331 Third transistor 340 First pull-down unit 341 Fourth transistor 342 Fifth transistor 343 Sixth transistor 344 seventh transistor 345 eighth transistor 350 second pull-down unit 346 ninth transistor 351 tenth transistor 352 eleventh transistor 353 twelfth transistor 354 thirteenth transistor 360 third Pull-down unit 355 fourteenth transistor 356 fifteenth transistor
22 201225532 163、361 第十六電晶體 164、362 第十七電晶體 165 ' 363 第十八電晶體 364 第十九電晶體 365 第二十電晶體 366 第二十一電晶體 CKca_l 第一進位時脈 CKca一 2 第二進位時脈 CKca—3 第三進位時脈 CKca—4 第四進位時脈 CKpd_l 第一下拉時脈 CKpd_lc 第一下拉互補時脈 CKpd_2 第二下拉時脈 CKpd_2c 第二下拉互補時脈 CKpd—3 第三下拉時脈 CKpd—3 c 第三下拉互補時脈 CKpul 第一上拉時脈 CKpu—2 第二上拉時脈 CKpu_3 第三上拉時脈 CKpu 一4 第四上拉時脈 GLn-2、GLn_l、 閘極線 GLn、GLn+l、GLn+2 s. 23 201225532 sen、SC2、SC3、 控制訊號 sen、SC12、SC2卜 SC22 ' SC31 ' SC32 SGn-2 > SGn-1 ' 閘極訊號 SGn'SGn+1 'SGn+2 Sinl 第一輸入訊號 Sin2 第二輸入訊號 VQn 驅動控制電壓 Vssl 第一低電源電壓 Vss2 第二低電源電壓 Vss3 第三低電源電壓 2422 201225532 163, 361 16th transistor 164, 362 17th transistor 165 ' 363 18th transistor 364 19th transistor 365 20th transistor 366 21st transistor CKca_l First carry Pulse CKca-2 Second Carry Clock CKca-3 Third Carry Clock CKca-4 Fourth Carry Clock CKpd_l First Pulldown Clock CKpd_lc First Pulldown Complementary Clock CKpd_2 Second Pulldown Clock CKpd_2c Second Pulldown Complementary clock CKpd-3 third pull-down clock CKpd-3 c third pull-down complementary clock CKpul first pull-up clock CKpu-2 second pull-up clock CKpu_3 third pull-up clock CKpu a 4 fourth Pull clock GLn-2, GLn_l, gate line GLn, GLn+l, GLn+2 s. 23 201225532 sen, SC2, SC3, control signal sen, SC12, SC2 BU SC22 'SC31 'SC32 SGn-2 > SGn -1 ' Gate signal SGn'SGn+1 'SGn+2 Sinl First input signal Sin2 Second input signal VQn Drive control voltage Vssl First low supply voltage Vss2 Second low supply voltage Vss3 Third low supply voltage 24