201230245 六、發明說明： 【發明所屬之技術領域】 本發明係有關-種域電路_連線製作方法，_是指—種同步形 成銀内連線之擴散阻障層與電鍍晶種層的方法。 【先前技術】 目前用來形成集成電路之銅合金鱗線如金祕及介層窗（也）的方 法稱為鑲嵌（dam_e) ’其綠是时電層〇彡成㈣，齡電層是用來 分隔垂直間隔的金屬層，後，於開D内依序形成—擴散阻障層與—銅晶 種層，擴散轉層是时防止銅擴散至_介電射，峨晶種層是用ϋ 利於後續銅或銅合金填充於開口内之銅紐晶種層。最後，侧電錄方式 將銅或銅合金填充於開π内’並進行化學機械研磨製程，移除多餘的又喊 銅合金’即完成内連線製程。201230245 VI. Description of the Invention: [Technical Field] The present invention relates to a method for fabricating a seed-area circuit, and a method for simultaneously forming a diffusion barrier layer of a silver interconnect and a plating seed layer . [Prior Art] The current method for forming copper alloy scales such as gold secrets and vias (also) for integrated circuits is called damascene (dam_e) 'its green is the time layer (4), and the age layer is used. To separate the vertically spaced metal layers, and then form a diffusion barrier layer and a copper seed layer in the opening D. The diffusion layer is to prevent copper from diffusing to the dielectric beam, and the germanium seed layer is used for the germanium. Conducive to subsequent copper or copper alloy filling in the opening of the copper button seed layer. Finally, the side-circuit recording method fills the copper or copper alloy in the open π and performs a chemical mechanical polishing process to remove the excess copper alloy, which completes the interconnect process.
但在日益微縮的製程要求下，縣的銅製程纽製程上與電性上的版 頸，舉例來說：i.在電性方面，當導線尺度日益減少但作為阻障層（例如 組/氮化組）的厚度維持不請，使得㈣鋼或鋼合金的部分_減少，有 效電阻相對提高’失去低阻值優勢；2•在製程方面，當導線尺度日賊少時， 若作為阻障層（例純/統㈣的厚度轉不變，將使得銅晶種層的製程 條件變得相對嚴苛，以目前物理氣相沈積法（pvD)製作晶種層時的表面 批^ co職ge)程度，已無法滿足需求，相對造成後續電鑛結果的 失敗例如產生孔洞，3.在材料選擇方面，—些新的擴散阻障層製程技術像 原子層沈魏她（缝_、__了（ald_Ru)或者化學氣相 沈贿（⑽句等，除了阻值高外，阻障效果也不佳，即使採用，還是 201230245 需要搭配極薄的晶種層’因此減性不佳的問題補存在。再者，雖然有 新的電鑛促進層的研發’解決了在批覆不佳的情況下的電鑛施行成效，但 疋在此方式下仍需要依靠物理氣相沈積法來形成極薄的晶種層，而且阻值 上也因多了 14層電鍍促進層而提高，@此在孔麻小的情況下，還是面臨 到極大的挑戰。 銀金屬具有較銅低的電阻率，被視為可能取代銅成為新的金屬導線材 料之-。有鑑於此’本發明遂針對上利知技術之缺失，針對未來銀導線 製程所面臨更嚴苛_境’提出—鋪新關步形成朗連線之擴散阻障 層與電種層的方法，以有效克服上述之該等問題。 【發明内容】 曰本發敗主要目的在提供—_步形成勘連線之舰啡層與電楚 明種層的n其藉崎料設計與反賴制，賴處理製辦，由於人金 材料在銀中_祕隨溫奸高町降析出，這麟合勤學現象的㈣ 刀=不僅同時且等向均勻。添加的合金在升溫過程巾-邊㈣，一邊與其 田夕層或疋自錯層反應，形輕化物或是録化物，可作為銀的擴散阻障 用相對原來銀合金裏的銀純度升高，可作為後續電鑛之 且厚度是料均⑽分佈。 _之用 晶種_她—瓣臟罐轉層與電鑛 入：寬 路。 心後績電__性’能適用於微縮化後的集成電 本發明之再一目 的在提供-_步軸朗連線之_轉層與電鑛 201230245 晶種層的方法，其減少了擴散阻障層的製作流程與成本，也提高元件製作 速度。 為達上述之目的，本發明提供—制步形成軸連線之擴散阻障層與 電鑛晶種層的妓’其包含有下列步驟：魏，提供—基底，並於基底上 形成一介電層；隨後，於介電層中形成__開σ，並於開σ内依序形成一富 .㈣與—銀合金晶以及進行_熱處理步驟，崎銀合金晶種層中的 彳由銀巾刀離’並且合金材料擴散至銀合金晶種層之底表面，並與 籲富石夕層反應形成石夕化物層，以作為一擴散阻障層，銀合金晶種層中的銀作 為電鑛晶種；電鑛填充-銀材料於開口中；以及執行一平坦化步驟，以移 除覆蓋在介電層上的多餘銀材料。 上述之富石夕層可以用富錄層取代。當以富鍺層取代時，合金材料擴散 至銀口金層之底表面後將與富錯層反應形成錯化物層。 底下藉由具體實施例詳加說明，當更容易瞭解本發明之目的、技術内 谷、特點及其所達成之功效。 • 【實施方式】 本發月有鑑於集成電路製程技術的微縮化，選擇—個合適的新金屬導 線材料’銀’並祕適當的銀合金晶種層材料設計航應機制，再藉由熱 處製程使銀。金曰曰種層内之合金與銀基材分離，以同時且等向均句的形 成電锻晶種層與擴散阻障層，進而減少了擴散阻障層的製作流程與成本， 南元件製作速度。再者，由於少了—道製程，相對電鑛液流入空間變 寬可大大減j/後續電鍍的困難性。另外，這銀合金晶種層的厚度可以從 製程條件來精準控制’相對可靠度高，能與現有製程技術相容。另一方面 201230245 也減少設備成本的支出。 :下，係舉兩個實施例來說明本發明，但並不因此紐本發明的範圍。 一 帛（a)第1 (g) ® ’其係本發明之-實施例的各步驟剖面 丁意圓首先&第1(a)圖所示，提供—基底⑺，叾中此基底之材 質為石夕或錯，並於基底ω上形成—介電層12。隨後，如第i㈦圖所示， 形成一開σ 14於該介電層12中。再如第1⑷圖所示，於開口 14内沈積 一非結晶销16或者非結晶錯層，來作為富骑或者富錯層。如第i⑷ 圖所示，於賴晶销16或者賴晶騎上形成-終金晶_ 18’其中 銀合金_ 18包含核合金_成合金_金_(_峨llic 她_。在本發财所翻材金編_，合金材料職下方是非 結晶賴她編麵㈣。舉細，#侧讀料為辦， 銀口金明種層中的合金材料可選自於姑（c。）、鉻⑼、翻（M。）、銳⑽）、 2⑽’（Pt)，㈤、鈦㈤、飢W、鶴（W)或者錯（Zr)。 層之材料為錯時，銀合金晶種層中的合金材料可選自於錯（办）、銳 ⑽、鈕㈤、鉬(Mo)、鎳⑽、鉑(Pt)、鈷(Co)、鉻⑹或鋼 (Cu)。此外，銀合金晶種層18的形成方式是利用物理氣相沈積法（p奶）、 化學氣相沈積法（CVD)、原子層沈積法（ald)或者濕式製程。 接續，如第1 (e)圖所示，進行一熱處理步驟，以將銀合金晶種層18 中的。金材料φ作絲材金屬材料的射分離，並且合金材料擴散至銀合 金^晶 層 18 ^ rk. Μ. αχ 、 -表面’並與富石夕層或者富鍺層反應形成石夕化物層20或者 鍺化物層’ W作為-擴散_層，隨著銀合金晶種層18中的合金材料擴散 後’剩下的富銀層22則作為電鑛晶種層。如第1⑴圖所示，贿作為電 201230245 鑛晶種層’電職—銀材料μ於㈣且此銀_蓋㈣或者富錯 =雖贫、在第1 (e)圖中，有描綠出銀合金晶種層因熱處理形成—石夕化 物層2〇與一紐層22 ’或者是鍺化物層與富銀層，但在第丨⑴圖中，因 為富銀層22與败銀材料24二者是相同的材料，因此二者間可能無法 區隔，所以並沒有無描繪出銀晶種層。最後，如第ι⑷圖所示，執行— 平坦化轉，崎恤糊增餘獅細則成電路内 連線之銀導線26。 • 上述之熱處理步驟的溫度是靴〜職，處理時間為i秒〜60分鐘。 請參閱第2 (a)〜第2⑷圖，其縣發明之另-實施_各步驟剖 面示意圖。此實施例與上述實施例之差異在於富销或者富鍺層的製作方 法’鑑此對於細部製㈣分可參社述實__述，在此料再重複進 行贅述。 首先’如第2 (a)圖所示，提供一半導體基底3〇，並於基底3〇上形 成-介電層32。隨後，如第2㈦圖所示，形成—開口 ％於介電層32中。 再如第2⑷圖所示’離子植人方式對自開π 34顯露出之介電層32 與基底30進行矽離子佈值，以形成一石夕離子植入層允，來作為富石夕層。當 然此處的矽離子也可使用錯離子取代。 接續’如第2 (d)圖所示’於石夕離子植入層36上形成一銀合金晶種層 38。再如第2 (e)圖所示，進行一熱處理步驟，以將銀合金晶種層38中的 合金材料由作為基材金屬材料的銀中分離，並且合金材料擴散至銀合金層 之底表面，並與石夕離子植入層36反應形成石夕化物層40，以作為一擴散阻障 層，銀合金晶種層中的富銀層42則作為電鍍晶種層。如第2 (f)圖所示， 201230245 層乍為電鑛B曰種層，電鑛填充一銀材料44。最後，如第2⑷圖所 丁平化步驟，以獲得作為集成電路内連線之銀導線邮。 上述之熱處理步驟的溫度是賊〜聊，處理時間為〗秒〜⑼分鐘。 -本發明巧妙地翻絲溫巾對銀金屬個溶量之金屬，與石夕或 緒反應後_输_，姆嫩罐，綱製程良率並 減少製程程序，降低成本。 本發月藉由熱處理製程時’銀合金晶種層中的合金材料在銀中的固溶 限隨溫度升高下降而析出，這鋪力學現㈣元素分離不制時且等向均鲁 勻的現象T添加的合金在升溫過財—邊析出，-邊與其下富發層或是 富錄層反應，形成石夕化物或是錯化物，來作為銀的擴散阻障層之用。相對However, under the increasingly narrow process requirements, the county's copper process and the plate neck, for example: i. In terms of electrical, when the wire scale is decreasing, but as a barrier layer (such as group / nitrogen) The thickness of the chemical group is not maintained, so that (4) the steel or steel alloy part is reduced, the effective resistance is relatively increased, and the low resistance value is lost. 2. In the process, when the wire scale is small, if it is used as a barrier layer (In the case of pure/systematic (four) thickness, the process conditions of the copper seed layer will become relatively harsh, and the surface batch of the seed layer will be produced by the current physical vapor deposition (pvD) method) The degree has been unable to meet the demand, which has caused the failure of subsequent electric ore results, such as the creation of holes. 3. In terms of material selection, some new diffusion barrier process techniques like atomic layering Wei Wei (seam _, __ ( ald_Ru) or chemical vapor bribery ((10) sentence, in addition to the high resistance, the barrier effect is not good, even if it is used, 201230245 needs to be matched with a very thin seed layer', so the problem of poor reduction complements. Furthermore, although there are new electric ore promoting layers The hair 'resolved the effect of the implementation of the electric ore in the case of poor approval, but in this way, it still needs to rely on physical vapor deposition to form a very thin seed layer, and the resistance is also increased by 14 layers. The plating promotion layer is improved, and this is still facing great challenges in the case of small pores. Silver metal has a lower resistivity than copper and is considered to be a potential replacement for copper as a new metal wire material. This invention is aimed at the lack of the above-mentioned technology, and proposes a new method for forming a diffusion barrier layer and an electric seed layer for the future connection of the silver wire process. Overcoming the above-mentioned problems. [Summary of the Invention] The main purpose of the 发 发 发 在 在 在 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要In the case of the establishment of the gold material in the silver _ secret with the rape of Gaocho, the phenomenon of this symbiosis (4) knife = not only at the same time and uniformity. The added alloy in the heating process towel - side (four), while Tian Xi layer or 疋 self-replacement layer reaction, light form or It is a recorded material, which can be used as a diffusion barrier for silver. The purity of silver in the original silver alloy is increased, and it can be used as a subsequent electric ore and the thickness is the distribution of the material (10). _ The seed crystal _ she-valve can turn layer With the electric mine into: wide road. After the heart __ sex 'can be applied to the integrated electric after the miniaturization of the present invention, another purpose of the invention is to provide -_ step axis lang connection _ transfer layer and electric mine 201230245 seed crystal The layer method reduces the fabrication process and cost of the diffusion barrier layer, and also improves the component fabrication speed. To achieve the above object, the present invention provides a diffusion barrier layer and an electromineral seed layer for forming a shaft connection. The crucible includes the following steps: Wei, providing a substrate, and forming a dielectric layer on the substrate; subsequently, forming a __open σ in the dielectric layer and sequentially forming a rich in the σ. (4) With the silver alloy crystal and the heat treatment step, the crucible in the silver alloy seed layer is separated from the silver towel knife and the alloy material diffuses to the bottom surface of the silver alloy seed layer, and reacts with the Yufushi layer to form a stone. An yttrium layer for use as a diffusion barrier layer in silver in a silver alloy seed layer The seed crystal is electro-mine; the electro-mineral fill-silver material is in the opening; and a planarization step is performed to remove excess silver material overlying the dielectric layer. The above-mentioned rich layer can be replaced by a rich layer. When replaced with a ruthenium-rich layer, the alloy material diffuses to the bottom surface of the silver-plated gold layer and reacts with the impurity-rich layer to form a staggered layer. The details of the present invention, the characteristics of the technology, the characteristics, and the effects achieved by the present invention will be more readily understood by the detailed description of the specific embodiments. • [Implementation] In this month, in view of the miniaturization of integrated circuit process technology, we chose a suitable new metal wire material 'silver' and the appropriate silver alloy seed layer material to design the aviation response mechanism, and then by the heat The process makes silver. The alloy in the gold bismuth layer is separated from the silver substrate to form an electrically forged seed layer and a diffusion barrier layer at the same time and in the same direction, thereby reducing the production process and cost of the diffusion barrier layer. speed. Moreover, due to the lack of the process, the relative inflow of the electro-mineral liquid can greatly reduce the difficulty of subsequent plating. In addition, the thickness of the silver alloy seed layer can be precisely controlled from process conditions. 'The relative reliability is high and compatible with existing process technologies. On the other hand, 201230245 also reduces the cost of equipment costs. In the following, two embodiments are described to illustrate the invention, but are not intended to limit the scope of the invention. A (a) 1 (g) ® 'is a part of the steps of the present invention - an embodiment of the first embodiment of the first & 1 (a), providing a substrate (7), the material of the substrate It is a stone or a fault, and a dielectric layer 12 is formed on the substrate ω. Subsequently, as shown in the i-th (seventh) diagram, an opening σ 14 is formed in the dielectric layer 12. Further, as shown in Fig. 1(4), a non-crystalline pin 16 or an amorphous layer is deposited in the opening 14 as a rich or misaligned layer. As shown in the figure i(4), the Lai Jingpin 16 or Lai Jing rides on the formation - the final gold crystal _ 18' where the silver alloy _ 18 contains the nuclear alloy _ alloy _ gold _ (_ 峨llic her _. in this fortune Turning the gold _, the alloy material is below the non-crystallized Lai her face (four). Lifting fine, # side reading for the office, the alloy material in the Yinkou Jinming seed layer can be selected from Yu (c.), chromium (9), Turn (M.), sharp (10)), 2 (10) '(Pt), (5), titanium (five), hunger W, crane (W) or wrong (Zr). When the material of the layer is wrong, the alloy material in the silver alloy seed layer may be selected from the group consisting of ergo, sharp (10), button (5), molybdenum (Mo), nickel (10), platinum (Pt), cobalt (Co), chromium (6). Or steel (Cu). Further, the silver alloy seed layer 18 is formed by physical vapor deposition (p milk), chemical vapor deposition (CVD), atomic layer deposition (ald) or wet process. Next, as shown in Fig. 1(e), a heat treatment step is performed to deposit the silver alloy in the seed layer 18. The gold material φ is used for the separation of the wire metal material, and the alloy material diffuses to the silver alloy layer 18 ^ rk. Μ. α χ , - surface 'and reacts with the eutectic layer or the yttrium-rich layer to form the lithium layer 20 Alternatively, the telluride layer 'W acts as a diffusion layer, and the remaining silver-rich layer 22 acts as an electromineral seed layer as the alloy material in the silver alloy seed layer 18 diffuses. As shown in Figure 1(1), bribe as electricity 201230245 mineral seed layer 'electricity-silver material μ in (four) and this silver_cover (four) or rich error = poor, in the first (e) figure, there is a green The silver alloy seed layer is formed by heat treatment—the lithium layer 2〇 and the one layer 22' or the bismuth layer and the silver-rich layer, but in the figure (1), because the silver-rich layer 22 and the silver-stained material 24 The same material, so the two may not be separated, so there is no silver layer. Finally, as shown in Figure ι(4), the implementation - flattening, the singularity of the lions into the circuit of the silver wire 26 in the circuit. • The temperature of the above heat treatment step is the boots-to-job, and the processing time is from i seconds to 60 minutes. Please refer to the second (a) to (2)th drawings, and a schematic cross-sectional view of each of the county inventions. The difference between this embodiment and the above embodiment lies in the method of producing a rich or rich layer. This is described in detail for the detailed system (four), which is repeated here. First, as shown in Fig. 2(a), a semiconductor substrate 3 is provided, and a dielectric layer 32 is formed on the substrate 3. Subsequently, as shown in the second (seventh) diagram, the opening % is formed in the dielectric layer 32. Further, as shown in Fig. 2(4), the ion implantation method is performed on the dielectric layer 32 exposed from the π 34 and the substrate 30 to form a cerium ion implantation layer. Of course, the cerium ions here can also be replaced with a wrong ion. Next, a silver alloy seed layer 38 is formed on the Shixia ion implantation layer 36 as shown in Fig. 2(d). Further, as shown in FIG. 2(e), a heat treatment step is performed to separate the alloy material in the silver alloy seed layer 38 from silver as a base metal material, and the alloy material is diffused to the bottom surface of the silver alloy layer. And reacting with the Shiyue ion implantation layer 36 to form the lithium layer 40 as a diffusion barrier layer, and the silver-rich layer 42 in the silver alloy seed layer serves as a plating seed layer. As shown in Figure 2 (f), the 201230245 layer is an electric ore B layer, and the electric ore is filled with a silver material 44. Finally, the step of flattening as shown in Figure 2(4) is to obtain a silver wire mail as an interconnect of the integrated circuit. The temperature of the above heat treatment step is thief ~ chat, the processing time is 〖seconds ~ (9) minutes. - The invention ingeniously rewinds the temperature of the silver metal to the metal of the molten metal, and after the reaction with Shi Xi or _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ In the current heat treatment process, the solid solution limit of the alloy material in the silver alloy seed layer in silver is precipitated as the temperature rises, and the mechanical properties are (4) when the elements are separated and the isotropic is uniform. The alloy added by the phenomenon T is precipitated when it is heated up, and reacts with the lower rich layer or the rich layer to form a litmus compound or a staggered compound, which is used as a diffusion barrier layer for silver. relatively
的原來銀。金03種層裏的銀純度升高，可作為後續電鑛之晶種層之用。且 厚度是等向均勻的分佈D 唯以上所述者’僅為本發明之較佳實施例而已，並非用來限定本發明 實施之範圍。故即凡依本發明申請範圍所述之特徵及精神所為之均等變化 或修飾，均應包括於本發明之申請專利範圍内。 · 【圖式簡單說明】 第1 U)〜第1 (g)圖係本發明之_實施例的各步驟剖面示意圖。 第2⑷〜第2 (g)圖係本發明之另—實施例的各步驟剖面示意圖。 【主要元件符.號說明】 1〇基底 12介電層 14開口 8 201230245 16非晶矽層 18銀合金晶種層 20矽化物層 22 富銀層 24銀材料 , 26銀導線 30基底 φ 32介電層 34 開口 36矽離子植入層 38銀合金晶種層 40 >5夕化物層 42富銀層 44銀材料 • 46銀導線The original silver. The purity of silver in the gold 03 layer is increased and can be used as a seed layer for subsequent electric ore. And the thickness is an isotropic uniform distribution D. The above description is only a preferred embodiment of the present invention and is not intended to limit the scope of the practice of the present invention. Therefore, any changes or modifications of the features and spirits of the present invention should be included in the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS The first U) to the first (g) are schematic cross-sectional views of respective steps of the embodiment of the present invention. 2(4) to 2(g) are schematic cross-sectional views showing respective steps of another embodiment of the present invention. [Main component symbol. No. description] 1 〇 substrate 12 dielectric layer 14 opening 8 201230245 16 amorphous enamel layer 18 silver alloy seed layer 20 bismuth layer 22 silver-rich layer 24 silver material, 26 silver wire 30 substrate φ 32 Electrical layer 34 opening 36 矽 ion implantation layer 38 silver alloy seed layer 40 > 5 夕 layer 42 silver rich layer 44 silver material • 46 silver wire