TW201250923A - Pre-cut wafer applied underfill film - Google Patents

Pre-cut wafer applied underfill film Download PDF

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Publication number
TW201250923A
TW201250923A TW101103275A TW101103275A TW201250923A TW 201250923 A TW201250923 A TW 201250923A TW 101103275 A TW101103275 A TW 101103275A TW 101103275 A TW101103275 A TW 101103275A TW 201250923 A TW201250923 A TW 201250923A
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Taiwan
Prior art keywords
wafer
underfill
tape
dicing
semiconductor
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TW101103275A
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English (en)
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TWI528498B (zh
Inventor
Youn-Sang Kim
Gina Hoang
Rose Guino
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Henkel Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W95/00—Packaging processes not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6302—Non-deposition formation processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7402—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7402—Wafer tapes, e.g. grinding or dicing support tapes
    • H10P72/7404—Wafer tapes, e.g. grinding or dicing support tapes the wafer tape being a laminate of three or more layers, e.g. including additional layers beyond a base layer and an uppermost adhesive layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/012—Manufacture or treatment of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7416—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7422—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7438—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support with parts of the auxiliary support remaining in the finished device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors

Landscapes

  • Mechanical Treatment Of Semiconductor (AREA)
  • Dicing (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Description

201250923 六、發明說明： 【發明所屬之技術領域】 本發明係關於製作半導體晶粒之方法。 本申請案主張2011年2月1曰提出申請之美國臨時專利申 . 請案第61/438,327號之權利，該案件之内容以引用方式併 入本文中。 【先前技術】 電設備及電子設備之微型化及輕量化已導致需要較薄半 導體裝置及較薄半導體封裝。一種製造較薄半導體晶粒之 方式係自晶粒之背側（非活性側）移除過量材料。此藉由自 切割出個別晶粒之半導體晶圓之背側移除過量材料更容易 元成。過量晶圓之移除通常出現於研磨過程（通常稱作背 側研磨）中。 一種製造更小且更有效半導體封裝之方式係採用具有附 接至封裝之作用面之金屬凸塊陣列的封裝。金屬凸塊經佈 置以與基板上之結合墊匹配。在金屬回流成熔體時，其與 結合墊連接，形成電連接及機械連接二者。此金屬凸塊封 裝通常稱作「覆晶」，此乃因凸起之半導體經翻轉以附接 • 至其基板。 • 在半導體與基板間存在熱失配，使得在重複熱循環下對 金屬互連件施加應力’從而潛在地導致失效。為抵消此問 題，將囊封材料（通常稱作底部填充料）佈置於半導體與基 板間圍繞金屬凸塊之空隙中。 半導體封裝製作中之當前趨勢偏好以晶圓級完成盡可能 16I796.doc 201250923 多之製程步驟’允許同時處理多個積體 粒個體化後所發生的那樣個別地處理。 研磨步驟中薄化晶圓時，底部填充料施 晶圓級處理，此乃因處置由於薄化晶圓 至更困難。 電路， 而非如同晶 不幸的是，尤其在 加不能充分適宜於 之易碎性而變得甚 圓級底部填充材 因此’需要不會損害晶圓之脆性之將晶 料施加至薄化晶圓的方法。 【發明内容】 本發明係關於製造施加底部填充料之薄化半導體的方 法’該方法包含：⑷提供半導體晶圓’該半導體晶圓之頂 部側上面具有複數個金屬凸塊及視情況垂直穿㈣晶^ 矽通孔；（b)將背研磨膠帶層壓至該晶圓頂部，覆蓋該等金 =凸塊及料孔：⑷薄化該晶圓之背側；（d)將切割膠帶 安裝至薄化晶圓之背側並將該矽晶圓及切割膠帶安裝至切 割框；（e)移除背研磨膠帶；⑴提供預切割成晶圓形狀之 底部填充材料；（g)使該底部填充料與該晶圓對準並將該 部填充料層壓至該晶圓。 — 【實施方式】 晶圓係半導體材料，通常為梦、钟化鎵、鍺或類似化合 物半導體材料。根據工業文獻中充分記載之半導體及金屬 製作方法在晶頂部側上形成複數個金屬凸塊及其金屬成 份0 出於將電路自一個晶圓連接至另一晶圓之目的，矽通孔 係完全延伸貫穿矽晶圓之垂直通道。 161796.doc 201250923 本發明方法中所用之切割膠帶的目的係在切割操作期間 支撐晶圓。切割膠帶可自多個來源購得且在一種形式中係 由載體上之熱敏性、壓敏性或uv敏感性黏著劑組成。載 體通常係聚烯烴或聚醯亞胺之撓性基板。在分別施加熱、 拉應變或uv時，黏著性降低。通常，釋放襯墊覆蓋黏著 層且可在即將使用切割膠帶之前容易地移除。 者研磨膠帶之目的係在晶圓薄化過程期間保護並支撐金 屬凸塊及晶圓之頂部表面。背研磨膠帶可自多個來源購得 且在一種形式中係由載體上之熱敏性、壓敏性或uv敏感 性黏著劑組成《載體通常係聚烯烴或聚醯亞胺之撓性基 板。在分別施加熱、拉應變或uv時，黏著性降低。通 常’釋放襯墊覆蓋黏著層且可在即將使用背研磨膠帶之前 合易地移除。可藉由機械研磨、雷射研磨或链刻實施背研 磨操作。 已知適於作為可呈膜形式之底部填充料化學物質的黏著 劑及囊封劑’如同製造底部填充膜之方法_樣。底部填充 材料之厚度可經調節’以便可在層壓後完全或僅部分覆蓋 金屬凸塊。在任—情形下’供應底部填充材料以使盆完全 填充半導體與預期基板間之空間。在一個實施例中，在載 體上提供底部填充材料並將其用釋放襯墊保護。因此，將 以三層形式提供底部填充材料，其中順序為第―層係載 體’例如撓性聚烯烴或聚醯亞胺膠帶，第二層係底部填充 材料'，且第三層係釋放襯墊。在即將使用之前，移除釋放 襯塾並通常在底部填充料仍附接至載體時施加底部填充 161796.doc 201250923 料。在將底部填充料施加至晶圓後，移除載體。 參照該等圖進一步闡述本發明。在該等圖中，可以石夕晶 圓之作用面（含有金屬凸塊之面）向上或向下定向來顯示切 割膠帶、矽晶圓、金屬凸塊、底部填充料及背研磨膠帶中 之一或多個元件之總成。可以由專業人員確定之任一定向 處理§亥總成。切割膠帶、背研磨膠帶及底部填充料中之每 一者均顯示無釋放襯墊◊在載體上提供切割膠帶及背研磨 膠帶且在使用後丟棄。彼等熟習此項技術者應理解，通常 使用釋放襯墊來保護切割膠帶或背研磨膠帶之壓敏性黏著 劑，且在即將使用前移除釋放襯墊。繼續對層壓於晶圓之 活性侧上之底部填充層實施切割及結合步驟。 圖la及lb繪示製備具有由底部填充料支撐之金屬凸塊的 薄化石夕晶圓之第-先前技術方案。製備在碎晶圓之一個面 (作用面)上具有金屬凸塊"之矽晶圓1〇。用膠帶覆蓋金 屬凸塊11以在晶圓薄化期間保護晶圓之作用面。膠帶通常
稱作背研磨膠帶。薄仆a間+办^ L 存化®之背側以產生薄化晶圓13。在 移除背研磨膠帶時，故a 士北 ^ 令將具有者研磨膠帶12之薄化晶圓13放 置於真工夾盤σ 17上。將底部填充材料“層壓於晶圓之作 用面上k而圍繞並囊封金屬凸塊丄丄。將切割膠帶Μ安裝 於晶圓之薄化背侧卜，Η μ μ 上且隨後將晶圓放置於切割框（或夾 具）16中用於隨德切射 成個別半導體。此方法之缺點在於 在移除背研磨膠帶後，a ^ aa圓易碎且在將晶圓層壓於切割膠 帶上並放置於切割框中上_ T之則其未受到支撐。 圖2a及2b繪示製備且古 有具有由底部填充料支撐之金屬凸塊的 161796.doc 201250923 薄化石夕晶圓之第二先前技術方案。製備在石夕晶圓之一個面 (作用面）上具有金屬凸塊11之矽晶圓10。用保護性背研磨 膠帶12覆蓋金屬凸塊丨丨。薄化晶圓之背側以產生薄化晶圓 13。將切割膠帶15安裝於晶圓之背側上，且將晶圓放置於 真空夾盤台20上之切割框16中。將底部填充材料〗4層壓於 晶圓之作用面上，從而圍繞並囊封金屬凸塊丨丨。此方法之 缺點在於底部填充材料在界面18處連接切割框，從而導致 在層壓期間在底部填充料中起皺。 圖3a及3b繪示製備具有由底部填充料支撐之金屬凸塊的 4化矽B曰圓之第二先前技術方案。製備在矽晶圓之一個面 (作用面）上具有金屬凸塊1 1之石夕晶圓1 〇。在石夕晶圓之作用 面上佈置兩層膠帶19(其中一層係保護性背研磨膠帶12且 第二層係底部填充材料丨4) ’其中底部填充層與金屬凸塊 η接觸並覆蓋其。薄化晶圓之背側以產生薄化晶圓13。將 切割膠帶15安裝於晶圓之背側上，且將晶圓放置於真空夾 盤台20上之切割框16中。移除兩層膠帶19中之背研磨膠帶 層12’留下底部填充材料14。此方法之缺點係背研磨膠帶 與底部填充材料間之相互作用。背研磨膠帶對底部填充層 之黏著力可比底部填充層對晶圓之黏著力強。此可造成在 移除背研磨穋帶期間底部填充層自晶圓卿。另外，晶圓 之均句薄化可受到背研磨膠帶之厚度變化的影響。當底部 填充料之厚度變化與背研磨膠帶之厚度變化相加時，總厚 度變化增加且對薄化後之晶圓厚度之均句性具有甚至更大 的有害影響。 161796.doc 201250923 圖4a及4b繪示本發明方法：製備具有複數個金屬凸塊" 及可選梦通孔21之厚《ε夕晶圓1 〇。將保護性背研磨膠帶12層 壓於金屬凸塊及矽晶圓之頂部表面上。將用以在隨後切割 期間支撐薄化晶圓之切割膠帶1 5安裝於薄化晶圓之背側。 將具有切割膠帶1 5及背研磨膠帶1 2之晶圓13安裝至切割框 16中’其中晶圓之頂部側面向上且切割膠帶與切割框接 觸。移除背研磨膠帶。提供在一側上具有底部填充材料j 4 之載體膠帶17。預切割底部填充材料丨4以配合晶圓之頂部 表面。使底部填充料與晶圓接觸，使形狀對準，並在载體 仍完好之情況下層壓至晶圓之作用面（具有金屬凸塊）。在 進一步處理之前移除載體。 因此，在一個實施例中’本發明係關於製造施加底部填 充料之薄化半導體晶圓的方法’其包含：（a)提供半導體晶 圓，s亥半導體晶圓之頂部側上面具有複數個金屬凸塊及視 情況垂直穿過矽晶圓之矽通孔；（b)將背研磨膠帶層壓至該 晶圓頂部，覆蓋該等金屬凸塊及矽通孔；（c)薄化該晶圓 之背側；（d)將切割膠帶安裝至薄化晶圓之背側並將該矽晶 圓及切割膠帶安裝至切割框；（e)移除背研磨膠帶；⑴提 供預切割成晶圓形狀之底部填充材料；（幻使該底部填充料 與該晶圓對準並將該底部填充料層壓至該晶圓。 此方法具有兩個主要優點：（〇在整個製作步驟期間，薄 化晶圓係由背研磨膠帶或切割膠帶或二者支撐，及（ii)由 於底部填充料經預切割成晶圓形狀，故底部填充料不會碰 才里切割框’從而消除在底部填充料層壓至晶圓期間起皺或 161796.doc 201250923 產生空隙之任何可能性。 【圖式簡單說明】 圖la及lb連續地繪示製備具有由底部填充料支撐之金屬 凸塊的薄化矽晶圓之第一先前技術方案。 圖2a及2b連續地繪示製備具有由底部填充料支撐之金屬 凸塊的薄化矽晶圓之第二先前技術方案。 之金屬 圖仏及4b連續地繪示製備具有由底部填充料支樓 凸塊的薄化矽晶圓之本發明方案。 【主要元件符號說明】 10 矽晶圓 11 金屬凸塊 12 背研磨膠帶 13 薄化晶圓 14 底部填充材料 15 切割膠帶 16 切割框（或夾具） 17 載體膠帶 18 界面 19 兩層膠帶 20 真空夾盤台 21 矽通孔 161796.doc

Claims (1)

  1. 201250923 七、申請專利範圍： 1 一種製造施加底部填充料之薄化半導體晶圓的方法，其 包含： (a)提供半導體晶圓，該半導體晶圓在其頂部側上具 有複數個金屬凸塊’及視情況垂直穿過該矽晶圓之矽通 孔； (b) 將背研磨膠帶層壓至該晶圓之該頂部 等金屬凸塊及矽通孔； (c) 薄化該晶圓之背侧； ⑷將切割膠帶安裝至該薄化晶圓之該背側並將該石夕 晶圓及切割膠帶安裝至切割框； (e)移除該背研磨膠帶； ⑴提供預切割成該晶圓之形狀的底部填充材料； (g)使該底部填充料盘該晶 層壓至該晶圓。對準並將該底部填充料 16l796.doc
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