TW201320073A - Stable SRAM bitcell design utilizing independent gate FinFET - Google Patents

Abstract

Stable SRAM cells utilizing Independent Gate FinFET architectures provide improvements over conventional SRAM cells in device parameters such as Read Static Noise Margin (RSNM) and Write Noise Margin (WNM). Exemplary SRAM cells comprise a pair of storage nodes, a pair of bit lines, a pair of pull-up devices, a pair of pull-down devices and a pair of pass-gate devices. A first control signal and a second control signal are configured to adjust drive strengths of the pass-gate devices, and a third control signal is configured to adjust drive strengths of the pull-up devices, wherein the first control signal is routed orthogonal to a bit line direction, and the second and third control signals are routed in a direction same as the bit line direction. RSNM and WNM are improved by adjusting drive strengths of the pull-up and pass-gate devices during read and write operations.

Description

Stable Static Random Access Memory Bit Grid Design Using Independent Gate Fin Field Effect Transistor

The disclosed embodiments relate to static random access memory (SRAM) bit cells. More specifically, the illustrative embodiments relate to highly stable SRAM cells using a separate gate fin field effect transistor (FinFET) (IG-FinFET) architecture.

SRAM is typically used in applications where speed and low power are a consideration. SRAM cells are fast and do not require dynamic updates, as in the case of dynamic random access memory (DRAM) cells. The structure of a conventional SRAM cell comprises two cross-coupled inverters typically formed of four complementary metal oxide semiconductor field effect transistors (complementary MOSFETs or CMOS transistors). The cross-coupled inverter forms a basic storage element having two stable states representing complementary binary values "0" and "1". Two additional transistors (referred to as "access transistors") are used to control access to the storage elements during read and write operations. Therefore, the conventional SRAM cell architecture involves six transistors and is commonly referred to as a 6T SRAM cell.

Figure 1 illustrates a conventional 6T SRAM cell 100. The storage element contains transistors M1 to M4. Nodes Q and QC maintain complementary binary values. The write operation on cell 100 is initiated by driving word line WL to positive supply voltage VDD. Access transistors M5 and M6 transfer the values on the complementary bit lines BL and BLC to the storage element. In a read operation, both BL and BLC are precharged to a predefined value or are floating. Once the word line is activated, the complementary value stored in the storage element is used to discharge one of the bit lines. A sense amplifier (not shown) quickly drives the value on the discharged bit line to the negative supply voltage VSS and correspondingly drives the complementary bit line to VDD accordingly.

MOSFETs used in conventional SRAM architectures suffer from short channel effects, such as increased sub-limit leakage currents, as the device size is reduced. In addition, when the supply voltage and the threshold voltage are lowered to keep the power consumption low, the stability of the data stored in the SRAM cell is affected. In order to resist the shortcomings of conventional MOSFET structures, multi-gate field effect transistors (MuGFETs) have been discussed in the past. MuGFETs have more than one gate in a single device such that multiple gates can be controlled by a single gate electrode. The channel in the multi-gate device is surrounded by a plurality of gates, resulting in suppression of leakage current and corresponding reduction in power consumption. Although the conventional MOSFET is flat, the multi-gate device is a non-flat structure.

The FinFET is a multi-gate device in which the channel is wound around a thin "fin" that forms the body of the device (rather than a flat Si surface). The size of the fin determines the effective channel length of the device. The short channel effect is suppressed by making the fins very narrow. A separate gate (IG) FinFET is similar to two single gate MOSFETs that share a parallel connection of a common body.

Several parameters are related to the stability of the study SRAM lattice. Although the parameters were originally explained with respect to the conventional SRAM cell of Figure 1, it can be easily extended to the IG-FinFET SRAM structure. Transistors M2 and M4 include a pull up (PU) logic that enables storage nodes Q and QC to be pulled up to the positive supply voltage VDD. Similarly, transistors M1 and M3 contain pull-down (PD) logic to connect nodes Q and QC to a negative supply voltage VSS (VSS can be connected to ground). Access transistors M5 and M6 are also referred to as pass gate (PG) transistors. The relative strength of the PU, PD, and PG components of the SRAM cell determines factors such as the writeability of the cell and the stability of the data. In general, the strength of a transistor refers to the amount of current flowing through the device and is proportional to the size of the transistor and the gate voltage of the transistor.

Leakage current, voltage disturbances, switching activity on adjacent cells, and other system noise have an effect on the stability of the data in the SRAM cell. Sometimes the noise may be high enough that the data stored in the grid "flips" to an error state, even if the particular cell is not selected for reading or writing. The minimum DC voltage disturbance required to flip or flip the state of the grid is known as Static Noise Tolerance (SNM). Keep Static Noise Tolerance (HSNM) refers to the SNM of the cell in hold or standby mode. Referring to Figure 1, increasing the VDD grid voltage generally has the effect of increasing the HSNM.

The parameter "α" indicates the ratio of the strength of the PG to the PU (indicated as "PG/PU"). It can be seen that reducing the PU intensity and increasing the PG intensity allows the values on the BL and BLC to be easily written into the storage node. Write Static Noise Tolerance (WNM) refers to the SNM of the cell in write mode. Therefore, the WNM of the SRAM circuit varies proportionally with α. The WNM can be improved by adding PG and/or reducing the PU as indicated by α(=PG/PU).

The parameter "β" indicates the ratio of the strength of the PD to the PG (denoted as "PD/PG"). It can be seen that reducing the PG intensity and increasing the PD intensity allows the values on Q and QC to be easily read into the bit line. Read Static Noise Tolerance (RSNM) refers to the SNM of the cell in read mode. The RSNM of the SRAM circuit varies proportionally with β. The RSNM can be improved by increasing the PD and/or decreasing the PG as indicated by β(=PD/PG).

From the foregoing discussion, it should be understood that varying the strength of the PU, PD, and PG components involves complex trade-offs between the HSNM, RSNM, and WNM. Figure 2A illustrates a conventional tying gate SRAM (TG-SRAM) cell. The TG-SRAM cell has the basic structure of a dual gate SRAM (DG-SRAM) cell. Two of the double gates of each transistor in the TG-SRAM are tied together, and thus the operation of the TG-SRAM cell is similar to the operation of the conventional 6T SRAM of FIG.

The technique for increasing the stability of the lattice by the feedback mechanism to the gate after the PG device is proposed by Guo et al., "FinFET-Based SRAM Design" ( Sym. ISLPED , 2005, pages 2 to 7) (below) In the case of "Guo", this document is incorporated herein by reference. Guo uses a FinFET-based SRAM cell to achieve better control of the gate and lower sub-limit leakage current (as noted above). Guo tried to improve the lattice beta ratio by controlling the gate after the PG device. The gate after the PG device is controlled by connecting the storage node to the back gate (as illustrated in Figure 2B) to improve the RSNM. However, connecting the storage node to the back gate degrades the WNM by reducing the lattice alpha ratio. In order to improve the WNM, Guo proposes to lower the voltage VDD grid.

Figure 3 illustrates a schematic diagram of an SRAM array formed from the cells of Guo. The bit lines BL and BLB are shown in FIG. 3 as being disposed in the vertical direction, and the word lines WL are disposed in the horizontal direction. During the write operation, the VDD grid connected to the "selected" BL and BLB cells is lowered, thereby reducing the PU drive strength. Therefore, the alpha ratio (PG/PU) of the selected lattice is improved.

However, the semi-selected cell in Figure 3 The VDD grid (horizontal selected and vertically unselected) is also reduced, which has a lower for semi-selected cells The effect of HSNM. Therefore, although Guo tried to improve the RSNM of the SRAM cell, the HSNM deteriorated. Therefore, there are two disadvantages in the design of Guo. First, controlling the VDD grid is very difficult and suffers from a large number of variations in the SRAM array. Second, lowering the VDD grid has the effect of reducing HSNM (as noted above).

Figure 7 illustrates a butterfly transfer curve (BTC) for the RSNM values of the conventional TG-SRAM cell and the SRAM cell of Guo. BTC is a plot of the storage node voltage during the write operations of "0" and "1". The SNM is measured by fitting to the largest square inside the BTC. As indicated by Figure 7, the Guo circuit provides an improvement of 85.4 mv RSNM compared to the conventional TG-SRAM circuit. Figure 8 similarly illustrates the BTC of the WNM for the conventional TG-SRAM circuit and the circuit of Guo. It can be observed that the WNM is improved by 34.1 mv due to the reduction of the VDD grid voltage. Figure 9 illustrates a BTC for the conventional TG-SRAM and HSNM values for the circuitry of Guo. It is observed that the HSNM of the half-selected cell of Guo is 41.4 mv lower than the HSNM of the conventional TG-SRAM cell.

It has been proposed in "An Independent-Gate FinFET SRAM Cell for High Data Stability and Enhanced Integration Density" ( IEEE SOC Conference, 2007, pages 68 to 69) (hereinafter "Liu") of Liu et al. An alternative to the problem of the conventional TG-SRAM and Guo is incorporated herein by reference. Liu's SRAM grid is illustrated in Figure 4. Liu uses a FinFET-based structure in which each of the PU, PD, and PG components uses two transistors with independently controllable gates. This situation provides improved control over their individual strengths.

Liu uses control signals "RW" and "W" (as shown in Figure 4) instead of conventional word line control signals (e.g., WL in Figure 1) to control read and write operations. The signal RW is held high during both the read and write operations, while the signal W is only high during the write operation. Therefore, during reading, RW is high and W is low. Thus, during reading, PG1 and PG2 conduct, but by the intensity of only one of the two transistors in each pair (pre-transistor), PG can be maintained at a low value. The PD and PU (i.e., PD1, PD2, PU1, and PU2) are maintained at a constant value, and thus β (= PD / PG) is increased, and the RSNM of the cell is correspondingly high.

In Liu, during a write operation, both RW and W are high, thereby causing two of each pair of PG1 and PG2 to conduct. It will be seen that in this mode, the relative strength of the PU, PD and PG components of the cell is similar to the relative strength of the conventional SRAM, since each component in the Liu is essentially replaced by a pair of transistors (as is known Compared to a single transistor in SRAM). Therefore, the ratio α (= PG / PU) is equivalent to the α of the conventional TG-SRAM, and correspondingly, there is no improvement in the WNM of Liu. In the standby mode, both the RW signal and the W signal remain low, and thereby the HSN of Liu is the same as the HSNM of the conventional TG-SRAM.

While these techniques provide an improvement in one or both of these parameters, the cost is a deterioration of the remaining parameters and/or a lack of improvement. Accordingly, there is a need in the art for techniques to improve the SNM of an SRAM circuit in a read and write mode of operation without degrading the stability in the standby mode of operation.

The illustrative embodiments are systems and methods for highly stable SRAM cells for use with a separate gate FinFET (IG-FinFET) architecture. The exemplary embodiments of the SRAM cells provide improved stability over conventional SRAM cells (as evidenced by parameters such as RSNM and WNM) without degrading the HSNM.

For example, an exemplary implementation relates to an SRAM cell that includes: a pair of storage nodes configured to store complementary binary values; a pair of bit lines configured to complement the complementary bits The binary values are transmitted to/from the storage nodes to transmit the complementary binary values; a pair of pull-up devices configured to couple the storage nodes to the positive power supply voltage; a pair of pull-downs a device configured to couple the storage nodes to a negative power supply voltage; a pair of pass gate devices configured to couple the storage nodes to the bit lines; a first control signal And a second control signal configured to adjust a driving strength of the pass gate device, wherein the first control signal is sent in one direction orthogonal to a bit line direction, and the second control The signal is delivered in the same direction as the direction of the bit line; and a third control signal is used to adjust the driving strength of the pull-up device, wherein the third control signal is associated with the bit line The direction is the same in one direction.

Another illustrative embodiment is directed to a method of forming an SRAM cell, comprising: configuring a pair of storage nodes to store complementary binary values; coupling a pair of bit lines to the storage nodes to complement the pixels Transmitting a binary value to/from the storage nodes to transmit the complementary binary values; coupling a pair of pull-up devices to the storage nodes to connect the storage nodes to a positive power supply voltage; a pair of pull down devices coupled to the storage nodes to connect the storage nodes to a negative power supply voltage; a pair of pass gate devices coupled to the storage nodes to connect the storage nodes to the bit lines Coupling a first control signal and a second control signal to the pass gate devices for adjusting the driving strength of the pass gate devices, wherein the first control signal is one of orthogonal to a bit line direction Transmitting in a direction, and the second control signal is sent in one direction in the same direction as the bit line direction; and coupling a third control signal to the pull-up devices to adjust the pull-up devices drive Degrees, wherein the third control signal lines routed in the same direction, one of the bit line direction.

Yet another illustrative embodiment relates to an SRAM cell comprising: a storage component for storing a complementary binary value; and a bit line access component for transmitting the complementary binary value to the storage component/ Transmitting the complementary binary values from the storage member; a pull-up member for coupling the storage member to a positive power supply voltage; and a pull-down member for coupling the storage member to a negative power supply voltage; a shutter member for coupling the storage member to the bit line access member; a first control member and a second control member for adjusting a driving strength of the passing gate member, wherein the first control The component is delivered in one direction orthogonal to a direction of the one-dimensional line, and the second control member is delivered in one direction the same as the direction of the bit line; and a third control member is used for The driving strength of the pull-up member is adjusted, wherein the third control member is delivered in the same direction as the direction of the bit line.

Another illustrative embodiment is directed to a method of forming an SRAM cell, comprising: a step of configuring a pair of storage nodes to store a complementary binary value; and coupling a pair of bit lines to the storage a step of transmitting, by the node, the complementary binary values to/from the storage nodes; and coupling a pair of pull-up devices to the storage nodes to a step of connecting a storage node to a positive power supply voltage; a step of coupling a pair of pull-down devices to the storage nodes to connect the storage nodes to a negative power supply voltage; for coupling a pair of pass gate devices a step of connecting to the storage nodes to connect the storage nodes to the bit lines; coupling a first control signal and a second control signal to the pass gate devices for adjusting the pass gate devices a step of driving strength, wherein the first control signal is delivered in one direction orthogonal to a one-dimensional line direction, and the second control signal is delivered in one direction in the same direction as the bit line direction ;and The third control signal to a pull-up device is coupled to such a step in order to adjust the drive strength of the pull means those wherein the third control signal lines routed in the same direction, one of the bit line direction.

The accompanying drawings are included to illustrate the embodiments of the embodiments

Aspects of the invention are disclosed in the following description of the specific embodiments and the accompanying drawings. Alternative embodiments may be devised without departing from the scope of the invention. In other instances, well-known elements of the various embodiments are not described in detail, or such elements may be omitted in order to avoid obscuring the details of the various embodiments.

The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. Also, the term "embodiment" does not require that all embodiments include the features, advantages, or modes of operation discussed.

The terminology used herein is for the purpose of the description and the embodiments As used herein, the singular forms "" It is to be understood that the terms "comprises" and "comprises" and "includes" are used in the context of the specification and the meaning The presence or addition of other features, integers, steps, operations, components, components, and/or groups thereof.

In addition, many of the embodiments are described in terms of sequences of actions to be performed by, for example, elements of a computing device. It will be appreciated that various actions described herein can be performed by a particular circuit (e.g., an application specific integrated circuit (ASIC)), by program instructions being executed by one or more processors, or by a combination of the two. . In addition, it is contemplated that such sequences of actions described herein are fully embodied in any form of computer readable storage medium having a set of corresponding computer instructions stored therein, the instructions being executed The associated processor is caused to perform the functionality described herein. Various aspects of the various embodiments can be embodied in many different forms, and all such forms are intended to be within the scope of the claimed subject matter. Moreover, for each of the embodiments described herein, a corresponding form of any such embodiments can be described herein as, for example, "logic configured to perform the described acts."

As previously described, prior art techniques such as Guo attempted to improve RSNM by controlling the gate after the PG circuit in the SRAM cell, but at the expense of reducing the HSNM (due to the reduced VDD lattice used to protect the WNM from degradation). Voltage). On the other hand, Liu improved the RSNM during the read operation, but did not improve the WNM. Thus, the exemplary embodiments relate to improved RSNM and WNM while substantially protecting the HSNM from degradation.

Figure 5 illustrates an exemplary embodiment. As shown in FIG. 5, SRAM cell 50 includes independently controllable PU, PD, and PG circuits. Each of these circuits includes a pair of transistors formed by an IG-FinFET having independently controllable gates. The control signal "SW" controls the gate potential after the IG-FinFET in the PU devices PU51 and PU52. Signal SW is high during the standby and write modes of operation.

The control signal "RW" controls the gate potential before the IG-FinFET in the PG devices PG51 and PG52. The control signal "W" controls the other transistors (back gate) of the two pairs. Signal RW is high during read and write operations, while signal W is only high during write operations.

The write operation in SRAM 50 continues by driving all three signals SW, RW, and W high. Driving the SW high has the effect of having a gate after disconnecting the IG-FinFET transistors of PU51 and PU52. Therefore, the front gate is conducted during the write operation and the PU intensity of the cell is correspondingly reduced. On the other hand, the two transistors of the PG devices PG51 and PG52 are conducted during writing. Therefore, in the case where the PG intensity is maintained at a high value and the PU intensity is lowered, the ratio α (= PG / PU) of the circuit and the corresponding WNM increase. Therefore, the SRAM 51 achieves high WNM and improved writability in the write mode.

During the read operation, the signal RW is high while driving both SW and W low. Therefore, only the gates of PG51 and PG52 are "on" before, thereby reducing the strength of the PG without changing the strength of the PD and the PU. Therefore, β (= PD / PG) increases, and correspondingly, the RSNM of the SRAM cell also increases.

In the standby mode, SW is high and RW and W are kept low. Therefore, the gates of PU51 and PU52 are turned off, thereby reducing the strength of the PU. Because RW and W are low, PG devices PG51 and PG52 are not conducting and isolate the SRAM storage elements from the bit lines. Since the driving strength of the PU is only slightly reduced, the HSNM degradation is not significant.

Figure 6 illustrates an SRAM array comprising cells in accordance with an illustrative embodiment described in the preceding section. The bit lines BL and BLB as illustrated are disposed in the vertical direction. The control signals SW and W are delivered in the same direction as the bit line (hereinafter referred to as the "vertical" direction). The control signal RW is delivered in a direction orthogonal to the bit line (hereinafter referred to as a "horizontal" direction). SRAM cell 60 is a selected cell during an exemplary write operation. The grid 62 is horizontally selected and vertically unselected, and the grid 64 is vertically selected and the level is not selected. Cells 62 and 64 are referred to as "semi-selected cells." The grid 62 operates in the read mode of operation and is in a hold condition. The binary values "0" and "1" are indicated during the read and write operations. The value "f1" refers to the floating voltage value "1", and "D, D'" is used to indicate the complementary data value. The illustrative embodiment advantageously avoids the problems associated with the semi-selected cells by vertically delivering control signals SW and W.

Focusing on the grid 62, the bit line floats, which is because the line to which the cell belongs is not selected. The signal RW is horizontally delivered as previously described, and thus RW is driven high for both the selected cell 60 and the half selected cell 62 during a write operation. However, for grid 62, signals SW and W are maintained low because the grid is not in the selected row. While the prior art will subject the grid 62 to a semi-selective read problem, the illustrative embodiments avoid this problem. Since SW and W are low and only RW is high, the intensity of the PG device of cell 62 is reduced. Therefore, α is low and therefore the RSNM of cell 62 is high. In other words, the cell is stable during the read operation and prevents erroneous read operations.

For grid 64, SW and W are high because this is driven vertically and the grid is in the selected row, but RW is low. Therefore, the gate is slightly conducted only after each PG device, and the p-channel PU device is also slightly weakened. However, the current flowing through the PG device is negligible under this condition, and the slightly weakened PU device does not have a significant impact on the HSNM. Therefore, the unselected cells 64 are prevented from being affected by the semi-selection problem in the exemplary embodiment.

In summary, the exemplary embodiments described above improve WNM and RSNM, while the HSNM of the circuit does not suffer degradation. A comparison of all three SNM parameters RSNM, WNM, and HSNM between the SRAM circuit of Liu and the exemplary embodiment of SRAM cell 50 is illustrated in the table of FIG.

In Figure 10, Liu has two different terms for RSNM (RSNM1 and RSNM2), while cell 50 has three different terms for HSNM (HSNM1, HSNM2, and HSNM3). The signal "SW" is high in both the standby mode and the write operation. Therefore, during the write operation, the gate after the PU is turned off while the PG is fully turned on. Due to the weakened driving strength of the PU, the alpha ratio is increased and thus the WNM of the lattice 50 is improved (compared to the conventional TG-SRAM and the WNM of Liu).

During the read operation, the PG operates in the same manner as Liu. On the other hand, the SW is low and therefore the gates are turned on after the two PUs, resulting in leakage current through a PU that is only turned on by the back gate. However, the leakage current is negligible and does not interfere with normal read operations. Therefore, the RSNM of the cell 50 is equivalent to the RSNM1 of Liu.

During the standby mode, the SW is high, and thus the gate is turned off after the PU. Due to the weakened drive strength of the PU, the static noise tolerance (HSNM) of the cell 50 is slightly degraded (compared to the HSNM of the conventional TG-SRAM). However, as described below, HSNM degradation is negligible.

The possessives are classified into four different conditions: selected cells (SLC), horizontally selected and vertically semi-selected cells (HSLC 1), vertically selected and horizontally semi-selected cells (HSLC 2), and unselected cells (USLC), as shown in Figure 10. Shown in . In contrast to Liu, the W is placed vertically and only high if BL is selected. Since W is low for HSLC 1 (box 62), the RSNM for HSLC 1 (box 62) during the write operation is the same as the RSNM during the read operation. Therefore, during the write operation, for HSLC 1, cell 50 does not suffer from RSNM degradation. During read and write operations, the stability of HSLC 2 and USLC is evaluated by HSNM because the PG is completely or partially turned on by the back gate. The HSNM2 for the USLC during the read and write operations and the HSNM3 for the HSLC 2 during the write operation are almost identical to the HSNM1 during the standby mode. These results are also illustrated in the graph of Figure 11. Thus, the illustrative embodiments achieve stability and high noise margin during read, write, and standby modes of operation of the operation.

It should be appreciated that the embodiments include various methods for performing the procedures, functions, and/or algorithms disclosed herein. For example, as illustrated in FIG. 12, an embodiment can include a method of forming an SRAM cell that includes configuring a pair of storage nodes to store complementary binary values (block 1202). Next, at block 1204, a pair of bit lines are coupled to the storage node to transmit the complementary binary value to the storage node/self storage node to transmit the complementary binary value. At block 1206, a pair of pull up devices are coupled to the storage node to connect the storage node to the positive power supply voltage. Proceeding to block 1208, a pair of pull down devices are coupled to the storage node to connect the storage node to the negative power supply voltage, and at block 1210, a pair of pass gate devices are coupled to the storage node to place the storage node Connect to the bit line. Next, at block 1212, the first control signal and the second control signal are coupled to the pass gate device for adjusting the driving strength of the pass gate device, wherein the first control signal is horizontally delivered, and the second control The signal is sent vertically. Finally, at block 1214, a third control signal is coupled to the pull up device to adjust the drive strength of the pull up device, wherein the third control signal is delivered vertically.

Those skilled in the art will appreciate that information and signals can be represented using any of a variety of different technologies and techniques. For example, the materials, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the above description may be by voltage, current, electromagnetic wave, magnetic field or magnetic particle, light field or light particle, or any combination thereof. Said.

In addition, those skilled in the art will appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the embodiments disclosed herein can be implemented as an electronic hardware, a computer software, or a combination of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Implementing this functionality as hardware or software depends on the particular application and design constraints imposed on the overall system. The described functionality may be implemented in varying ways for each particular application, and such implementation decisions should not be interpreted as causing a departure from the scope of the invention.

The methods, sequences and/or algorithms described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of both. The software module can reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, scratchpad, hard disk, removable disk, CD-ROM, or any of the techniques known in the art. Other forms of storage media. The exemplary storage medium is coupled to the processor such that the processor can read information from the storage medium and write the information to the storage medium. In the alternative, the storage medium can be integrated into the processor.

Thus, embodiments can include a computer readable medium embodying a method for using an (IG-FinFET) architecture in a highly stable SRAM architecture. Thus, the various embodiments are not limited to the illustrated examples, and any means for performing the functionality described herein are included in the embodiments.

Embodiments of the invention may be suitably employed in any device including active integrated circuits (including memory) and on-wafer circuits for testing and characterization.

The apparatus and methods disclosed above are typically designed and configured to store GDSII and GERBER computer files on a computer readable medium. These files are in turn provided to the manufacturer of the manufacturing device based on such files. The resulting product is a semiconductor wafer that is subsequently diced into semiconductor dies and packaged into a semiconductor wafer. The wafers are then used in the apparatus described above.

While the foregoing disclosure shows illustrative embodiments, it should be noted that various changes and modifications may be made herein without departing from the scope of the invention as defined by the appended claims. The functions, steps, and/or actions of the method claims in accordance with the embodiments described herein are not required to be performed in any particular order. In addition, although the elements of the various embodiments may be described or claimed in the singular, the

50. . . Static random access memory (SRAM) cell

60. . . Static random access memory (SRAM) cell

62. . . grid

64. . . grid

BL. . . Bit line

BLB. . . Bit line

BLC. . . Bit line

M1. . . Transistor

M2. . . Transistor

M3. . . Transistor

M4. . . Transistor

M5. . . Access transistor

M6. . . Access transistor

PD1. . . Pulldown (PD) logic

PD2. . . Pulldown (PD) logic

PG1. . . Pass brake

PG2. . . Pass brake

PG51. . . Pass gate (PG) device

PG52. . . Pass gate (PG) device

PU1. . . Pull-up (PU) logic

PU2. . . Pull-up (PU) logic

PU51. . . Pull-up (PU) device

PU52. . . Pull-up (PU) device

Q. . . node

QC. . . node

WL. . . Word line

Figure 1 illustrates a conventional SRAM cell.

Figure 2A illustrates a conventional TG-SRAM cell.

Figure 2B illustrates the SRAM cell of Guo according to the prior art.

Figure 3 illustrates an SRAM array of Guo according to the prior art.

Figure 4 illustrates the IG-FinFET SRAM cell design of Liu according to the prior art.

FIG. 5 illustrates an IG-FinFET SRAM cell in accordance with an illustrative embodiment.

FIG. 6 illustrates an SRAM array including cells in accordance with an exemplary embodiment in which the semi-selection problem is avoided.

Figure 7 illustrates a BTC for comparing a conventional TG-SRAM with an RSNM value according to the SRAM of Guo.

Figure 8 illustrates a BTC for comparing a conventional TG-SRAM with a WNM value according to the SRAM of Guo.

Figure 9 illustrates a BTC for comparing a conventional TG-SRAM with an HSNM value according to the SRAM of Guo.

Figure 10 illustrates a graph comparing conventional RS-SRAM, RSNM, WNM, and HSNM values according to prior art designs and exemplary embodiments of Liu.

Figure 11 illustrates a bar graph of the values shown in the table of Figure 10.

12 is a flow chart illustrating a method of forming an SRAM cell, in accordance with an illustrative embodiment.

50. . . Static random access memory (SRAM) cell

PG51. . . Pass gate (PG) device

PG52. . . Pass gate (PG) device

PU51. . . Pull-up (PU) device

PU52. . . Pull-up (PU) device

Claims (32)

A static random access memory (SRAM) cell comprising: a pair of storage nodes configured to store complementary binary values; a pair of bit lines configured to transmit the complementary binary values Transmitting/removing the complementary binary values from the storage nodes; a pair of pull-up devices configured to couple the storage nodes to a positive power supply voltage; a pair of pull-down devices Configuring to couple the storage nodes to a negative power supply voltage; a pair of pass gates configured to couple the storage nodes to the bit lines; a first control signal and a second Control signals configured to adjust the drive strength of the pass gate devices; and a third control signal for adjusting the drive strength of the pull up devices. The SRAM cell of claim 1, wherein the pull-up devices, the pull-down devices, and the pass-through devices comprise a pair of IG-FinFET transistors. The SRAM cell of claim 2, wherein the first control signal is maintained in a high voltage state during a read operation and a write operation; the second control signal is maintained in a high voltage state during a write operation; And the third control signal is maintained in a high voltage state during an inactive mode and a write operation. The SRAM cell of claim 3, wherein in a read operation, the driving strength of the pass gate device is reduced to improve a read static noise margin parameter. The SRAM cell of claim 3, wherein in a write operation, the driving strength of the pull-up devices is reduced to improve a write noise tolerance parameter. The SRAM of claim 1, wherein the first control signal is sent in a direction orthogonal to a direction of a bit line, and the second control signal and the third control signal are in the bit line The direction is the same in one direction. The SRAM cell of claim 1 is integrated in at least one semiconductor die. The SRAM cell of claim 1 is integrated into a device selected from the group consisting of: a set-top box, a music player, a video player, an entertainment unit, a navigation device, a communication device, and a personal digital assistant ( PDA), fixed location data unit, and a computer. A method of forming a static random access memory (SRAM) cell, comprising: configuring a pair of storage nodes to store complementary binary values; coupling a pair of bit lines to the storage nodes to complement the pixels Transmitting a binary value to/from the storage nodes to transmit the complementary binary values; coupling a pair of pull-up devices to the storage nodes to connect the storage nodes to a positive power supply voltage; a pair of pull down devices coupled to the storage nodes to connect the storage nodes to a negative power supply voltage; a pair of pass gate devices coupled to the storage nodes to connect the storage nodes to the bit lines Coupling a first control signal and a second control signal to the pass gate devices for adjusting the driving strength of the pass gate devices; and coupling a third control signal to the pull-up devices to adjust the The driving strength of the pull-up device. The method of claim 9, comprising forming the pull-up devices, the pull-down devices, and the pass-through devices using a pair of IG-FinFET transistors. The method of claim 10, comprising maintaining the first control signal in a high voltage state during a read operation and a write operation; maintaining the second control signal at a high voltage during a write operation a state; and maintaining the third control signal in a high voltage state during an inactive mode and a write operation. The method of claim 11, comprising reducing the drive strength of the pass gate device during a read operation, thereby improving a read static noise margin parameter. The method of claim 11, comprising reducing the drive strength of the pull-up devices during a write operation, thereby improving a write noise tolerance parameter. The method of claim 9, wherein the first control signal is sent in one direction orthogonal to a one-dimensional line direction, and the second control signal and the third control signal are in a direction opposite to the bit line Deliver in the same direction. The method of claim 9, wherein the SRAM cell is integrated in at least one of the semiconductor dies. The method of claim 9, wherein the SRAM cell is integrated into a device selected from the group consisting of: a set-top box, a music player, a video player, an entertainment unit, a navigation device, a communication device, and a personal digital device. Assistant (PDA), fixed location data unit, and a computer. A static random access memory (SRAM) cell, comprising: a storage component for storing a complementary binary value; and a bit line access component for transmitting the complementary binary value to the storage component/ Transmitting the complementary binary values from the storage member; a pull-up member for coupling the storage member to a positive power supply voltage; and a pull-down member for coupling the storage member to a negative power supply voltage; a shutter member for coupling the storage member to the bit line access member; a first control member and a second control member for adjusting a driving strength of the passing gate member; and a third control A member for adjusting the driving strength of the pull-up member. The SRAM cell of claim 17, wherein the pull up member, the pull down member, and the pass gate member comprise a pair of IG-FinFET transistors. The SRAM cell of claim 18, wherein the first control component is maintained in an active high state during a read operation and a write operation; the second control component maintains an active high state during a write operation And the third control member is maintained in an active high state during an inactive mode and a write operation. The SRAM cell of claim 18, wherein in a read operation, the drive strength of one of the pass gate members is reduced to improve a read static noise tolerance parameter. The SRAM cell of claim 18, wherein in a write operation, one of the pull-up members has a reduced drive strength to improve a write noise tolerance parameter. The SRAM cell of claim 17, wherein the first control component is delivered in one direction orthogonal to a bit line direction, and the second control component and the third control component are tied to the bit line The direction is the same in one direction. The SRAM cell of claim 17 is integrated into at least one of the semiconductor dies. The SRAM cell of claim 17 is integrated into a device selected from the group consisting of: a set-top box, a music player, a video player, an entertainment unit, a navigation device, a communication device, and a personal digital assistant ( PDA), fixed location data unit, and a computer. A method of forming a static random access memory (SRAM) cell, comprising: a step of configuring a pair of storage nodes to store complementary binary values; and coupling a pair of bit lines to the storage a step of transmitting, by the node, the complementary binary values to/from the storage nodes; and coupling a pair of pull-up devices to the storage nodes to a step of connecting a storage node to a positive power supply voltage; a step of coupling a pair of pull-down devices to the storage nodes to connect the storage nodes to a negative power supply voltage; for coupling a pair of pass gate devices a step of connecting to the storage nodes to connect the storage nodes to the bit lines; coupling a first control signal and a second control signal to the pass gate devices for adjusting the pass gate devices a step of driving strength; and a step of coupling a third control signal to the pull-up devices to adjust the driving strength of the pull-up devices. The method of claim 25, comprising the steps of forming the pull-up devices, the pull-down devices, and the pass-through devices using a pair of IG-FinFET transistors. The method of claim 26, comprising the step of maintaining the first control signal in a high voltage state during a read operation and a write operation; for controlling the second control during a write operation The step of maintaining the signal in a high voltage state; and the step of maintaining the third control signal in a high voltage state during an inactive mode and a write operation. The method of claim 27, comprising the step of reducing the drive strength of the pass gate device during a read operation, thereby improving a read static noise margin parameter. The method of claim 27, comprising the step of reducing the drive strength of the pull-up devices during a write operation, thereby improving a write noise tolerance parameter. The method of claim 25, wherein the first control signal is sent in one direction orthogonal to a one-dimensional line direction, and the second control signal and the third control signal are in a direction opposite to the bit line Deliver in the same direction. The method of claim 25, wherein the SRAM cell is integrated in at least one of the semiconductor dies. The method of claim 25, wherein the SRAM cell is integrated into a device selected from the group consisting of: a set-top box, a music player, a video player, an entertainment unit, a navigation device, a communication device, and a personal digital device. An assistant (PDA), a fixed location data unit, and a computer, the SRAM cell is integrated into the device.